CN104241472A - 一种能减低位错密度的led芯片生长方法 - Google Patents
一种能减低位错密度的led芯片生长方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 8
- 239000010980 sapphire Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
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- 238000005516 engineering process Methods 0.000 claims description 10
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- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
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- 238000001312 dry etching Methods 0.000 claims description 4
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- 238000001704 evaporation Methods 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
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- 229910052719 titanium Inorganic materials 0.000 claims 1
- 238000000407 epitaxy Methods 0.000 abstract description 2
- 230000003139 buffering effect Effects 0.000 abstract 2
- 238000001194 electroluminescence spectrum Methods 0.000 abstract 2
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- 238000002474 experimental method Methods 0.000 abstract 1
- 230000007773 growth pattern Effects 0.000 abstract 1
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- 208000012868 Overgrowth Diseases 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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- 239000000725 suspension Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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Abstract
本发明设计一种在金属热沉上制备功率型LED芯片及其制备方法，具体步骤为：在蓝宝石衬底(300)上生长GaN缓冲层(310)，在缓冲层上蒸镀透明电极Ni/Au(320)；在透明电极上蒸镀Ni/Ag/Ti/Au反射层(330)；在反射层上电镀平整的、周期性的金属热沉单元(340)，厚度在50μm左右，间隔在50μm左右；在金属热沉上生长LED外延片，生长方式是侧向外延，这种方式生长的LED外延片，位错密度明显降低，从而提高了外延片的晶体品质，相应的光学、电学性能也得到改善，实验证实，阴极荧光谱(CL谱)和电致发光谱(EL谱)强度都有增强。
Description
技术领域
本发明涉及到GaN基功率型发光二极管(LED)芯片的制备方法，尤其涉及一种能减低位错密度的LED芯片的制备方法。采用特殊工艺及GaN基侧向外延技术。
背景技术
近年来，以GaN和SiC为代表的第三代宽禁带半导体材料受到人们广泛关注和大力研究，尤其是III-V族氮化物半导体材料以及与它们相关的合金和异质结材料，在高温、高频大功率器件方面具有很大的优势。
目前，高亮度的蓝绿LED已经研制成功，但是高的穿透位错密度的存在限制了这些器件性能的进一步提高，因此在实现高性能的LED方面能否取得突破性进展，降低GaN位错密度至关重要。
GaN基半导体有一些严重缺陷，其GaN基LED位错密度104-1010cm-2。且GaN基LED的内量子效率主要受位错密度、多量子阱中压电场合量子阱横向形状等影响，通过降低位错密度和极化效应来最大限度增加LED的内量子效率。
GaN和蓝宝石之间存在很大的晶格失配和热失配，通常先在衬底上生长晶格常数渐变或者突变的缓冲层，然后在外延生长GaN。尽管缓冲层技术已很成熟，但用此技术生长得到的GaN薄膜仍具有很高的位错密度，对器件性能影响很大。
本发明在外延生长GaN前，先生长一层图形化的金属热沉，再采用侧向外延技术可有效降低外延层的位错密度。
早期采用侧向外延技术首先是在蓝宝石衬底上生长一定厚度的GaN，之后中断生长，将样品从反应室中取出，再在GaN上制备具有周期性的掩膜图形，采用SiO2作为掩膜层材料，而后将样品放回反应室继续生长，直至获得表面平整的薄膜。这种技术的特点是需间断生长，不利于节省时间，降低成本，而且将样品从反应室取出进行掩膜处理，不可避免地对样品造成污染。为了避免这些缺点，出现了简便可行的悬挂外延的外延方法。该方法首先利用干法刻蚀技术将蓝宝石衬底制备成具有周期性条纹的图形衬底，形成台面和凹槽，之后用于生长GaN。
发明内容
本发明的目的是提供一种能降低位错密度的LED芯片的制备方法，外延片自下而上依次包括蓝宝石衬底、GaN缓冲层、N型电极、反射层、图形化金属热沉、N型GaN、有源层、P型GaN、P型电极。
本发明先在蓝宝石衬底上利用MOCVD生长GaN缓冲层、N型电极、反射层；接着生长一层金属层(50μm以上)，利用干法刻蚀技术将这层金属层制备成具有周期性条纹的图形化金属层单元，间隔100-200μm，该层金属层可以增加散热作为热沉；然后在图形化金属层的台面和凹槽上生长N型GaN。
生长时金属层的台面和凹槽同时进行，台面N型GaN生长到一定程度就开始侧向外延，在槽中N型GaN没有达到台面高度之前，相邻的侧向外延部分就结合形成表面完整光滑的薄膜。
一种能减低位错密度的LED芯片的制备方法，具体包括以下步骤：
(1)在C面蓝宝石衬底上生长GaN缓冲层；
(2)在GaN缓冲层上蒸镀透明N型电极Ni/Au；
(3)在透明N型电极上蒸镀Ni/Ag/Ti/Au反射层；
(4)在反射层上生长一层厚度在50μm以上的金属层；利用干法刻蚀技术将这层金属层制备成平整的、周期性的金属热沉单元，间隔100-200μm；
(5)在金属热沉上外延生长N型GaN；
(6)在N型GaN上生长有源层，采用四元AlInGaN作为多量子阱层材料；
(7)在有源层上生长P型GaN；
(8)在P型GaN上生长P型电极。
附图说明
图1所示是本发明生长的LED芯片结构图。
Claims (5)
1.一种能减低位错密度的LED芯片，具体结构包括以下部分：
金属热沉厚度大于50微米，表面平整，金属热沉上直接生长N型GaN；
金属热沉下面是反射层，反射层逐层由Ni、Ag、Ti、Au金属组成，Ni联结Ag和透明电极；
反射层下面为透明N型电极，透明N型电极为氧化的Ni和Au组成；
透明N型电极下面是缓冲层；
在金属热沉上生长N型GaN；
在N型GaN上生长有源层，有源层采用多量子阱结构；
有源层上面为P型GaN
P型GaN上面为P型电极，P型电极和P型GaN之间为欧姆接触。
2.一种能减低位错密度的LED芯片的制备方法，具体包括以下步骤：
(1)在C面蓝宝石衬底上生长GaN缓冲层；
(2)在GaN缓冲层上蒸镀透明N型电极Ni/Au；
(3)在透明N型电极上蒸镀Ni/Ag/Ti/Au反射层；
(4)在反射层上生长一层厚度在50μm以上的金属层；利用干法刻蚀技术将这层金属层制备成平整的、周期性的金属热沉单元，间隔100-200μm；
(5)在金属热沉上外延生长N型GaN；
(6)在N型GaN上生长有源层，采用四元AlInGaN作为多量子阱层材料；
(7)在有源层上生长P型GaN；
(8)在P型GaN上生长P型电极。
3.根据权利要求2所述的能减低位错密度的LED芯片的制备方法，其特征在于：镀反射层Ni/Ag/Ti/Au，总厚度在100-200nm，彼此间相互连接，形成导电网络。
4.根据权利要求2所述的能减低位错密度的LED芯片的制备方法，其特征在于反射层上电镀平整的、周期性的金属热沉单元，厚度50μm，单元间间距为100-200μm。
5.根据权利要求2所述的能减低位错密度的LED芯片的制备方法，其特征在于：用CF4处理P型GaN表面，选择Ti/Al/Ni/Au多层结构，总厚度在300-1000nm，得到非合金化的P型GaN的欧姆接触。
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020056840A1 (en) * | 2000-11-16 | 2002-05-16 | United Epitaxy Company, Ltd | Epitaxial growth of nitride compound semiconductor |
| CN101145516A (zh) * | 2007-09-29 | 2008-03-19 | 中国电子科技集团公司第五十五研究所 | 硅基氮化物单晶薄膜的外延结构及生长方法 |
| CN101800278A (zh) * | 2010-01-05 | 2010-08-11 | 山西乐百利特科技有限责任公司 | 一种能减低位错密度的led芯片 |
| CN202797053U (zh) * | 2012-08-23 | 2013-03-13 | 南通同方半导体有限公司 | 一种氮化镓发光二极管结构 |
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- 2013-06-17 CN CN201310238927.4A patent/CN104241472A/zh active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020056840A1 (en) * | 2000-11-16 | 2002-05-16 | United Epitaxy Company, Ltd | Epitaxial growth of nitride compound semiconductor |
| CN101145516A (zh) * | 2007-09-29 | 2008-03-19 | 中国电子科技集团公司第五十五研究所 | 硅基氮化物单晶薄膜的外延结构及生长方法 |
| CN101800278A (zh) * | 2010-01-05 | 2010-08-11 | 山西乐百利特科技有限责任公司 | 一种能减低位错密度的led芯片 |
| CN202797053U (zh) * | 2012-08-23 | 2013-03-13 | 南通同方半导体有限公司 | 一种氮化镓发光二极管结构 |
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