CN104241375A - Straddling type heterojunction resonance tunneling field-effect transistor and preparing method thereof - Google Patents
Straddling type heterojunction resonance tunneling field-effect transistor and preparing method thereof Download PDFInfo
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- CN104241375A CN104241375A CN201410438469.3A CN201410438469A CN104241375A CN 104241375 A CN104241375 A CN 104241375A CN 201410438469 A CN201410438469 A CN 201410438469A CN 104241375 A CN104241375 A CN 104241375A
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- 230000005669 field effect Effects 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000005641 tunneling Effects 0.000 title abstract description 31
- 239000000463 material Substances 0.000 claims description 58
- 239000004065 semiconductor Substances 0.000 claims description 28
- 238000002360 preparation method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 8
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 239000012190 activator Substances 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000002353 field-effect transistor method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 229910052710 silicon Inorganic materials 0.000 description 2
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- 239000013078 crystal Substances 0.000 description 1
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- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/7606—Transistor-like structures, e.g. hot electron transistor [HET]; metal base transistor [MBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66931—BJT-like unipolar transistors, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistor [RTT], bulk barrier transistor [BBT], planar doped barrier transistor [PDBT], charge injection transistor [CHINT]
Abstract
The invention discloses a straddling type heterojunction resonance tunneling field-effect transistor and a preparing method thereof. The tunneling field-effect transistor comprise a tunneling source region, a channel region, a drain region and a control gate above a channel, the energy band structure of the heterogeneous tunnel junction of the tunneling source region and the channel region is a Straddling-Gap. If the field-effect transistor is an N type device, the field-effect transistor is located at the interface of the heterogeneous tunnel junction of the tunneling source region and the channel region, the tunneling source region conduction band bottom is located above the channel region conduction band bottom, and the tunneling source region valence band top is located below the channel region valence band top; if the field-effect transistor is a P type device, the tunneling source region conduction band bottom is located below the channel region conduction band bottom, and the tunneling source region valence band top is located above the channel region valence band top. According to the tunneling field-effect transistor and the preparing method of the tunneling field-effect transistor, the ON state current of the tunneling field-effect transistor can be obviously improved, and a steep sub-threshold slope is kept. The preparing technology is simple and effect, and the production cost is greatly reduced.
Description
Technical field
The invention belongs to field-effect transistor logical device field in cmos vlsi (ULSI), be specifically related to a kind of straddle riding type heterojunction resonance tunnel-through field-effect transistor and preparation method thereof.
Background technology
Since integrated circuit is born, microelectronics integrated technology is always according to " Moore's Law " development, and dimensions of semiconductor devices constantly reduces.Along with semiconductor device enters deep sub-micron range, existing MOSFET element limit owing to being subject to self spreading the conduction mechanism drifted about, and sub-threshold slope is subject to the restriction of thermoelectric potential kT/q and synchronously cannot reduces along with reducing of device size.This just causes MOSFET element leakage current to reduce the requirement that cannot reach device dimensions shrink, and the energy consumption of whole chip constantly rises, and chip power-consumption density sharply increases, and seriously hinders the development that chip system is integrated.In order to adapt to the development trend of integrated circuit, the R and D work of Novel super-low power consuming devices just seems particular importance.Tunneling field-effect transistor (TFET, Tunneling Field-Effect Transistor) adopt the new conduction mechanism of band-to-band-tunneling (BTBT), be a kind of Novel low power consumption device being suitable for system integration application development having very much development potentiality.TFET controls the tunnelling width of source and raceway groove interface place tunnel junctions by gate electrode, makes source valence-band electrons be tunneling to channel conduction band (or raceway groove valence-band electrons is tunneling to source conduction band) and forms tunnelling current.This novel conduction mechanism breaks through the restriction of thermoelectric potential kT/q in conventional MOS FET sub-threshold slope theoretical limit, can realize the super steep sub-threshold slope lower than 60mV/dec, reduces device static leakage current and then reduces device quiescent dissipation.
But because semiconductor tape band tunneling efficiency is on the low side, the ON state current of TFET is lower compared with existing MOSFET, the requirement in system integration application can not be met.Therefore, while the sub-threshold slope that maintenance is more steep, improving TFET ON state current, is the very important problem needing in TFET device application to solve.
Summary of the invention
For solving above-mentioned prior art Problems existing, the invention provides a kind of straddle riding type heterojunction resonance tunnel-through field-effect transistor and preparation method thereof, this straddle riding type heterojunction resonance tunnel-through field-effect transistor can significantly improve the ON state current of tunneling field-effect transistor, keeps more steep sub-threshold slope simultaneously.
Technical scheme of the present invention is as follows:
A kind of straddle riding type heterojunction resonance tunnel-through field-effect transistor, as shown in Figure 1, comprise tunnelling source region, channel region, drain region and the control gate be positioned at above channel region, wherein, form heterogeneous tunnel junctions at the interface place of tunnelling source region and channel region, the band structure of this heterogeneous tunnel junctions is straddle riding type heterojunction (Straddling-Gap).
Above-mentioned straddle riding type heterojunction resonance tunnel-through field-effect transistor can be N-type device or P type device.For N-type device, it is at the heterogeneous tunnel junctions interface place of tunnelling source region and channel region, the top at the bottom of the conduction band of channel region is positioned at the bottom of the conduction band of tunnelling source region, tunnelling source region top of valence band is positioned at the below of channel region top of valence band, as shown in Fig. 1-1 a), namely the electron affinity of tunnelling area material is less than channel region material electron affinity, and tunnelling area material energy gap is greater than channel region material energy gap; And for P type device, it is positioned at the below at the bottom of the conduction band of channel region at the bottom of the heterogeneous tunnel junctions interface place tunnelling source region conduction band of tunnelling source region and channel region, tunnelling source region top of valence band is positioned at above the top of valence band of channel region, as shown in Fig. 1-1 b), namely the electron affinity of tunnelling area material is greater than channel region material electron affinity, and tunnelling area material energy gap is less than channel region material energy gap.
Further, for N-type straddle riding type heterojunction resonance tunnel-through FET device, tunnelling source region is the heavy doping of P type, and its doping content is about 1E18cm
-3-1E20cm
-3, drain region is N-type heavy doping, and its doping content is about 1E18cm
-3-1E19cm
-3, channel region is P type light dope, and its doping content is about 1E13cm
-3-1E15cm
-3; And for P type straddle riding type heterojunction resonance tunnel-through FET device, tunnelling source region is N-type heavy doping, its doping content is about 1E18cm
-3-1E20cm
-3, drain region is the heavy doping of P type, and its doping content is about 1E18cm
-3-1E19cm
-3, channel region is N-type light dope, and its doping content is about 1E13cm
-3-1E15cm
-3.
Above-mentioned straddle riding type heterojunction resonance tunnel-through field-effect transistor can be applied to Si or Ge, or other can form binary or the ternary semiconductor material of II-VI, III-V or IV-IV race of straddle riding type (Straddling-Gap) heterostructure band structure.Further, for N-type device, require that the electron affinity of tunnelling area material is less than channel region material electron affinity, and tunnelling area material energy gap is greater than channel region material energy gap; And for P type device, require that the electron affinity of tunnelling area material is greater than channel region material electron affinity, and tunnelling area material energy gap is less than channel region material energy gap.
The present invention provides the preparation method of above-mentioned straddle riding type heterojunction resonance tunnel-through field-effect transistor simultaneously, comprises the following steps:
1) deposit one deck oxide and one deck nitride in order on a semiconductor substrate;
2) carry out shallow trench isolation after photoetching from (Shallow Trench Isolation, STI), then carry out chemical-mechanical planarization (Chemical Mechanical Polishing, CMP) after deposit isolated material filling deep hole;
3) deposit gate dielectric material and grid material, carries out photoetching and etching, forms gate figure;
4) photoetching exposes tunnelling source region and selective etching goes out tunnelling source region;
5) growth selection tunnelling source region compound semiconductor, forms straddle riding type (Straddling-Gap) heterogeneous tunnel junctions with channel region, carries out in-situ doped simultaneously to tunnelling source region;
6) photoetching exposes drain region, with photoresist and grid for mask, carries out ion implantation and forms drain region;
7) quick high-temp annealing activator impurity;
8) finally enter the consistent later process of same CMOS, comprise deposit passivation layer, opening contact hole and metallization etc., straddle riding type heterojunction resonance tunnel-through field-effect transistor can be obtained.
For the preparation method of above-mentioned straddle riding type heterojunction resonance tunnel-through field-effect transistor, step 1) in Semiconductor substrate be light dope or unadulterated Semiconductor substrate, the embodiment of the present invention is in step 1) the lightly doped Semiconductor substrate of middle employing, its doping content is about 1E13cm
-3-1E15cm
-3.Wherein, the material of Semiconductor substrate can be the one in germanium (GOI) on the binary of II-VI, III-V or IV-IV race or ternary semiconductor, isolate supports (SOI) or insulator.
Preferably, step 3) in gate dielectric material be SiO
2, Si
3n
4or high-K gate dielectric material.Preferably, step 3) in the method for deposit gate dielectric material be conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.
Preferably, step 3) in grid material be doped polycrystalline silicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or the silicide of metallic nickel.
In the preparation method of above-mentioned straddle riding type heterojunction resonance tunnel-through field-effect transistor, specific embodiments of the invention are in step 5) by molecular beam epitaxy growth selection tunnelling source region compound semiconductor; The material of tunnelling source region compound semiconductor be selected from Si, Ge etc. other can with the material of the Semiconductor substrate in channel region material (i.e. step 1)) form the semi-conducting material of straddle riding type (Straddling-Gap) heterostructure band structure, or the binary of other II-VI, III-V and IV-IV races or ternary semiconductor material.Step 5) to carry out in-situ doped to tunnelling source region, its doping content is about 1E18cm
-3-1E20cm
-3.Step 6) carry out ion implantation formation drain region, wherein, the concentration injecting ion is about 1E18cm
-3-1E19cm
-3.
Straddle riding type heterojunction resonance tunnel-through field-effect transistor provided by the invention can be N-type device or P type device.In above-mentioned preparation method, for N-type device, the electron affinity of tunnelling area material is less than channel region material electron affinity, and tunnelling area material energy gap is greater than channel region material energy gap; And for P type device, the electron affinity of tunnelling area material is greater than channel region material electron affinity, and tunnelling area material energy gap is less than channel region material energy gap.
Advantageous Effects of the present invention is:
Compared with existing TFET, straddle riding type heterojunction tunneling field-effect transistor provided by the invention not only significantly increases device ON state current, maintains steep sub-threshold slope simultaneously.For N-type straddle riding type heterojunction tunneling field-effect transistor device, tunnelling source region and channel region are different materials, the heterogeneous tunnel junctions of straddle riding type is formed at interface place, and the top be positioned at the bottom of the conduction band in tunnelling source region, heterojunction boundary place at the bottom of the conduction band of channel region, the top of valence band in tunnelling source region is positioned at below the top of valence band of channel region.Gate electrode adds positive voltage, and raceway groove can be with drop-down, and channel region forms a triangular quantum well at tunnel junctions place, when source region valence band, channel region valence band and channel region conduction band three place overlap, at tunnel junctions place, resonance tunnel-through occurs, device is opened, and can obtain more steep subthreshold swing.Along with grid voltage increases, source region valence band, between channel region valence band and channel region conduction band, tunnelling width reduces, when both sides tunneling efficiency close to time, resonance tunnel-through efficiency sharply increases, and tunnelling probability levels off to 1, thus obtains the ON state current of larger tunneling transistor.
Straddle riding type heterojunction tunneling field-effect transistor preparation technology provided by the invention is simple, can integrated TFET device in CMOS integrated circuit effectively, standard technology can also be utilized to prepare the low power consumption integrated circuit be made up of TFET, significantly reduce production cost, simplify technological process.
Accompanying drawing explanation
Fig. 1 is the structural representation of straddle riding type heterojunction resonance tunnel-through field-effect transistor of the present invention;
Fig. 1-1 is N/P type straddle riding type heterojunction resonant tunneling thin film tunnel junctions straddle riding type band structure schematic diagram;
Wherein: a) for the band structure of the straddle riding type of N-type straddle riding type heterojunction resonant tunneling thin film tunnel junctions is illustrated; B) for the band structure of P type straddle riding type heterojunction resonant tunneling thin film tunnel junctions straddle riding type is illustrated;
Fig. 1-2 is N-type straddle riding type heterojunction resonance tunnel-through field-effect transistor fundamental diagram;
Wherein: a) be the band structure at tunnel junctions place during device OFF state; B) be the band structure at tunnel junctions place during device ON state;
Fig. 2 removes the device profile map after nitride after forming STI isolation on a semiconductor substrate;
Fig. 3 is photoetching and etches the device profile map after forming grid;
Fig. 4 is that photoetching exposes the source region of TFET device and device profile map after etching source region;
Fig. 5 is behind the heterogeneous source region of extension growth selection, and to tunnelling source region carry out in-situ doped after device profile map;
Fig. 6 photoetching exposes the drain region of TFET device and the device profile map behind ion implantation formation drain region;
In Fig. 1 ~ Fig. 6,
1-Semiconductor substrate (channel region); 2-STI isolates;
3-gate dielectric layer; 4-control gate;
5-photoresist; The heterogeneous tunnelling source region of 6-;
7-drain region; The passivation layer of 8-later process;
The metal of 9-later process.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment, the present invention is described further.
In the present embodiment, the structure of straddle riding type heterojunction resonance tunnel-through field-effect transistor as shown in Figure 1, comprise tunnelling source region 6, channel region 1, drain region 7 and the control gate 4 be positioned at above channel region, it is characterized in that, described tunnelling source region 6 is straddle riding type heterojunction (Straddling-Gap) with the band structure of the heterogeneous tunnel junctions in channel region 1, as shown in Fig. 1-1.
Straddle riding type heterojunction resonance tunnel-through field-effect transistor can be N-type device or P type device.For N-type device, the top at the bottom of the conduction band of channel region is positioned at the bottom of heterogeneous tunnel junctions interface place tunnelling source region conduction band, tunnelling source region top of valence band is positioned at below the top of valence band of channel region, namely the electron affinity of tunnelling area material is less than channel region material electron affinity, and tunnelling area material energy gap is greater than channel region material energy gap; And for P type device, require the below be positioned at the bottom of heterogeneous tunnel junctions interface place tunnelling source region conduction band at the bottom of the conduction band of channel region, tunnelling source region top of valence band is positioned at above the top of valence band of channel region, namely the electron affinity of tunnelling area material is greater than channel region material electron affinity, and tunnelling area material energy gap is less than channel region material energy gap.
Described tunneling field-effect transistor, is characterized in that, for N-type device, tunnelling source region is the heavy doping of P type, and its doping content is about 1E18cm
-3-1E20cm
-3, drain region is N-type heavy doping, and its doping content is about 1E18cm
-3-1E19cm
-3, channel region is P type light dope, and its doping content is about 1E13cm
-3-1E15cm
-3; And for P type device, tunnelling source region is N-type heavy doping, its doping content is about 1E18cm
-3-1E20cm
-3, drain region is the heavy doping of P type, and its doping content is about 1E18cm
-3-1E19cm
-3, channel region is N-type light dope, and its doping content is about 1E13cm
-3-1E15cm
-3.
Described tunneling field-effect transistor can be applied to GaAs/Ge semi-conducting material, also the II-VI that other can form straddle riding type (Straddling-Gap) heterostructure band structure can be applied to, the binary of III-V and IV-IV race or ternary semiconductor material.Further, for N-type device, require that the electron affinity of tunnelling area material is less than channel region material electron affinity, and tunnelling area material energy gap is greater than channel region material energy gap; And for P type device, require that the electron affinity of tunnelling area material is greater than channel region material electron affinity, and tunnelling area material energy gap is less than channel region material energy gap.
Fig. 1-2 is N-type straddle riding type heterojunction resonance tunnel-through field-effect transistor fundamental diagram, wherein: a) be the band structure at tunnel junctions place during device OFF state; B) be the band structure at tunnel junctions place during device ON state.Gate electrode adds positive voltage, and raceway groove can be with drop-down, and channel region forms a triangular quantum well at tunnel junctions place, when source region valence band, channel region valence band and channel region conduction band three place overlap, at tunnel junctions place, resonance tunnel-through occurs, device is opened, and can obtain more steep subthreshold swing.Along with grid voltage increases, source region valence band, between channel region valence band and channel region conduction band, tunnelling width reduces, when both sides tunneling efficiency close to time, resonance tunnel-through efficiency sharply increases, and tunnelling probability levels off to 1, thus obtains the ON state current of larger tunneling transistor.
Below for N-type device, the preparation method of above-mentioned straddle riding type heterojunction resonance tunnel-through field-effect transistor is described, the preparation of P type straddle riding type heterojunction resonance tunnel-through FET device is similar with it.For N-type device, the implementation step of the preparation method of above-mentioned straddle riding type heterojunction resonance tunnel-through field-effect transistor, as shown in Fig. 2 ~ Fig. 6, comprising:
1, be light dope (about 1E13cm in substrate doping
-3-1E15cm
-3), crystal orientation be <001> Ge substrate 1 on initial deposition layer of silicon dioxide, thickness is about 10nm, and deposit one deck silicon nitride (Si
3n
4), thickness is about 100nm, adopts shallow-trench isolation fabrication techniques active area STI to isolate 2 afterwards, then carries out CMP, as shown in Figure 2.
2, the silicon dioxide on surface is removed in drift, and then deposit one deck gate dielectric layer 3, gate dielectric layer is Al
2o
3, thickness is 1 ~ 5nm; Adopt LPCVD deposit grid material 4, grid material is doped polysilicon layer, and thickness is 50 ~ 200nm.Make gate figure by lithography, etch grid material 4 until gate dielectric layer 3, as shown in Figure 3.
3, photoetching exposes source region, and adopt high selectivity dry etching to go out heterojunction tunnelling source region, junction depth is about 50nm, as shown in figure-4.
4, adopt molecular beam epitaxy growth selection GaAs semiconductor to form heterogeneous source region 6, source region is carried out to in-situ doped (concentration is about 1E20cm simultaneously
-3), as shown in figure-5.
5, photoetching exposes drain region, and with photoresist 5 and grid 4 for mask, (As, dosage is 1E14/cm to carry out drain region 7 ion implantation
-2, energy is 20keV, injects ion concentration and is about 1E18/cm
-3), as shown in Figure 6.Carry out a quick high-temp annealing, and implanted dopant is activated (temperature is 1050 DEG C, and the time is 10s)
6, finally enter conventional later process, comprise deposit passivation layer 8, opening contact hole and metallization 9 etc., Figure 1 shows that the straddle riding type heterojunction resonance tunnel-through field-effect transistor structure schematic diagram of obtained described N-type.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (11)
1. a straddle riding type heterojunction resonance tunnel-through field-effect transistor, comprise tunnelling source region, channel region, drain region and the control gate be positioned at above raceway groove, it is characterized in that, form heterogeneous tunnel junctions at the interface place of described tunnelling source region and channel region, the band structure of described heterogeneous tunnel junctions is straddle riding type heterojunction.
2. straddle riding type heterojunction resonance tunnel-through field-effect transistor as claimed in claim 1, it is characterized in that, described straddle riding type heterojunction resonance tunnel-through field-effect transistor is N-type device or P type device.
3. straddle riding type heterojunction resonance tunnel-through field-effect transistor as claimed in claim 1, it is characterized in that, described straddle riding type heterojunction resonance tunnel-through field-effect transistor is N-type device, at the interface place of the heterogeneous tunnel junctions of described tunnelling source region and channel region, be positioned at the top at the bottom of the conduction band of channel region at the bottom of the conduction band in tunnelling source region, the top of valence band in tunnelling source region is positioned at the below of the top of valence band of channel region.
4. straddle riding type heterojunction resonance tunnel-through field-effect transistor as claimed in claim 3, it is characterized in that, described tunnelling source region is the heavy doping of P type, and doping content is 1E18cm
-3~ 1E20cm
-3; Described drain region is N-type heavy doping, and doping content is 1E18cm
-3~ 1E19cm
-3; Described channel region is P type light dope, and doping content is 1E13cm
-3~ 1E15cm
-3.
5. straddle riding type heterojunction resonance tunnel-through field-effect transistor as claimed in claim 1, it is characterized in that, described straddle riding type heterojunction resonance tunnel-through field-effect transistor is P type device, at the interface place of the heterogeneous tunnel junctions of described tunnelling source region and channel region, be positioned at the below at the bottom of the conduction band of channel region at the bottom of the conduction band in tunnelling source region, the top of valence band in tunnelling source region is positioned at the top of the top of valence band of channel region.
6. straddle riding type heterojunction resonance tunnel-through field-effect transistor as claimed in claim 5, it is characterized in that, described tunnelling source region is N-type heavy doping, and doping content is 1E18cm
-3~ 1E20cm
-3; Described drain region is the heavy doping of P type, and doping content is 1E18cm
-3~ 1E19cm
-3; Described channel region is N-type light dope, and doping content is 1E13cm
-3~ 1E15cm
-3.
7. a preparation method for straddle riding type heterojunction resonance tunnel-through field-effect transistor, comprises the following steps:
1) deposit one deck oxide and one deck nitride in order on a semiconductor substrate;
2) carry out after photoetching shallow trench isolation from, then deposit isolated material is filled after deep hole and is carried out chemical-mechanical planarization;
3) deposit gate dielectric material and grid material, carries out photoetching and etching, forms gate figure;
4) photoetching exposes tunnelling source region and selective etching goes out tunnelling source region;
5) growth selection tunnelling source region compound semiconductor, forms the heterogeneous tunnel junctions of straddle riding type with channel region, carries out in-situ doped simultaneously to tunnelling source region;
6) photoetching exposes drain region, with photoresist and grid for mask, carries out ion implantation and forms drain region;
7) quick high-temp annealing activator impurity;
8) by later process, deposit passivation layer, opening contact hole and metallization is comprised, obtained straddle riding type heterojunction resonance tunnel-through field-effect transistor.
8. the preparation method of straddle riding type heterojunction resonance tunnel-through field-effect transistor as claimed in claim 7, is characterized in that, step 1) described Semiconductor substrate is light dope or unadulterated Semiconductor substrate; The material of Semiconductor substrate is the one in the germanium GOI on the binary of II-VI, III-V or IV-IV race or ternary semiconductor, isolate supports SOI or insulator.
9. the preparation method of straddle riding type heterojunction resonance tunnel-through field-effect transistor as claimed in claim 7, is characterized in that, step 3) described gate dielectric material is SiO
2, Si
3n
4or high-K gate dielectric material; Step 3) method of described deposit gate dielectric material is conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition; Step 3) described grid material is doped polycrystalline silicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or the silicide of metallic nickel.
10. the preparation method of straddle riding type heterojunction resonance tunnel-through field-effect transistor as claimed in claim 7, is characterized in that, step 5) be by molecular beam epitaxy growth selection tunnelling source region compound semiconductor; Be positioned at the top at the bottom of the conduction band of channel region at the bottom of the conduction band in described tunnelling source region, the top of valence band in tunnelling source region is positioned at the below of the top of valence band of channel region and forms the heterogeneous tunnel junctions of described straddle riding type.
The preparation method of 11. straddle riding type heterojunction resonance tunnel-through field-effect transistors as claimed in claim 7, is characterized in that, step 5) described in-situ doped doping content is 1E18cm
-3~ 1E20cm
-3; Step 6) concentration of described ion implantation is 1E18cm
-3~ 1E19cm
-3.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4835581A (en) * | 1986-07-25 | 1989-05-30 | Hitachi, Ltd. | Electron gas hole gas tunneling transistor device |
| US5021841A (en) * | 1988-10-14 | 1991-06-04 | University Of Illinois | Semiconductor device with controlled negative differential resistance characteristic |
| US5734181A (en) * | 1995-09-14 | 1998-03-31 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method therefor |
| US20040217358A1 (en) * | 2002-04-26 | 2004-11-04 | Nissan Motor Co., Ltd | Silicon carbide semiconductor device |
| US6897098B2 (en) * | 2003-07-28 | 2005-05-24 | Intel Corporation | Method of fabricating an ultra-narrow channel semiconductor device |
| US20070178650A1 (en) * | 2006-02-01 | 2007-08-02 | International Business Machines Corporation | Heterojunction tunneling field effect transistors, and methods for fabricating the same |
| US20140175376A1 (en) * | 2012-12-21 | 2014-06-26 | Uygar E. Avci | Reduced Scale Resonant Tunneling Field Effect Transistor |
-
2014
- 2014-08-29 CN CN201410438469.3A patent/CN104241375B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4835581A (en) * | 1986-07-25 | 1989-05-30 | Hitachi, Ltd. | Electron gas hole gas tunneling transistor device |
| US5021841A (en) * | 1988-10-14 | 1991-06-04 | University Of Illinois | Semiconductor device with controlled negative differential resistance characteristic |
| US5734181A (en) * | 1995-09-14 | 1998-03-31 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method therefor |
| US20040217358A1 (en) * | 2002-04-26 | 2004-11-04 | Nissan Motor Co., Ltd | Silicon carbide semiconductor device |
| US6897098B2 (en) * | 2003-07-28 | 2005-05-24 | Intel Corporation | Method of fabricating an ultra-narrow channel semiconductor device |
| US20070178650A1 (en) * | 2006-02-01 | 2007-08-02 | International Business Machines Corporation | Heterojunction tunneling field effect transistors, and methods for fabricating the same |
| US20140175376A1 (en) * | 2012-12-21 | 2014-06-26 | Uygar E. Avci | Reduced Scale Resonant Tunneling Field Effect Transistor |
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