CN104241137B - Semiconductor structure and its manufacture method - Google Patents
Semiconductor structure and its manufacture method Download PDFInfo
- Publication number
- CN104241137B CN104241137B CN201410285928.9A CN201410285928A CN104241137B CN 104241137 B CN104241137 B CN 104241137B CN 201410285928 A CN201410285928 A CN 201410285928A CN 104241137 B CN104241137 B CN 104241137B
- Authority
- CN
- China
- Prior art keywords
- source region
- body area
- side wall
- resistance
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 230000008569 process Effects 0.000 claims abstract description 18
- 238000002347 injection Methods 0.000 claims description 27
- 239000007924 injection Substances 0.000 claims description 27
- 238000002513 implantation Methods 0.000 claims description 18
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 229910001449 indium ion Inorganic materials 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 description 21
- 239000013078 crystal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
Abstract
A kind of semiconductor structure and its manufacture method, the semiconductor structure include：Semiconductor substrate, positioned at Semiconductor substrate Nei Ti areas；Positioned at the semiconductor substrate surface and positioned at two grid structures and side wall of body area both sides, the grid structure is across body area and the edge of Semiconductor substrate；The heavy doping source region in body area exposed between side wall, source region is lightly doped in low-resistance positioned at heavy doping source region close to grid structure side, positioned at the heavy doping source region Nei Ti areas bonding pad, the minimum spacing being smaller than between current process lower body area bonding pad and side wall between body area bonding pad and side wall.Although the spacing between body area bonding pad and side wall diminishes, but because the electric current of channel region can be electrically connected by conductive channel (source region is lightly doped in low-resistance) with heavy doping source region, the conducting resistance of ldmos transistor will not be greatly improved, source region size and electric conductivity can be taken into account simultaneously.
Description
Technical field
The present invention relates to the semiconductor structure and its system of field of semiconductor manufacture, more particularly to a kind of LDMOS source regions position
Make method.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS) transistor is a kind of MOS device being lightly doped, with CMOS works
Skill has extraordinary compatibility.Conventional CMOS device is usually source and drain symmetrical structure, and ldmos transistor is non-right using source and drain
Structure is claimed to meet the demand compared with high withstand voltage and relatively low conducting resistance.
Fig. 1 and Fig. 2 are refer to, Fig. 1 is the overlooking the structure diagram of existing NLDMOS source transistors zone position, and Fig. 2 is
The cross-sectional view of AA ' wire cuttings along along Fig. 1, including：Semiconductor substrate 10, positioned at the Nei Ti areas of Semiconductor substrate 10
20；Positioned at the Semiconductor substrate 10 and positioned at two grid structures 40 and side wall 41 of the both sides of body area 20, the grid structure
40 across body area 20 and the edge of Semiconductor substrate 10；There is heavy doping source region in the body area exposed between two side walls 41
31, source region 32 is lightly doped close to the side of grid structure 40 positioned at heavy doping source region 31, in the heavy doping source region 31
Body area bonding pad 21, the conductive plunger 22 positioned at the surface of body area bonding pad 21.Due to constantly carrying with integrated circuit integrated level
Height, the size of NLDMOS transistors is constantly reducing, therefore two adjacent NLDMOS transistors share and are same as a source region, Fig. 1
Two NLDMOS transistors are belonging respectively to two grid structures in Fig. 2.
But it is due to need to be formed body area bonding pad 21 in heavy-doped source area 31, therefore Tu1Zhong Ti areas bonding pad 21
The width W2 of the heavy doping source region 31 of width W1 and the both sides of body area bonding pad 21 size can not further reduce, and can cause
The size of NLDMOS transistors is not easy further diminution.
The content of the invention
The problem of present invention is solved is to provide a kind of semiconductor structure and its manufacture method, can effectively reduce LDMOS crystal
The source region size of pipe.
To solve the above problems, the embodiment of the present invention provides a kind of manufacture method of semiconductor structure, including：Offer is partly led
There is body area in body substrate, the Semiconductor substrate；In semiconductor substrate surface formation grid structure, the grid structure
Across body area and the edge of Semiconductor substrate；Using the grid structure as mask, the body area between two grid structures is carried out
First foreign ion tilts injection, light in position formation low-resistance of the body surface and grid structure bottom exposed close to edge
Doping source region；In gate structure sidewall formation side wall, using the side wall as mask, weight is formed to the body surface exposed
Doping source region；Ion implanting is carried out in the corresponding position of the heavy doping source region using photomask, body area bonding pad, institute's shape is formed
Into body area bonding pad and side wall between the minimum spacing being smaller than between current process lower body area bonding pad and side wall.
Optionally, when the semiconductor structure is the source structure of NLDMOS transistors, first foreign ion is
Arsenic ion；When the semiconductor structure is the source structure of PLDMOS transistors, first foreign ion is BF2Ion or
Indium ion.
Optionally, when first foreign ion is arsenic ion, the Implantation Energy that the arsenic ion tilts injection is 10KeV
~50KeV, implantation dosage is 5e13/ square centimeters~1e14/ square centimeters, and the angle of injection is 7 degree~15 degree, the low-resistance
The square resistance that source region is lightly doped is 600 ohm~1.2K ohm.
Optionally, when first foreign ion is BF2Ion or indium ion, the BF2Ion or indium ion tilt injection
Implantation Energy be 10KeV~100KeV, implantation dosage is 5e13/ square centimeters~1e14/ square centimeters, and the angle of injection is
7 degree~15 degree, the square resistance that source region is lightly doped in the low-resistance is 1K ohm~2K ohm.
Optionally, the projection of body area bonding pad photomask pattern has lap with side wall.
Optionally, the photomask pattern of body area bonding pad is the minimum dimension figure of current process lower body area bonding pad.
Optional, the photomask pattern of body area bonding pad is square, and the side of the square edge and side wall
Edge is in 45 degree.
The embodiment of the present invention additionally provides a kind of semiconductor structure, including：Semiconductor substrate, in Semiconductor substrate
Body area；Positioned at the semiconductor substrate surface and positioned at two grid structures and side wall of body area both sides, the grid structure is horizontal
Across body area and the edge of Semiconductor substrate；The heavy doping source region in body area exposed between side wall, positioned at heavy-doped source
Source region is lightly doped in low-resistance of the area close to grid structure side, positioned at the heavy doping source region Nei Ti areas bonding pad, the body area
The minimum spacing being smaller than between current process lower body area bonding pad and side wall between bonding pad and side wall.
Optionally, when the semiconductor structure is the source structure of NLDMOS transistors, source region is lightly doped in the low-resistance
The first foreign ion be arsenic ion；When the semiconductor structure is the source structure of PLDMOS transistors, the low-resistance is light
First foreign ion of doping source region is BF2Ion or indium ion.
Optionally, when the semiconductor structure is the source structure of PLDMOS transistors, source region is lightly doped in the low-resistance
Square resistance be 1K ohm~2K ohm.
Optionally, when the semiconductor structure is the source structure of NLDMOS transistors, source region is lightly doped in the low-resistance
Square resistance be 600 ohm~1.2K ohm.
Optionally, body area bonding pad is in contact with side wall.
Optionally, the photomask pattern of body area bonding pad for square, and the edge of the square light mask graph with
The edge of side wall is in 45 degree.
Optionally, in addition to the conductive plunger positioned at body area bonding pad surface, the spacing between two side wall edges is equal to
Twice of minimum spacing between side wall and conductive plunger, both width of conductive plunger sum.
Compared with prior art, the technical program has advantages below：
Low-resistance is formed in the position that source region is lightly doped using the first impure ion injection technology and source region is lightly doped, in side wall
Conductive channel is formed in the body area of bottom, while being smaller than current process lower body between the body area bonding pad formed and side wall
Minimum spacing between area bonding pad and side wall, although the spacing between body area bonding pad and side wall diminishes, but due to channel region
Electric current can be electrically connected by conductive channel (source region is lightly doped in low-resistance) with heavy doping source region, LDMOS crystal will not be greatly improved
The conducting resistance of pipe, therefore source region size and electric conductivity can be taken into account simultaneously.
Brief description of the drawings
Fig. 1 and Fig. 2 are the structural representations of the source region position of the NLDMOS transistors of prior art；
Fig. 3~Fig. 9 is the structural representation of the manufacturing process of the semiconductor structure of the embodiment of the present invention.
Embodiment
Inventor has found that the width W1 of body area bonding pad 21 can not enter one due to being limited by photoetching process
Step reduces, and the width W2 of the heavy doping source region 31 of the both sides of body area bonding pad 21 is not only to be limited by photoetching process, also
It can be limited by device performance.Due to transoid between body area bonding pad 21 and heavy doping source region 31, when body area bonding pad 21 with
When width W2 between side wall 41 is too small, the resistance of the heavy doping source region 31 of the side correspondence position of body area bonding pad 21 can become big.
Further study show that, it is by medium energy (about 100KV) median dose mainly due to the existing source region 32 that is lightly doped
The phosphonium ion injection of (1e12~1e13/ square centimeters) wide-angle (about 30 degree) is formed, it is therefore an objective to meet nmos pass transistor
Hot carrier cause device property to be degenerated the life requirements of (HCI), but resistance is larger under source side wall, and the diffusion of phosphonium ion
Speed is fast, and parasitic base resistance is larger.If corresponding width W2 is also too small, the conducting of NLDMOS transistors can be had a strong impact on
Resistance.
Therefore the embodiments of the invention provide a kind of semiconductor structure and its manufacture method, the first foreign ion injection is utilized
Technique forms low-resistance in the position that source region is lightly doped and source region is lightly doped, and forms conductive channel in the body area of the bottom of side wall, together
When the body area bonding pad that is formed and side wall between be smaller than between minimum between current process lower body area bonding pad and side wall
Away from, although the spacing between body area bonding pad and side wall diminishes, but due to channel region electric current can (low-resistance be light by conductive channel
Doping source region) electrically connected with heavy doping source region, the conducting resistance of ldmos transistor will not be greatly improved, therefore can take into account simultaneously
Source region size and electric conductivity.
Below in conjunction with the accompanying drawings, by specific embodiment, clear, complete description is carried out to technical scheme.By
NLDMOS transistors or PLDMOS crystal can be manufactured respectively in the manufacture method of the semiconductor structure using the embodiment of the present invention
The source structure of pipe, in the present embodiment, to the half of the embodiment of the present invention exemplified by manufacturing the source structure of NLDMOS transistors
The manufacturing process of conductor structure is illustrated.
Fig. 3~Fig. 9 is refer to, is the structural representation of the manufacturing process of the semiconductor structure of the embodiment of the present invention.
Fig. 3 be refer to there is provided Semiconductor substrate 110, the Semiconductor substrate 110 is interior to have PXing Ti areas 120.
In the present embodiment, because corresponding ldmos transistor is NLDMOS transistors, therefore the Semiconductor substrate
110 be N-type substrate, after the formation process in the PXing Ti areas 120 is ion implantation technology, ion implanting, is entered using annealing process
Row moves back knot and activator impurity.
In other embodiments, N-type well region can also be formed in Semiconductor substrate 110, p-type is formed in N-type well region
Body area 120.
Fig. 4 is refer to, grid structure 140 is formed on the surface of Semiconductor substrate 110.
Before grid structure 140 is formed, it is additionally included in Semiconductor substrate and forms fleet plough groove isolation structure, P type trap zone
Deng processing step, because the formation process in NLDMOS drain regions is not the protection main points of the present invention, it is not detailed herein.
The grid structure 140 is polysilicon gate construction or metal gate structure etc..In the present embodiment, the grid
Structure 140 is polysilicon gate construction, including gate oxide and the polysilicon gate positioned at gate oxide surface.In other implementations
In example, grid technique formation metal gate structure after using, the grid structure can also be the pseudo- grid of polysilicon.
Fig. 5 is refer to, is mask with the grid structure 140, the PXing Ti areas 120 between two grid structures 140 are entered
Row arsenic ion tilts injection, is formed on the surface of PXing Ti areas 120 and the bottom of grid structure 140 exposed close to the position at edge
Source region 132 is lightly doped in low-resistance.
In the present embodiment, because manufactured ldmos transistor is NLDMOS transistors, between two grid structures
To carry out the first foreign ion to tilt the first foreign ion of injection be arsenic ion in body area, the arsenic ion tilts the injection of injection
Energy is 10KeV~50KeV, and implantation dosage is 5e13/ square centimeters~1e14/ square centimeters, and the angle of injection is 7 degree~15
Degree, the square resistance that source region 132 is lightly doped in the low-resistance ultimately formed is 600 ohm~1.2K ohm.
Because the Implantation Energy that the arsenic ion tilts injection is less than the existing Implantation Energy that source region is lightly doped, and injection
The implantation concentration of source region is lightly doped more than existing in dosage, therefore can effectively reduce the resistance under NLDMOS source side walls；Together
When arsenic Speed of diffusion it is slow, for phosphorus injection, can obtain smaller parasitic base resistance, improvement influences hitting during break-over of device
Wear characteristic.
Source region 132 is lightly doped due to being also formed with low-resistance close to the position at edge in the bottom of grid structure 140, therefore is located at
The bottom of grid structure 140 can form conductive channel close to the position at edge, even if follow-up body area bonding pad is in contact with side wall, body
Electric current in the channel region of area bonding pad correspondence position can flow to the heavy doping source region of other positions by conductive channel, form logical
Road.
Fig. 6 is refer to, is mask with the side wall 141, to exposure in the side wall formation side wall 141 of grid structure 140
The surface of ChuPXing Ti areas 120 carries out ion implanting formation N-type heavy doping source region 131.
While N-type heavy doping source region 131 are formed, N-type is correspondingly formed in the drain region position of NLDMOS transistors
Heavy doping drain region (not shown).
Fig. 7 is refer to, ion implanting is carried out in the corresponding position of the N-type heavy doping source region 131 using photomask, is formed
PXing Ti areas bonding pad 121, p-type under current process is smaller than between the PXing Ti areas bonding pad 121 formed and side wall 141
Minimum spacing between body area bonding pad and side wall.
The depth of PXing Ti areas bonding pad 121 is more than or equal to the depth of N-type heavy doping source region 131 so that p-type body
Area bonding pad 121 and PXing Ti areas 120 are electrically connected, and subsequently form conductive plunger on the surface of PXing Ti areas bonding pad 121.
In the present embodiment, both overlapping margins of PXing Ti areas bonding pad 121 and side wall 141.In other embodiment
In, PXing Ti areas bonding pad is in contact with side wall.Or PXing Ti areas bonding pad is separated with side wall, QiePXing Ti areas
The minimum spacing being smaller than between current process XiaPXing Ti areas bonding pad and side wall between bonding pad and side wall.
In the present embodiment, projection and the side wall of the photomask pattern for forming PXing Ti areas bonding pad 121 have overlapping portion
Point so that both overlapping margins of PXing Ti areas bonding pad 121 and side wall 141 of final ion implanting formation.
In one embodiment, the photomask pattern of PXing Ti areas bonding pad 121 is square, and the square
Edge and side wall edge be in 45 degree, it is described square for current process lower body area bonding pad minimum dimension figure.
In the case of identical graphics area, because the square of 45 degree of rotations can cause PXing Ti areas bonding pad and side
Intersection between wall is most short so that drain current conductive channel (source region 132 is lightly doped in the low-resistance of side wall bottom) flow away from
From most short.Although the resistance that source region 132 is lightly doped in low-resistance is relatively low, due to HCI presence, doping concentration can not be too high, therefore
Drain current is more short better in the flow distance of conductive channel.Because the size of PXing Ti areas bonding pad mask pattern is by technique
Limitation can not be too small, therefore when PXing Ti areas bonding pad photomask pattern be current process lower body area bonding pad minimum chi
Very little figure, after long and wide determination, in order to further reduce flow distance of the drain current in conductive channel, PXing Ti areas are connected
Angle is provided between the photomask pattern and side wall in area.Therefore, in the present embodiment, the photomask pattern of PXing Ti areas bonding pad
For square, the edge at the square edge and side wall is in 45 degree.
Because the presence of source region 132 is lightly doped in the low-resistance of side wall bottom, between PXing Ti areas bonding pad 121 and side wall 141
Spacing can infinitely reduce.Even if PXing Ti areas bonding pad 121 is in contact with side wall 141 completely, by 131 points of N-type heavy doping source region
Several parts are divided into, but because the presence of source region 132 is lightly doped in low-resistance, several N-type heavy doping source regions 131 still electricity of separation connects
Connect, total conducting resistance will not significantly change because of the change in location of PXing Ti areas bonding pad 121, therefore can take into account source simultaneously
Area's size and electric conductivity.
Fig. 8 and Fig. 9 are refer to, Fig. 9 is the overlooking the structure diagram of the semiconductor structure shown in Fig. 8, in the PXing Ti areas
The surface of bonding pad 121 and the surface of N-type heavy doping source region 131 form conductive plunger 122.
Because the spacing between PXing Ti areas bonding pad 121 and side wall 141 can infinitely reduce, between described two source regions
Distance depend between side wall and conductive plunger minimum spacing and conductive plunger width.In the present embodiment, it is described two
Spacing (i.e. the width of N-type heavy doping source region 131) between side wall 141 is two of minimum spacing between side wall and conductive plunger
Again, the width sum of conductive plunger.In other embodiments, the spacing between described two side walls 141 may be slightly larger than side wall with
Twice, the width sum of conductive plunger of minimum spacing between conductive plunger.
In another embodiment, due to specific steps and the NLDMOS crystal processed of the source structure that manufactures PLDMOS transistors
The specific steps of the source structure of pipe are similar, and something in common is not repeated.Doped ions electricity is differed only in due to both
Type on the contrary, in the present embodiment, body area, body area bonding pad are p-type, and source region is lightly doped for N-type in heavy doping source region, low-resistance,
And in another embodiment, body area, body area bonding pad are N-type, source region is lightly doped for p-type in heavy doping source region, low-resistance, and described the
One foreign ion is BF2Ion or indium ion, the BF2Ion or indium ion tilt the Implantation Energy of injection for 10KeV~
100KeV, implantation dosage is 5e13/ square centimeters~1e14/ square centimeters, and the angle of injection is 7 degree~15 degree, the low-resistance
The square resistance that source region is lightly doped is 1K ohm~2K ohm.
The embodiment of the present invention additionally provides a kind of semiconductor structure, refer to Fig. 8 and Fig. 9, including：Semiconductor substrate 110,
Positioned at the NeiPXing Ti areas 120 of Semiconductor substrate 110；Positioned at the surface of Semiconductor substrate 110 and positioned at the both sides of PXing Ti areas 120
Two grid structures 140 and side wall 141, the grid structure 140 is across the side of PXing Ti areas 120 and Semiconductor substrate 110
Edge；N-type heavy doping source region 131 in the PXing Ti areas 120 exposed between side wall 140, positioned at N-type heavy doping source region 131
Source region 132 is lightly doped in low-resistance close to the side of grid structure 140, connects positioned at the NeiPXing Ti areas of N-type heavy doping source region 131
Meet area 121, between PXing Ti areas bonding pad 121 and side wall 141 be smaller than current process XiaPXing Ti areas bonding pad with
Minimum spacing between side wall.
In the present embodiment, when first foreign ion is arsenic ion, the formation process of source region is lightly doped in the low-resistance
For：The Implantation Energy that arsenic ion tilts injection is 10KeV~50KeV, and implantation dosage is 5e13/ square centimeters~1e14/ squares
Centimetre, the angle of injection is 7 degree~15 degree, and the square resistance that source region is lightly doped in the low-resistance is 600 ohm~1.2K ohm.
In the present embodiment, because the photomask pattern of PXing Ti areas bonding pad 121 is square and described square
The edge of edge and side wall is in 45 degree, and PXing Ti areas bonding pad is in contact with side wall.
In other embodiments, PXing Ti areas bonding pad can also be other figures, such as rectangle, circular lamp, and institute
Between the minimum being smaller than between current process XiaPXing Ti areas bonding pad and side wall between ShuPXing Ti areas bonding pad and side wall
Away from.
In the present embodiment, in addition to the conductive plunger 122 positioned at the surface of PXing Ti areas bonding pad 121, between two side walls
Spacing be equal between side wall and conductive plunger twice of minimum spacing and conductive plunger width sum.
In the present embodiment, the semiconductor structure is the source structure of NLDMOS transistors, in other embodiments, when
When the semiconductor structure is the source structure of PLDMOS transistors, first foreign ion is BF2Ion or indium ion, institute
State BF2The Implantation Energy that ion or indium ion tilt injection is 10KeV~100KeV, implantation dosage is 5e13/ square centimeters~
1e14/ square centimeters, the angle of injection is 7 degree~15 degree, and the square resistance that source region is lightly doped in the low-resistance is 1K ohm~2K
Ohm.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques content of the disclosure above to this hair
Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention
Protection domain.
Claims (13)
1. a kind of manufacture method of semiconductor structure, it is characterised in that including：
There is provided has body area in Semiconductor substrate, the Semiconductor substrate；
In semiconductor substrate surface formation grid structure, boundary of the grid structure between body area and Semiconductor substrate
Face；
Using the grid structure as mask, the first foreign ion is carried out to the body area between two grid structures and tilts injection,
The body surface and grid structure bottom exposed forms low-resistance close to the position at edge and source region is lightly doped, light using the low-resistance
Doping source region forms conductive channel in the body area of side wall bottom, and the square resistance scope that source region is lightly doped in the low-resistance is 600
Ohm~2K ohm；
In gate structure sidewall formation side wall, using the side wall as mask, the body surface formation heavy doping to exposing
Source region；
Ion implanting is carried out in the corresponding position of the heavy doping source region using photomask, body area bonding pad is formed, is formed
Body area bonding pad is contacted with side wall.
2. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that when the semiconductor structure is
During NLDMOS transistors, first foreign ion is arsenic ion；It is described when the semiconductor structure is PLDMOS transistors
First foreign ion is BF2Ion or indium ion.
3. the manufacture method of semiconductor structure as claimed in claim 2, it is characterised in that when first foreign ion is arsenic
Ion, the Implantation Energy that the arsenic ion tilts injection is 10KeV~50KeV, implantation dosage is 5e13/ square centimeters~
1e14/ square centimeters, the angle of injection is 7 degree~15 degree, the square resistance that source region is lightly doped in the low-resistance is 600 ohm~
1.2K ohm.
4. the manufacture method of semiconductor structure as claimed in claim 2, it is characterised in that when first foreign ion is BF2
Ion or indium ion, the BF2The Implantation Energy that ion or indium ion tilt injection is 10KeV~100KeV, and implantation dosage is
5e13/ square centimeters~1e14/ square centimeters, the angle of injection is 7 degree~15 degree, and the square electricity of source region is lightly doped in the low-resistance
Hinder for 1K ohm~2K ohm.
5. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that body area bonding pad photomask pattern
Projection has lap with side wall.
6. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the photomask pattern of body area bonding pad
For the minimum dimension figure of current process lower body area bonding pad.
7. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the photomask pattern of body area bonding pad
It it is in 45 degree for the edge of square, and the square edge and side wall.
8. a kind of semiconductor structure, it is characterised in that including：Semiconductor substrate, positioned at Semiconductor substrate Nei Ti areas；Positioned at institute
State semiconductor substrate surface and positioned at two grid structures and side wall of body area both sides, the grid structure is across body area with partly leading
Interface between body substrate；The heavy doping source region in body area exposed between side wall, positioned at heavy doping source region close to grid
Source region is lightly doped in the low-resistance of pole structure side, and source region is lightly doped using the low-resistance forms conductive logical in the body area of side wall bottom
Road, the square resistance scope that source region is lightly doped in the low-resistance is 600 ohm~2K ohm；Body in the heavy doping source region
Area bonding pad, the body area bonding pad formed is contacted with side wall.
9. semiconductor structure as claimed in claim 8, it is characterised in that when the semiconductor structure is NLDMOS transistors
When, the first foreign ion that source region is lightly doped in the low-resistance is arsenic ion；When the semiconductor structure is PLDMOS transistors,
The first foreign ion that source region is lightly doped in the low-resistance is BF2Ion or indium ion.
10. semiconductor structure as claimed in claim 9, it is characterised in that when the semiconductor structure is PLDMOS transistors
When, the square resistance that source region is lightly doped in the low-resistance is 1K ohm~2K ohm.
11. semiconductor structure as claimed in claim 9, it is characterised in that when the semiconductor structure is NLDMOS transistors
When, the square resistance that source region is lightly doped in the low-resistance is 600 ohm~1.2K ohm.
12. semiconductor structure as claimed in claim 8, it is characterised in that the photomask pattern of body area bonding pad is square,
And the edge of the square light mask graph and the edge of side wall are in 45 degree.
13. semiconductor structure as claimed in claim 8, it is characterised in that also including the conduction positioned at body area bonding pad surface
Spacing between connector, two side wall edges is equal to twice of minimum spacing between side wall and conductive plunger and the width of conductive plunger
Both sums of degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410285928.9A CN104241137B (en) | 2014-06-24 | 2014-06-24 | Semiconductor structure and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410285928.9A CN104241137B (en) | 2014-06-24 | 2014-06-24 | Semiconductor structure and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104241137A CN104241137A (en) | 2014-12-24 |
| CN104241137B true CN104241137B (en) | 2017-08-08 |
Family
ID=52228986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410285928.9A Active CN104241137B (en) | 2014-06-24 | 2014-06-24 | Semiconductor structure and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104241137B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151618B (en) * | 2020-09-27 | 2022-09-20 | 杰华特微电子股份有限公司 | Manufacturing method of transverse super junction structure |
| CN115101477B (en) * | 2022-08-24 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116207142B (en) * | 2023-05-04 | 2023-07-18 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719421A (en) * | 1994-10-13 | 1998-02-17 | Texas Instruments Incorporated | DMOS transistor with low on-resistance and method of fabrication |
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
-
2014
- 2014-06-24 CN CN201410285928.9A patent/CN104241137B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719421A (en) * | 1994-10-13 | 1998-02-17 | Texas Instruments Incorporated | DMOS transistor with low on-resistance and method of fabrication |
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104241137A (en) | 2014-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9087774B2 (en) | LDMOS device with short channel and associated fabrication method | |
| US9245997B2 (en) | Method of fabricating a LDMOS device having a first well depth less than a second well depth | |
| CN104992977B (en) | NLDMOS device and its manufacturing method | |
| US10388741B2 (en) | Semiconductor device with arrangement of semiconductor regions for improving breakdown voltages | |
| WO2017211105A1 (en) | Super-junction device, chip and manufacturing method therefor | |
| TWI565053B (en) | High voltage semiconductor device and method of manufacturing the same | |
| CN104241137B (en) | Semiconductor structure and its manufacture method | |
| CN103178087B (en) | Superhigh pressure LDMOS device structure and preparation method | |
| CN108288645A (en) | High voltage device and method for manufacturing the same | |
| CN109935633B (en) | LDMOS device | |
| CN102623353A (en) | Manufacturing method of N-LDMOS (N-Laterally Diffused Metal Oxide Semiconductor) | |
| US9117901B2 (en) | High voltage device and manufacturing method thereof | |
| CN105206675A (en) | Nldmos device and manufacturing method thereof | |
| JP2008060152A (en) | Semiconductor device, and its manufacturing method | |
| JP2006261562A (en) | Semiconductor device | |
| CN104282763B (en) | Radio frequency horizontal dual pervasion field effect transistor preparation method | |
| CN103022125A (en) | NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method | |
| CN103456784B (en) | High-voltage P-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method | |
| KR20110078861A (en) | Lateral double diffused metal oxide semiconductor | |
| CN104201203B (en) | High withstand voltage LDMOS device and manufacture method thereof | |
| CN103515414A (en) | Transistor device and manufacturing method thereof | |
| CN103515439B (en) | Groove type metal oxide semiconductor field effect transistor | |
| CN106941122A (en) | Semiconductor device and its manufacture method | |
| CN104716184A (en) | High voltage lateral extended drain mos transistor with improved drift layer contact | |
| CN104681605B (en) | The structure and its manufacture method of power MOS pipe |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Patentee after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 424, building 1, 1500 Wenyi West Road, Cangqian street, Yuhang District, Hangzhou City, Zhejiang Province Patentee before: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd. |
|
| CP03 | Change of name, title or address |