CN104241137A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN104241137A CN104241137A CN201410285928.9A CN201410285928A CN104241137A CN 104241137 A CN104241137 A CN 104241137A CN 201410285928 A CN201410285928 A CN 201410285928A CN 104241137 A CN104241137 A CN 104241137A
- Authority
- CN
- China
- Prior art keywords
- tagma
- side wall
- bonding pad
- source region
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000002513 implantation Methods 0.000 claims description 20
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 14
- 229910001449 indium ion Inorganic materials 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 210000000746 body region Anatomy 0.000 abstract 9
- 150000002500 ions Chemical class 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a semiconductor substrate, a body region located in the semiconductor substrate, two gate structures and side walls, heavy doping source regions, low-resistance light doping source regions and a body region connection region, wherein the two gate structures and the side walls are located on the surface of the semiconductor substrate and located on the two sides of the body region, and the gate structures stretch across the body region and the edges of the semiconductor substrate; the heavy doping source regions are located in the exposed regions, between the side walls, of the body region; the low-resistance light doping source regions are located on the sides, close to the gate structures, of the heavy doping source regions; the body region connection region is located in the heavy doping source regions. The intervals between the body region connection region and the side walls are smaller than the minimum interval between a body region connection region and side walls in an existing process. Though the intervals between the body region connection region and the side walls become smaller, the current in a channel region can be electrically connected with the heavy doping source regions through conducting channels (the low-resistance light doping source regions) so that the turn-on resistance of an LDMOS transistor cannot be improved greatly, and the resource region size and conductivity property can be taken into consideration at the same time.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to semiconductor structure and the manufacture method thereof of position, a kind of LDMOS source region.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS) transistor is a kind of lightly doped MOS device, has extraordinary compatibility with CMOS technology.Conventional CMOS device is generally source and drain symmetrical structure, and ldmos transistor adopts source and drain unsymmetric structure to meet the demand of higher withstand voltage and relative low conducting resistance.
Please refer to Fig. 1 and Fig. 2, Fig. 1 is the plan structure schematic diagram of existing NLDMOS source transistor zone position, and Fig. 2 is the cross-sectional view along AA ' Linear cut in Fig. 1, comprising: Semiconductor substrate 10, is positioned at the tagma 20 of Semiconductor substrate 10; Be positioned at described Semiconductor substrate 10 and be positioned at two grid structures 40 and the side wall 41 of both sides, tagma 20, described grid structure 40 is across the edge of tagma 20 with Semiconductor substrate 10; In the tagma exposed between two side walls 41, there is heavy doping source region 31, be positioned at the light dope source region 32 of heavy doping source region 31 near grid structure 40 side, be positioned at the bonding pad, tagma 21 in described heavy doping source region 31, be positioned at the conductive plunger 22 on surface, bonding pad, tagma 21.Due to improving constantly along with integrated circuit integrated level, the size of NLDMOS transistor is constantly reducing, and two therefore adjacent NLDMOS transistors share and are same as a source region, and two grid structures in Fig. 1 and Fig. 2 belong to two NLDMOS transistors respectively.
But owing to needing bonding pad, organizator district 21 in heavy doping source region 31, the size of the width W 2 in the width W 1 of the bonding pad, tagma 21 therefore in Fig. 1 and the heavy doping source region 31 of both sides, bonding pad, tagma 21 can not reduce further, and the size of NLDMOS transistor can be caused to be not easy to reduce further.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor structure and manufacture method thereof, effectively can reduce the source region size of ldmos transistor.
For solving the problem, the embodiment of the present invention provides a kind of manufacture method of semiconductor structure, comprising: provide Semiconductor substrate, has tagma in described Semiconductor substrate; Form grid structure at described semiconductor substrate surface, described grid structure is across the edge of tagma and Semiconductor substrate; With described grid structure for mask, carry out the first foreign ion to the tagma between two grid structures and tilt to inject, bottom the body surface exposed and grid structure, submarginal position forms low-resistance light dope source region; Form side wall at described gate structure sidewall, with described side wall for mask, heavy doping source region is formed to the body surface exposed; Utilize photomask to carry out ion implantation in the position that described heavy doping source region is corresponding, form bonding pad, tagma, the spacing between the bonding pad, tagma formed and side wall is less than the minimum spacing under current process between bonding pad, tagma and side wall.
Optionally, when described semiconductor structure is the source structure of NLDMOS transistor, described first foreign ion is arsenic ion; When described semiconductor structure is the source structure of PLDMOS transistor, described first foreign ion is BF
2ion or indium ion.
Optionally, when described first foreign ion is arsenic ion, the Implantation Energy that described arsenic ion tilts to inject is 10KeV ~ 50KeV, implantation dosage is 5e13/ square centimeter ~ 1e14/ square centimeter, the angle injected is 7 degree ~ 15 degree, and the square resistance in described low-resistance light dope source region is 600 ohm ~ 1.2K ohm.
Optionally, when described first foreign ion is BF
2ion or indium ion, described BF
2the Implantation Energy that ion or indium ion tilt to inject is 10KeV ~ 100KeV, and implantation dosage is 5e13/ square centimeter ~ 1e14/ square centimeter, and the angle of injection is 7 degree ~ 15 degree, and the square resistance in described low-resistance light dope source region is 1K ohm ~ 2K ohm.
Optionally, the projection of bonding pad, tagma photomask pattern and side wall have lap.
Optionally, the photomask pattern of bonding pad, tagma is the minimum dimension figure of bonding pad, tagma under current process.
Optional, the photomask pattern of bonding pad, tagma is square, and the edge of described foursquare edge and side wall is 45 degree.
The embodiment of the present invention additionally provides a kind of semiconductor structure, comprising: Semiconductor substrate, is positioned at the tagma of Semiconductor substrate; Be positioned at described semiconductor substrate surface and be positioned at two grid structures and the side wall of both sides, tagma, described grid structure is across the edge of tagma and Semiconductor substrate; Heavy doping source region in the tagma exposed between side wall, be positioned at the low-resistance light dope source region of heavy doping source region near grid structure side, be positioned at the bonding pad, tagma in described heavy doping source region, the spacing between bonding pad, described tagma and side wall is less than the minimum spacing under current process between bonding pad, tagma and side wall.
Optionally, when described semiconductor structure is the source structure of NLDMOS transistor, first foreign ion in described low-resistance light dope source region is arsenic ion; When described semiconductor structure is the source structure of PLDMOS transistor, first foreign ion in described low-resistance light dope source region is BF
2ion or indium ion.
Optionally, when described semiconductor structure is the source structure of PLDMOS transistor, the square resistance in described low-resistance light dope source region is 1K ohm ~ 2K ohm.
Optionally, when described semiconductor structure is the source structure of NLDMOS transistor, the square resistance in described low-resistance light dope source region is 600 ohm ~ 1.2K ohm.
Optionally, bonding pad, described tagma contacts with side wall.
Optionally, the photomask pattern of bonding pad, tagma is square, and the described edge of square light mask graph and the edge of side wall are 45 degree.
Optionally, also comprise the conductive plunger being positioned at surface, bonding pad, tagma, the spacing between two side wall edges equals the twice of minimum spacing between side wall and conductive plunger, the width sum of conductive plunger.
Compared with prior art, the technical program has the following advantages:
The first impure ion injection technology is utilized to form low-resistance light dope source region in the position in light dope source region, conductive channel is formed in the tagma of the bottom of side wall, spacing between the bonding pad, tagma simultaneously formed and side wall is less than the minimum spacing under current process between bonding pad, tagma and side wall, although the pitch smaller between bonding pad, tagma and side wall, but because the electric current of channel region is electrically connected with heavy doping source region by conductive channel (low-resistance light dope source region), significantly can not improve the conducting resistance of ldmos transistor, therefore can take into account source region size and electric conductivity simultaneously.
Accompanying drawing explanation
Fig. 1 and Fig. 2 is the structural representation of the position, source region of the NLDMOS transistor of prior art;
Fig. 3 ~ Fig. 9 is the structural representation of the manufacturing process of the semiconductor structure of the embodiment of the present invention.
Embodiment
Inventor finds through research, the width W 1 of bonding pad, tagma 21 can not reduce further due to the restriction being subject to photoetching process, and the width W 2 in the heavy doping source region 31 of both sides, bonding pad, tagma 21 is not only the restriction being subject to photoetching process, the restriction of device performance also can be subject to.Due to transoid between bonding pad, tagma 21 and heavy doping source region 31, when the width W 2 between bonding pad, tagma 21 and side wall 41 is too small, the resistance in the heavy doping source region 31 of side, bonding pad, tagma 21 correspondence position can become large.Further research finds, mainly because existing light dope source region 32 is injected by the phosphonium ion of medium energy (being about 100KV) median dose (1e12 ~ 1e13/ square centimeter) wide-angle (being about 30 degree) formed, object is that the hot carrier meeting nmos pass transistor causes device property to degenerate the life requirements of (HCI), but resistance is larger under source side wall, and the diffusion velocity of phosphonium ion is fast, parasitic base resistance is larger.If when the width W of correspondence 2 is also too small, the conducting resistance of NLDMOS transistor can be had a strong impact on.
Therefore a kind of semiconductor structure and manufacture method thereof is embodiments provided, the first impure ion injection technology is utilized to form low-resistance light dope source region in the position in light dope source region, conductive channel is formed in the tagma of the bottom of side wall, spacing between the bonding pad, tagma simultaneously formed and side wall is less than the minimum spacing under current process between bonding pad, tagma and side wall, although the pitch smaller between bonding pad, tagma and side wall, but because the electric current of channel region is electrically connected with heavy doping source region by conductive channel (low-resistance light dope source region), significantly can not improve the conducting resistance of ldmos transistor, therefore can take into account source region size and electric conductivity simultaneously.
Below in conjunction with accompanying drawing, by specific embodiment, clear, complete description is carried out to technical scheme of the present invention.Due to the source structure utilizing the manufacture method of the semiconductor structure of the embodiment of the present invention can manufacture NLDMOS transistor or PLDMOS transistor respectively, in the present embodiment, be described for the manufacture process of source structure to the semiconductor structure of the embodiment of the present invention manufacturing NLDMOS transistor.
Please refer to Fig. 3 ~ Fig. 9, is the structural representation of the manufacture process of the semiconductor structure of the embodiment of the present invention.
Please refer to Fig. 3, Semiconductor substrate 110 is provided, there is in described Semiconductor substrate 110 P type tagma 120.
In the present embodiment, ldmos transistor due to correspondence is NLDMOS transistor, and therefore described Semiconductor substrate 110 is N-type substrate, and the formation process in described P type tagma 120 is ion implantation technology, after ion implantation, annealing process is utilized to carry out moving back knot and activator impurity.
In other embodiments, N-type well region can also be formed in Semiconductor substrate 110, in N-type well region, form P type tagma 120.
Please refer to Fig. 4, form grid structure 140 on described Semiconductor substrate 110 surface.
Before formation grid structure 140, be also included in Semiconductor substrate and form fleet plough groove isolation structure, the processing steps such as P type trap zone, the formation process due to NLDMOS drain region is not protection main points of the present invention, does not describe in detail at this.
Described grid structure 140 is polysilicon gate construction or metal gate structure etc.In the present embodiment, described grid structure 140 is polysilicon gate construction, comprises gate oxide and the polysilicon gate being positioned at gate oxide surface.In other embodiments, when after employing, grid technique forms metal gate structure, described grid structure also can be the pseudo-grid of polysilicon.
Please refer to Fig. 5, with described grid structure 140 for mask, carry out arsenic ion to the P type tagma 120 between two grid structures 140 to tilt to inject, bottom the surface, P type tagma 120 exposed and grid structure 140, submarginal position forms low-resistance light dope source region 132.
In the present embodiment, because manufactured ldmos transistor is NLDMOS transistor, the first foreign ion tagma between two grid structures being carried out to the first foreign ion inclination injection is arsenic ion, the Implantation Energy that described arsenic ion tilts to inject is 10KeV ~ 50KeV, implantation dosage is 5e13/ square centimeter ~ 1e14/ square centimeter, the angle injected is 7 degree ~ 15 degree, and the square resistance in the final low-resistance light dope source region 132 formed is 600 ohm ~ 1.2K ohm.
Implantation Energy due to described arsenic ion inclination injection is less than the Implantation Energy in existing light dope source region, and implantation dosage is greater than the implantation concentration in existing light dope source region, therefore can effectively reduce the resistance under NLDMOS source side wall; Arsenic Speed of diffusion is slow simultaneously, and comparatively phosphorus injects, and can obtain less parasitic base resistance, improves breakdown characteristics when affecting break-over of device.
Because position submarginal bottom grid structure 140 is also formed with low-resistance light dope source region 132, therefore be positioned at submarginal position bottom grid structure 140 and can form conductive channel, even if bonding pad, follow-up tagma contacts with side wall, electric current in the channel region of bonding pad, tagma correspondence position can flow to the heavy doping source region of other positions by conductive channel, form path.
Please refer to Fig. 6, form side wall 141 at described grid structure 140 sidewall, with described side wall 141 for mask, ion implantation is carried out to the surface, P type tagma 120 exposed and forms N-type heavy doping source region 131.
While the described N-type heavy doping source region 131 of formation, in the position, drain region of NLDMOS transistor, correspondence forms N-type heavy doping drain region (not shown).
Please refer to Fig. 7, photomask is utilized to carry out ion implantation in the position of described N-type heavy doping source region 131 correspondence, form bonding pad, P type tagma 121, the spacing between the bonding pad, P type tagma 121 formed and side wall 141 is less than the minimum spacing under current process between bonding pad, P type tagma and side wall.
The degree of depth of bonding pad, described P type tagma 121 is more than or equal to the degree of depth in N-type heavy doping source region 131, and bonding pad, P type tagma 121 is connected with P type tagma 120 electricity, follow-up at surface, bonding pad 121, P type tagma formation conductive plunger.
In the present embodiment, the overlapping margins of bonding pad, described P type tagma 121 and both side walls 141.In other embodiments, bonding pad, described P type tagma contacts with side wall.Or described bonding pad, P type tagma and side wall are separated, and the spacing between bonding pad, P type tagma and side wall is less than the minimum spacing under current process between bonding pad, P type tagma and side wall.
In the present embodiment, there is lap for the formation of the projection of the photomask pattern of bonding pad, P type tagma 121 and side wall, the overlapping margins of the bonding pad, P type tagma 121 that final ion implantation is formed and both side walls 141.
In one embodiment, the photomask pattern of bonding pad, described P type tagma 121 is square, and the edge of described foursquare edge and side wall is 45 degree, and described square is the minimum dimension figure of bonding pad, tagma under current process.
When identical graphics area, because 45 degree of squares rotated can cause the intersection between bonding pad, P type tagma and side wall the shortest, the distance that drain current is flowed at conductive channel (the low-resistance light dope source region 132 bottom side wall) is the shortest.Although the resistance in low-resistance light dope source region 132 is lower, due to the existence of HCI, doping content can not be too high, and therefore drain current is more short better in the flow distance of conductive channel.Size due to bonding pad, P type tagma mask pattern is subject to the restriction of technique can not be too small, therefore the minimum dimension figure of bonding pad, tagma under the photomask pattern of bonding pad, P type tagma is current process, long and wide determine after, in order to reduce the flow distance of drain current at conductive channel further, be provided with angle by between the photomask pattern of bonding pad, P type tagma and side wall.Therefore, in the present embodiment, the photomask pattern of bonding pad, P type tagma is square, and the edge of described foursquare edge and side wall is 45 degree.
Due to the existence in the low-resistance light dope source region 132 bottom side wall, the spacing between bonding pad, P type tagma 121 and side wall 141 can infinitely reduce.Even if bonding pad, P type tagma 121 contacts with side wall 141 completely, N-type heavy doping source region 131 is separated into several part, but due to the existence in low-resistance light dope source region 132, several N-type heavy doping source regions 131 of separating still electricity connect, total conducting resistance significantly can not change because of the change in location of bonding pad, P type tagma 121, therefore can take into account source region size and electric conductivity simultaneously.
Please refer to Fig. 8 and Fig. 9, the plan structure schematic diagram that Fig. 9 is the semiconductor structure shown in Fig. 8, form conductive plunger 122 on surface, bonding pad 121, described P type tagma and surface, N-type heavy doping source region 131.
Because the spacing between bonding pad, P type tagma 121 and side wall 141 can infinitely reduce, the distance between described two source regions depends on the width of minimum spacing and conductive plunger between side wall and conductive plunger.In the present embodiment, the twice that the spacing (i.e. the width in N-type heavy doping source region 131) between described two side walls 141 is minimum spacing between side wall and conductive plunger, the width sum of conductive plunger.In other embodiments, the spacing between described two side walls 141 can slightly larger than the width sum of the twice of minimum spacing between side wall and conductive plunger, conductive plunger.
In another embodiment, because the concrete steps of the source structure manufacturing PLDMOS transistor are similar to the concrete steps of the source structure of NLDMOS transistor processed, something in common does not repeat.Because both differences are only the contrary of Doped ions electrical type, in the present embodiment, tagma, bonding pad, tagma are P type, heavy doping source region, low-resistance light dope source region are N-type, and in another embodiment, tagma, bonding pad, tagma are N-type, and heavy doping source region, low-resistance light dope source region are P type, and described first foreign ion is BF
2ion or indium ion, described BF
2the Implantation Energy that ion or indium ion tilt to inject is 10KeV ~ 100KeV, and implantation dosage is 5e13/ square centimeter ~ 1e14/ square centimeter, and the angle of injection is 7 degree ~ 15 degree, and the square resistance in described low-resistance light dope source region is 1K ohm ~ 2K ohm.
The embodiment of the present invention additionally provides a kind of semiconductor structure, please refer to Fig. 8 and Fig. 9, comprising: Semiconductor substrate 110, is positioned at the P type tagma 120 of Semiconductor substrate 110; Be positioned at described Semiconductor substrate 110 surface and be positioned at two grid structures 140 and the side wall 141 of both sides, P type tagma 120, described grid structure 140 is across the edge of P type tagma 120 with Semiconductor substrate 110; N-type heavy doping source region 131 in the P type tagma 120 exposed between side wall 140, be positioned at the low-resistance light dope source region 132 of N-type heavy doping source region 131 near grid structure 140 side, be positioned at the bonding pad, P type tagma 121 in described N-type heavy doping source region 131, the spacing between bonding pad, described P type tagma 121 and side wall 141 is less than the minimum spacing under current process between bonding pad, P type tagma and side wall.
In the present embodiment, when described first foreign ion is arsenic ion, the formation process in described low-resistance light dope source region is: the Implantation Energy that arsenic ion tilts to inject is 10KeV ~ 50KeV, implantation dosage is 5e13/ square centimeter ~ 1e14/ square centimeter, the angle injected is 7 degree ~ 15 degree, and the square resistance in described low-resistance light dope source region is 600 ohm ~ 1.2K ohm.
In the present embodiment, the photomask pattern due to bonding pad, P type tagma 121 is square, and the edge of described foursquare edge and side wall is 45 degree, and bonding pad, described P type tagma contacts with side wall.
In other embodiments, bonding pad, described P type tagma can also be other figures, such as rectangle, circular lamp, and the spacing between described bonding pad, P type tagma and side wall is less than the minimum spacing under current process between bonding pad, P type tagma and side wall.
In the present embodiment, the spacing also comprised between conductive plunger 122, two side walls being positioned at surface, bonding pad 121, P type tagma equals the twice of minimum spacing between side wall and conductive plunger and the width sum of conductive plunger.
In the present embodiment, described semiconductor structure is the source structure of NLDMOS transistor, and in other embodiments, when described semiconductor structure is the source structure of PLDMOS transistor, described first foreign ion is BF
2ion or indium ion, described BF
2the Implantation Energy that ion or indium ion tilt to inject is 10KeV ~ 100KeV, and implantation dosage is 5e13/ square centimeter ~ 1e14/ square centimeter, and the angle of injection is 7 degree ~ 15 degree, and the square resistance in described low-resistance light dope source region is 1K ohm ~ 2K ohm.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (14)
1. a manufacture method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, there is tagma;
Form grid structure at described semiconductor substrate surface, described grid structure is across the edge of tagma and Semiconductor substrate;
With described grid structure for mask, carry out the first foreign ion to the tagma between two grid structures and tilt to inject, bottom the body surface exposed and grid structure, submarginal position forms low-resistance light dope source region;
Form side wall at described gate structure sidewall, with described side wall for mask, heavy doping source region is formed to the body surface exposed;
Utilize photomask to carry out ion implantation in the position that described heavy doping source region is corresponding, form bonding pad, tagma, the spacing between the bonding pad, tagma formed and side wall is less than the minimum spacing under current process between bonding pad, tagma and side wall.
2. the manufacture method of semiconductor structure as claimed in claim 1, it is characterized in that, when described semiconductor structure is the source structure of NLDMOS transistor, described first foreign ion is arsenic ion; When described semiconductor structure is the source structure of PLDMOS transistor, described first foreign ion is BF
2ion or indium ion.
3. the manufacture method of semiconductor structure as claimed in claim 2, it is characterized in that, when described first foreign ion is arsenic ion, the Implantation Energy that described arsenic ion tilts to inject is 10KeV ~ 50KeV, implantation dosage is 5e13/ square centimeter ~ 1e14/ square centimeter, the angle injected is 7 degree ~ 15 degree, and the square resistance in described low-resistance light dope source region is 600 ohm ~ 1.2K ohm.
4. the manufacture method of semiconductor structure as claimed in claim 2, is characterized in that, when described first foreign ion is BF
2ion or indium ion, described BF
2the Implantation Energy that ion or indium ion tilt to inject is 10KeV ~ 100KeV, and implantation dosage is 5e13/ square centimeter ~ 1e14/ square centimeter, and the angle of injection is 7 degree ~ 15 degree, and the square resistance in described low-resistance light dope source region is 1K ohm ~ 2K ohm.
5. the manufacture method of semiconductor structure as claimed in claim 1, it is characterized in that, projection and the side wall of bonding pad, tagma photomask pattern have lap.
6. the manufacture method of semiconductor structure as claimed in claim 1, it is characterized in that, the photomask pattern of bonding pad, tagma is the minimum dimension figure of bonding pad, tagma under current process.
7. the manufacture method of semiconductor structure as claimed in claim 1, is characterized in that, the photomask pattern of bonding pad, tagma is square, and the edge of described foursquare edge and side wall is 45 degree.
8. a semiconductor structure, is characterized in that, comprising: Semiconductor substrate, is positioned at the tagma of Semiconductor substrate; Be positioned at described semiconductor substrate surface and be positioned at two grid structures and the side wall of both sides, tagma, described grid structure is across the edge of tagma and Semiconductor substrate; Heavy doping source region in the tagma exposed between side wall, be positioned at the low-resistance light dope source region of heavy doping source region near grid structure side, be positioned at the bonding pad, tagma in described heavy doping source region, the spacing between bonding pad, described tagma and side wall is less than the minimum spacing under current process between bonding pad, tagma and side wall.
9. semiconductor structure as claimed in claim 8, it is characterized in that, when described semiconductor structure is the source structure of NLDMOS transistor, first foreign ion in described low-resistance light dope source region is arsenic ion; When described semiconductor structure is the source structure of PLDMOS transistor, first foreign ion in described low-resistance light dope source region is BF
2ion or indium ion.
10. semiconductor structure as claimed in claim 9, it is characterized in that, when described semiconductor structure is the source structure of PLDMOS transistor, the square resistance in described low-resistance light dope source region is 1K ohm ~ 2K ohm.
11. semiconductor structures as claimed in claim 9, is characterized in that, when described semiconductor structure is the source structure of NLDMOS transistor, the square resistance in described low-resistance light dope source region is 600 ohm ~ 1.2K ohm.
12. semiconductor structures as claimed in claim 8, it is characterized in that, bonding pad, described tagma contacts with side wall.
13. semiconductor structures as claimed in claim 12, is characterized in that, the photomask pattern of bonding pad, tagma is square, and the described edge of square light mask graph and the edge of side wall are 45 degree.
14. semiconductor structures as claimed in claim 8, it is characterized in that, also comprise the conductive plunger being positioned at surface, bonding pad, tagma, the spacing between two side wall edges equals the twice of minimum spacing between side wall and conductive plunger, the width sum of conductive plunger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410285928.9A CN104241137B (en) | 2014-06-24 | 2014-06-24 | Semiconductor structure and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410285928.9A CN104241137B (en) | 2014-06-24 | 2014-06-24 | Semiconductor structure and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104241137A true CN104241137A (en) | 2014-12-24 |
| CN104241137B CN104241137B (en) | 2017-08-08 |
Family
ID=52228986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410285928.9A Active CN104241137B (en) | 2014-06-24 | 2014-06-24 | Semiconductor structure and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104241137B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151618A (en) * | 2020-09-27 | 2020-12-29 | 杰华特微电子（杭州）有限公司 | Manufacturing method of transverse super junction structure |
| CN115101477A (en) * | 2022-08-24 | 2022-09-23 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116207142A (en) * | 2023-05-04 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719421A (en) * | 1994-10-13 | 1998-02-17 | Texas Instruments Incorporated | DMOS transistor with low on-resistance and method of fabrication |
| US8546879B2 (en) * | 2011-08-18 | 2013-10-01 | Monolithic Power Systems, Inc. | High density lateral DMOS with recessed source contact |
-
2014
- 2014-06-24 CN CN201410285928.9A patent/CN104241137B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151618A (en) * | 2020-09-27 | 2020-12-29 | 杰华特微电子（杭州）有限公司 | Manufacturing method of transverse super junction structure |
| CN115101477A (en) * | 2022-08-24 | 2022-09-23 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115101477B (en) * | 2022-08-24 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116207142A (en) * | 2023-05-04 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104241137B (en) | 2017-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9087774B2 (en) | LDMOS device with short channel and associated fabrication method | |
| US9997626B2 (en) | NLDMOS device and method for manufacturing the same | |
| JP5833277B1 (en) | Semiconductor device | |
| KR101699585B1 (en) | High voltage semiconductor device and method of manufacturing the same | |
| JP6615348B2 (en) | Laterally diffused metal oxide semiconductor field effect transistor | |
| US10366981B2 (en) | Power semiconductor devices | |
| CN104979398A (en) | Semiconductor Device and Method for Forming a Semiconductor Device | |
| CN104576368A (en) | Method for forming reverse-conducting IGBT (insulated gate bipolar translator) backside process | |
| CN103855210A (en) | Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof | |
| CN104241137A (en) | Semiconductor structure and manufacturing method thereof | |
| CN102263125A (en) | Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides | |
| KR20170114703A (en) | Gate electrode structure and high voltage semiconductor device having the same | |
| CN104201203B (en) | High withstand voltage LDMOS device and manufacture method thereof | |
| JP2008060152A (en) | Semiconductor device, and its manufacturing method | |
| JP2006261562A (en) | Semiconductor device | |
| CN103022125A (en) | NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method | |
| CN106816463B (en) | Terminal structure, semiconductor device and preparation method thereof | |
| CN102569404B (en) | Transverse diffusion metal oxide semiconductor (MOS) device with low on-resistance | |
| KR20110078861A (en) | Lateral double diffused metal oxide semiconductor | |
| CN103515414A (en) | Transistor device and manufacturing method thereof | |
| CN106941122A (en) | Semiconductor device and its manufacture method | |
| US9780171B2 (en) | Fabricating method of lateral-diffused metal oxide semiconductor device | |
| KR102088548B1 (en) | High voltage semiconductor device | |
| CN103137694A (en) | Surface channel field effect transistor and manufacture method thereof | |
| CN102956479B (en) | Insulated gate bipolar transistor structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Patentee after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 424, building 1, 1500 Wenyi West Road, Cangqian street, Yuhang District, Hangzhou City, Zhejiang Province Patentee before: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd. |