CN104218007A - 小脚印半导体封装 - Google Patents

小脚印半导体封装 Download PDF

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Publication number
CN104218007A
CN104218007A CN201410236577.2A CN201410236577A CN104218007A CN 104218007 A CN104218007 A CN 104218007A CN 201410236577 A CN201410236577 A CN 201410236577A CN 104218007 A CN104218007 A CN 104218007A
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Prior art keywords
terminal
type surface
semiconductor element
electrode
semiconductor
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Granted
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CN201410236577.2A
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CN104218007B (zh
Inventor
龙登超
陈天山
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

公开了一种小脚印半导体封装。一种半导体组装包括具有导电区域的衬底和半导体封装。半导体封装包括半导体管芯、第一端子和第二端子以及模制化合物。管芯具有相对的第一主表面和第二主表面、与所述第一主表面和第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极。所述第一端子附接到所述第一电极。所述第二端子附接到所述第二电极。所述模制化合物包围管芯以及所述第一端子和所述第二端子的至少一部分，从而所述端子中的每一个具有平行于并且背对管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖。所述半导体封装的所述第一端子和所述第二端子连接到所述衬底的所述导电区域中的不同区域。

Description

小脚印半导体封装
技术领域
本申请涉及半导体封装，并且更特别地，涉及具有小脚印（footprint）的半导体封装。
背景技术
具有半导体管芯（芯片）的常规高功率半导体封装要求相对大的PCB（印制电路板）脚印。管芯的两个主表面典型地具有一个或更多个电极。在一个主表面面对PCB并且另一主表面背对PCB的情况下将管芯附接到PCB。在管芯的面对表面处所设置的每个电极例如以源极向下（source-down）或漏极向下（drain-down）的配置而附接到PCB的对应导电区域。金属夹或其它连接元件（诸如接合布线或条带）从PCB延伸到管芯的另一主表面，以使得与在背对PCB的管芯的表面处所设置的每个电极电连接。在PCB的表面上要求有很多‘方形’（即1平方毫米的单元）以容纳这样的源极向下或漏极向下封装配置，这增加了封装的成本。此外，在面对衬底的管芯的主表面处所排放的热量至少部分地通过PCB/衬底耗散。常规的PCB因此必须为安装在PCB上的部件提供电路径和热路径这两者，造成大量部件共享所设计的PCB的热路径。
发明内容
根据半导体封装的实施例，所述封装包括：半导体管芯,具有相对的第一主表面和第二主表面、与所述第一主表面和第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极。所述封装进一步包括：附接到所述第一电极的第一端子、附接到所述第二电极的第二端子、以及模制化合物。所述模制化合物包围所述半导体管芯以及所述第一端子和第二端子的至少一部分，从而所述第一端子和第二端子中的每一个具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖。从所述模制化合物形成的、或者从所述模制化合物突出出来的突起被设置在所述第一端子与第二端子之间。所述突起在所述半导体封装的同一侧面处比所述第一端子和第二端子向外延伸得更远。
根据半导体封装的另一实施例，所述封装包括：半导体管芯,具有相对的第一主表面和第二主表面、与所述第一主表面和第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极。所述封装进一步包括：附接到所述第一电极的第一端子、附接到所述第二电极的第二端子、以及模制化合物。所述模制化合物包围所述半导体管芯以及所述第一端子和第二端子的至少一部分，从而所述第一端子和第二端子中的每一个具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖。致冷结构被图案化到所述第一端子和第二端子中的至少一个的至少部分未被覆盖的侧面，以用于增加该侧面的表面面积。
根据半导体组装的实施例，所述组装包括衬底和半导体封装。所述衬底具有导电区域。所述半导体封装包括：半导体管芯,具有相对的第一主表面和第二主表面、与所述第一主表面和第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极。所述半导体封装进一步包括：第一端子，附接到所述第一电极；第二端子，附接到所述第二电极；以及模制化合物，包围所述半导体管芯以及所述第一端子和第二端子的至少一部分，从而所述第一端子和第二端子中的每一个具有平行于并且背对所述半导体管芯侧面，所述侧面保持为至少部分未被所述模制化合物覆盖。所述半导体封装的所述第一端子和第二端子连接到所述衬底的所述导电区域中的不同区域。
根据制造半导体封装的方法的实施例，所述方法包括：将管芯附接材料施加到半导体管芯的第一主表面，所述半导体管芯还具有相对的第二主表面、与所述第一主表面和第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极；旋转所述半导体管芯，从而所述半导体管芯的所述第一主表面面对第一端子；经由施加到所述第一主表面的所述管芯附接材料将所述第一电极附接到所述第一端子；将管芯附接材料施加到所述半导体管芯的所述第二主表面；旋转具有所附接的所述第一端子的所述半导体管芯，从而所述半导体管芯的所述第二主表面面对第二端子；以及经由施加到所述第二主表面的所述管芯附接材料将所述第二电极附接到所述第二端子。
根据制造半导体封装的方法的另一实施例，所述方法包括：将管芯附接材料施加到半导体管芯的第一主表面和所述半导体管芯的相对的第二主表面，所述半导体管芯进一步具有：与所述第一主表面和第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极；将具有所述管芯附接材料的所述半导体管芯插入到第一端子与第二端子之间的间隙中；以及在将所述半导体管芯插入到第一端子与第二端子之间的间隙中之后，经由施加到所述第一主表面的所述管芯附接材料将所述第一电极附接到所述第一端子，并且经由施加到所述第二主表面的所述管芯附接材料将所述第二电极附接到所述第二端子。
在阅读下面的详细描述并且查看随附的附图时，本领域技术人员将认识到附加的特征和优点。
附图说明
图中的部件并不一定成比例，相反重点被放在图解本发明的原理。此外，图中同样的标号指明对应的部分。在附图中：
图1图解附接到衬底的小脚印半导体封装的横截面视图；
图2A和图2B图解图1的封装中所包括的半导体管芯的相对的主表面的立视图；
图3图解根据另一实施例的小脚印半导体封装的横截面视图；
图4A至图4C图解在衬底上的不同组装阶段期间小脚印半导体封装的横截面视图；
图5A至图5C图解小脚印半导体封装的不同实施例的横截面视图；
图6A至图6C图解在插入到衬底上的插槽期间小脚印半导体封装的两个相对的横截面视图（图6A和图6B）以及一个对应的立视图（图6C）；
图7A至图7C图解根据两个不同实施例的小脚印半导体封装的底部立视图（图7A）和顶部立视图（图7B和图7C）；
图8A和图8B图解根据又一实施例的小脚印半导体封装的横截面视图；
图9A和图9B图解在封装的一个或更多个端子上具有致冷结构的小脚印半导体封装的不同侧面立视图；
图10A和图10B图解在封装的一个或更多个端子上具有翅片型致冷结构的小脚印半导体封装的不同侧面立视图；
图11包括图11A至图11E，图解制造小脚印半导体封装的方法的实施例；
图12包括图12A至图12C，图解制造小脚印半导体封装的方法的另一实施例。
具体实施方式
在此所描述的实施例提供一种半导体封装，用于安装到PCB或其它类型的衬底，从而所述封装中所包括的半导体管芯在其边缘面对衬底而不是所述管芯的任一主表面面对衬底的情况下被安装。这样的配置获得在管芯的两个主表面处的小封装脚印和更大的热量耗散。接下来所描述的各个实施例有关于半导体封装自身、包括这样的封装的半导体组装以及制造所述封装的方法。封装中所包括的半导体管芯可以是任意类型的半导体管芯，诸如IGBT（绝缘栅双极晶体管）管芯、功率MOSFET（金属氧化物半导体场效应晶体管）管芯、JFET（结型场效应晶体管）管芯、GaN管芯、SiC管芯、晶闸管管芯、功率二极管管芯、功率集成电路等。半导体管芯典型地具有从在管芯的一个主表面处的电极中的一个到在管芯的相对的主表面处的另一电极的电流流动路径。该半导体封装可以用于安装在相同或不同衬底上的其它半导体封装和部件，以形成任意类型的想要的电路（诸如半桥、全桥或三相电路等）。
图1图解安装、焊接或以其它方式附接到诸如PCB或层叠物的衬底102、具有顶部金属化表面和底部金属化表面的陶瓷材料、引线框的引线等的半导体封装100的横截面视图。半导体封装100包括例如在此于先前描述的种类的半导体管芯104。管芯104具有相对的第一主表面106和第二主表面108、与第一主表面106和第二主表面108垂直设置的边缘110、在第一主表面106处的至少一个电极112、114以及在第二主表面108处的至少一个第二电极116。在二极管管芯的情况下，阳极电极114设置在管芯104的一个主表面106处，并且阴极电极116设置在相对的主表面108处。在功率晶体管管芯104的情况下，栅极电极112和源极（发射极）电极114设置在管芯104的第一主表面106处，并且漏极（集电极）电极116设置在相对的主表面108处。管芯104的边缘110没有电极。
图2A示出管芯104的第一主表面106，其面对在封装100的该侧面处的一个或更多个对应端子118，并且图2B示出管芯的第二（相对）主表面108，其面对在封装100的相对侧面处的一个或更多个对应端子120。图2A所示的主管芯表面106包括晶体管管芯104的栅极电极112和源极电极114。图2B所示的相对的管芯表面108包括晶体管管芯104的漏极电极116。封装100包括根据该实施例的三个端子118、120：在管芯104的第一主表面106处的两个端子118，用于接触栅极电极112和源极电极114；在第二（相对）主表面108处的一个端子120，用于接触漏极电极116。当然，取决于用于如上面描述的管芯的管芯类型和电极配置，其它端子配置是可能的。栅极端子隐藏在源极端子118之后，因此在图1中不可见。
电极112、114、116可以是金属焊盘或典型地设置在半导体管芯104的表面106、108上的其它类型的结构，用于使得对于管芯104电接触。封装端子118、120可以是金属夹或典型地用于接触管芯104的电极112、114、116的其它类型的结构。如图1所示，封装端子118、120可以是L形的，具有基底区域118’/120’以及从相应的基底区域118’/120’垂直延伸的延伸区域118’’/120’’。每个端子118、120的基底区域118’/120’连接到衬底102的对应导电区域122、124，例如PCB的迹线（trace）、陶瓷材料上的图案化的金属化部、引线框的引线等。
管芯104的电极112、114、116经由管芯附接材料126、128、130（诸如焊料膏）焊接到或以其它方式附接到对应端子118、120，以形成封装100。半导体封装100然后被安装、焊接或以其它方式附接到衬底102，以形成如图1所示的半导体组装。封装100中所包括的半导体管芯104的边缘110面对衬底102，并且封装100的端子118、120连接到衬底102的导电区域122、124中的不同区域。以此方式，归因于边缘向下安装配置，因此封装100具有非常小的脚印。此外，用于封装100的主热量耗散路径不通过衬底102，而是通过封装100的两个侧面上的端子118、120，如图1所示的箭头所指示的那样。半导体组装可以包括相同或不同的半导体封装的附加封装以及安装到衬底的其它有源和/或无源部件（诸如电感器、电容器、变压器、电源等），以形成电路。
图3图解在进行衬底附接之前的半导体封装100的另一实施例的横截面视图。图3所图解的实施例与图1所图解的实施例相似，然而，封装100的端子118、120不是L形的。替代地，封装端子118、120在每个端子118、120的整个长度（L）上具有均匀的横截面面积（A）。
图4A至图4C示出在包括模制和对封装102进行附接的后续处理期间图3的半导体封装100的横截面视图。在图4A中，模制化合物132（诸如硅树脂、环氧树脂等）包围或包封半导体管芯104和端子118、120的至少一部分，从而每个端子118、120的平行于并且背对半导体管芯104的外部或外侧面134保持为至少部分未被模制化合物132覆盖。通过让每个端子118、120的外部或外侧面134至少部分地未被模制化合物132覆盖，来增加封装100进行的热量耗散。
进一步根据该实施例，由模制化合物132形成突起136。突起136设置在端子118、120之间，并且在半导体封装100的同一侧面处比端子118、120向外延伸得更远。另外根据该实施例，半导体管芯104被包围在由模制化合物132和端子118、120形成的空气腔138内。替换地，模制化合物132可以填充端子118、120与管芯104之间的所有开放间隙，从而管芯104完全被模制化合物132包住（覆盖）。在任一情况下，每个端子118、120的平行于并且背对半导体管芯104的外部或外侧面134保持为至少部分未被模制化合物132覆盖。
图4B示出被设计为容纳具有由模制化合物132形成的突起136的半导体封装100的衬底102的横截面视图。根据该实施例，衬底102具有用于容纳突起136的凹槽140。此外，衬底102的随后要连接到封装100的端子118、120的导电区域122、124设置在衬底102的顶表面142上。
图4C示出在如由图4C中用椭圆标记的“按压配合连接”指示那样以按压配合型连接将封装100的突起136插入到并容纳于形成在衬底102中的凹槽140之后的得到的组装的横截面视图。每个端子118、120的至少部分地未被覆盖的外部或外侧面134例如经由弹性或弹簧作用力抵靠衬底102的与衬底102的顶表面142垂直的对应导电区域122、124的侧面123、125而被按压，如图4C中用椭圆标记的“靠紧连接”所指示的那样。封装100的端子118、120可以被焊接到衬底102的对应导电区域122、124，以获得封装100与衬底102之间的更持久的连接。
图5A至图5C示出在进行模制之前半导体封装100的又一附加实施例的横截面视图。在图5A中，半导体管芯104的边缘110在端子118、120的要被安装到衬底的端部119、121处与端子118、120齐平。在图5B中，半导体管芯104的部分在端子118、120的要被安装到衬底的侧面119、121处比端子118、120向外延伸得更远。根据该实施例，半导体管芯104的比端子118、120向外延伸得更远的部分形成突起105，突起105被设计为由形成在衬底中的凹槽（例如，诸如图4B所示的凹槽140）容纳。在图5C中，半导体管芯104的边缘110既不像图5A所示那样与端子118、120的任一端部齐平，管芯边缘110也不像图5B所示那样延伸超过端子118、120的任一端部。
图6A和图6B示出半导体封装100的垂直侧面101、103的立视图。在该实施例中，半导体管芯104是功率晶体管管芯，并且封装100包括：在封装100的一个垂直侧面101处的栅极端子200和源极（或发射极）端子204，用于连接到管芯104的对应栅极电极112和源极（或发射极）电极114；以及在封装100的相对的垂直侧面103处的漏极（或集电极）端子204，用于连接到管芯104的漏极（或集电极）电极116。管芯104在图6A和图6B中被模制化合物132覆盖，因此不可见。源极（发射极）端子202和漏极（集电极）端子204的位置可以转换。图6A示出具有栅极端子200和源极（或发射极）端子202的封装100的侧面101，图6B示出具有漏极（或集电极）端子204的封装100的相对侧面103。根据该实施例，封装100的每个垂直侧面101、103的边缘被模制化合物132覆盖，而每个端子200、202、204的平行于并且背对半导体管芯104的外部或外侧面134保持为至少部分未被模制化合物132覆盖。
进一步根据该实施例，封装端子200、202、204中的每一个具有在每个端子200、202、204的至少部分地未被覆盖的侧面134的一个端部处所设置的一个或更多个接触焊盘206。接触焊盘206被设计为接触在半导体封装100要插入到的衬底的表面上所设置的插槽210中所包括的对应接触焊盘208。图6A和图6B还示出插槽210的对应侧面的横截面视图。插槽210具有基底212和带有用于容纳封装100的相对内部侧面211、213的开放区域214。插槽210的每个内部侧面211、213具有接触焊盘208，接触焊盘208被设计为使得在把封装100插入在插槽210中之时与靠紧插槽210的该侧面211、213的（多个）封装端子200/202/204的对应焊盘206接触。图6A和图6B中的面向下的箭头指示封装插入方向。图6C示出在插入到衬底的插槽210之后具有栅极端子200和源极（或发射极）端子202的封装100的侧面101的立视图。为了易于图解而未在图6A至图6C中示出衬底，但是可以是任意类型的在此于先前描述的衬底。
图7A示出根据实施例的半导体封装100的底部平面视图。端子200、202、204保持为在封装100的底部侧面（即封装100的要附接到衬底的侧面）处未被模制化合物132覆盖。
图7B示出根据实施例的半导体封装100的顶部平面视图。根据该实施例，端子200、202、204还保持为在封装100的顶部侧面（即封装100的背对衬底的侧面）处未被模制化合物132覆盖。
图7C示出根据替换的实施例的半导体封装100的顶部平面视图，其中，端子200、202、204在封装100的顶部侧面处被模制化合物132覆盖。在每种情况下，每个端子200、202、204的平行于并且背对半导体管芯104的外部或外侧面134保持为至少部分未被模制化合物132覆盖。根据该实施例，半导体封装100可以被表面安装在衬底上。
图8A和图8B示出根据另一实施例的在进行模制之前（图8A）和在进行模制之后（图8B）的半导体封装100的横截面视图。根据该实施例，每个端子118、120具有带有凹槽300的第一端部119、121和带有凹槽300的相对的第二端部301、303。模制化合物132在模制处理之后在端子118、120的两个端部119/121、301、303处填充凹槽300，如图8B所示。
图9A和图9B示出根据再一实施例的半导体封装100的视图。图9A示出在封装端子118、120的横向侧面处看去的封装100的第一侧面立视图，图9B示出在端子118、120的主侧面处看去的封装100的第二侧面立视图。为了易于图解，图9A和图9B未示出模制化合物132。根据该实施例，致冷结构400被图案化到端子118、120中的一个或更多个的平行于并且背对半导体管芯104的外部或外侧面134。致冷结构400增加端子118/120的露出的表面面积，改进了封装100的热量耗散特性。在铜端子118、120的情况下，致冷结构400可以被刻蚀到端子118、120的至少部分未被覆盖的侧面134，以包括带有这样的结构的预成型或后成型引线框或夹。在铝端子118、120的情况下，可以通过模压（extrusion）形成致冷结构400。在一个实施例中，致冷结构400是图案化到端子118、120中的一个或更多个的平行于并且背对半导体管芯104的外部或外侧面134的翅片型结构。翅片可以具有任何类型的形状（例如矩形、三角形等）。可以替代地使用其它致冷结构形状，诸如柱形或针形致冷结构。
图10A和图10B示出根据不同实施例的具有翅片型致冷结构400的封装端子118/120中的一个的立视图。在图10A的实施例中，翅片型致冷结构400沿着端子118/120的平行于并且背对半导体管芯104的外部或外侧面134的长度（L）延伸。在图10B的实施例中，翅片型致冷结构400沿着端子118/120的平行于并且背对半导体管芯104的外部或外侧面134的宽度（W）延伸。在两种情况下空气都穿过翅片流动，使得封装100能够耗散更多热量。
图11图解制造在此所描述的半导体封装100的方法的实施例。提供半导体管芯104和用于对管芯100的连接的端子118、120（图11A）。管芯104具有相对的第一主表面106和第二主表面108、垂直于主表面106、108设置的边缘110、在第一主表面106处的一个或更多个电极以及在第二主表面108处的一个或更多个电极。管芯电极在图11中不可见。
继续于该制造方法，管芯附接材料126、128（诸如焊料膏）被施加到管芯104的（多个）对应电极上的第一主表面106（图11B）。然后旋转管芯104，从而管芯104的第一主表面106面对要被连接到第一主表面106的每个端子118（图11C）。在焊料膏的情况下，例如通过使管芯附接材料126、128回流，从而面对管芯104的第一主表面106的每个端子118经由施加到第一主表面106的管芯附接材料126、128附接到对应电极（图11C）。管芯附接材料130（诸如焊料膏）被施加到管芯104的（多个）对应电极上的第二主表面108（图11D），并且管芯104与先前所附接的（多个）端子118旋转，从而管芯104的第二主表面108面对要被连接到第二主表面108的每个端子120（图11E）。在焊料膏的情况下，例如通过使管芯附接材料108回流，从而面对管芯104的第二主表面108的每个端子120然后经由施加到第二主表面108的管芯附接材料130附接到对应电极（图11E）。该制造方法可以进一步包括：利用模制化合物132来包围半导体管芯104和端子118、120的至少一部分，从而端子118、120中的每一个具有平行于并且背对半导体管芯104的侧面134，该侧面134保持为至少部分未由模制化合物132覆盖。该制造方法可以进一步包括：从模制化合物132形成突起136，该突起136被设置在端子118、120之间，并且在半导体封装100的同一侧面处比端子118、120向外延伸得更远。
图12图解制造在此所描述的半导体封装100的方法的另一实施例。提供半导体管芯104和用于对管芯104的连接的端子118、120（图12A）。管芯104具有相对的第一主表面106和第二主表面108、垂直于主表面106、108设置的边缘110、在第一主表面106处的一个或更多个电极112、114以及在第二主表面108处的一个或更多个电极。管芯电极在图12中不可见。
继续于该制造方法，管芯附接材料126、128、130（诸如焊料膏）被施加到管芯104的电极上的两个主表面106、108（图12B）。在两个表面106、108上具有管芯附接材料1126、128、130的半导体管芯104然后插入到端子118、120之间的间隙，如图12B中的面向下箭头所指示的那样。在管芯104的第一主表面106处的（多个）电极经由施加到第一主表面的管芯附接材料126、128附接到邻近第一主表面106的（多个）对应端子118，并且在管芯104的第二主表面108处的（多个）电极经由施加到第二主表面108的管芯附接材料130附接到邻近第二主表面108的（多个）对应端子120（图12C）。该制造方法可以进一步包括：利用模制化合物132来包围半导体管芯104和端子118、120的至少一部分，从而端子118、120中的每一个具有平行于并且背对管芯104的侧面134，该侧面134保持为至少部分未由模制化合物132覆盖。该制造方法可以进一步包括：从模制化合物132形成突起136，该突起136被设置在端子118、120之间，并且在半导体封装100的同一侧面处比端子118、120向外延伸得更远。
为了便于描述而使用了与空间有关的术语（诸如‌‌“在……之下‌‌”、‌‌“以下‌‌”、‌‌“下部‌‌”、‌‌“在……上‌‌方”和‌‌“上部‌‌”等）以解释一个元件相对于第二元件的定位。这些术语意图涵盖器件的除了与图中所描绘的那些不同的定向之外的不同定向。进一步地，诸如‌‌“第一‌‌”和“第二‌‌”等的术语也用于描述各个元件、区域、部分等，并且也并非意图进行限制。同样的术语贯穿于描述指代同样的元件。
如在此使用的那样，术语‌‌“具有‌‌”‌、‌‌“‌包含‌‌”、‌‌“包括‌‌‌”和“‌含有‌‌”等是指示所声明的要素或特征的存在性的开放式术语，而非排除附加的要素或特征。数量词‌‌“‌一个‌‌”、‌‌“‌某个‌‌”以及代词‌‌“‌这个‌‌”意图包括复数以及单数，除非上下文另外地清楚指示。
应谨记在上面的变形和应用的范围的情况下，应当理解本发明既不由前面的描述限制，也不由随附的附图限制。替代地，本发明仅由下面的权利要求及其法律等同物来限制。

Claims (33)

1. 一种半导体封装，包括：
半导体管芯,具有相对的第一主表面和第二主表面、与所述第一主表面和所述第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极；
第一端子，附接到所述第一电极；
第二端子，附接到所述第二电极；
模制化合物，包围所述半导体管芯以及所述第一端子和所述第二端子的至少一部分，从而所述第一端子和所述第二端子中的每一个具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖；以及
突起，从所述模制化合物形成，或者从所述模制化合物突出出来，所述突起被设置在所述第一端子与所述第二端子之间，并且在所述半导体封装的同一侧面处比所述第一端子和所述第二端子向外延伸得更远。
2. 如权利要求1所述的半导体封装，其中，所述突起包括所述半导体管芯的一部分，从而所述半导体管芯在所述半导体封装的同一侧面处比所述第一端子和所述第二端子向外延伸得更远。
3. 如权利要求1所述的半导体封装，其中，所述半导体管芯是功率晶体管管芯，所述第一电极是所述功率晶体管管芯的源极电极，所述第二电极是所述功率晶体管管芯的漏极电极，并且所述功率晶体管管芯进一步在管芯的与所述源极电极或所述漏极电极相同的表面处具有栅极电极，所述半导体封装进一步包括：
第三端子，附接到所述栅极电极，
其中，所述模制化合物包围所述第三端子的至少一部分，从而所述第三端子具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖，并且所述突起在所述半导体封装的与所述第一端子和所述第二端子相同的侧面处比所述第三端子向外延伸得更远。
4. 如权利要求1所述的半导体封装，其中，所述半导体管芯被包围在由所述模制化合物和端子形成的空气腔内。
5. 如权利要求1所述的半导体封装，进一步包括：致冷结构，被图案化到所述第一端子和所述第二端子中的至少一个的至少部分未被覆盖的侧面，以用于增加该侧面的表面面积。
6. 如权利要求1所述的半导体封装，其中，所述第一端子和所述第二端子中的每一个具有在相应端子的至少部分未被覆盖的侧面的端部处所设置的一个或更多个接触焊盘。
7. 如权利要求1所述的半导体封装，其中，所述第一端子和所述第二端子在每个端子的整个长度上具有均匀的横截面面积。
8. 如权利要求1所述的半导体封装，其中，所述半导体管芯的边缘在所述第一端子和所述第二端子的一个端部处与端子齐平。
9. 如权利要求1所述的半导体封装，其中，所述第一端子和所述第二端子的每一个具有被所述模制化合物覆盖的第一端部以及至少部分未被所述模制化合物覆盖的相对的第二端部。
10. 如权利要求1所述的半导体封装，其中，所述第一端子和所述第二端子的每一个具有带有凹槽的第一端部以及带有凹槽的相对的第二端部，并且其中，所述模制化合物填充在端子的所述第一端部处的凹槽和在端子的所述第二端部处的凹槽。
11. 一种半导体封装，包括：
半导体管芯,具有相对的第一主表面和第二主表面、与所述第一主表面和所述第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极；
第一端子，附接到所述第一电极；
第二端子，附接到所述第二电极；
模制化合物，包围所述半导体管芯以及所述第一端子和所述第二端子的至少一部分，从而所述第一端子和所述第二端子中的每一个具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖；以及
致冷结构，被图案化到所述第一端子和所述第二端子中的至少一个的至少部分未被覆盖的侧面，以用于增加该侧面的表面面积。
12. 如权利要求11所述的半导体封装，其中，所述致冷结构包括被图案化到所述第一端子和所述第二端子中的至少一个的至少部分未被覆盖的侧面的翅片型结构。
13. 如权利要求12所述的半导体封装，其中，所述翅片型结构沿着具有所述致冷结构的至少部分未被覆盖的侧面的宽度延伸。
14. 如权利要求11所述的半导体封装，进一步包括：突起，从所述模制化合物形成，或者从所述模制化合物突出出来，所述突起被设置在所述第一端子与所述第二端子之间，并且在所述半导体封装的同一侧面处比所述第一端子和所述第二端子向外延伸得更远。
15. 一种半导体组装，包括：
衬底，具有导电区域；以及
半导体封装，包括：
　　半导体管芯,具有相对的第一主表面和第二主表面、与所述第一主表面和所述第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极；
　　第一端子，附接到所述第一电极；
　　第二端子，附接到所述第二电极；以及
　　模制化合物，包围所述半导体管芯以及所述第一端子和所述第二端子的至少一部分，从而所述第一端子和所述第二端子中的每一个具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖，
其中，所述半导体封装的所述第一端子和所述第二端子连接到所述衬底的所述导电区域中的不同区域。
16. 如权利要求15所述的半导体组装，其中，所述半导体封装进一步包括：突起，从所述模制化合物形成，或者从所述模制化合物突出出来，所述突起被设置在所述第一端子与所述第二端子之间，并且比所述第一端子和所述第二端子朝向所述衬底向外延伸得更远，其中，所述突起由所述衬底中的凹槽容纳。
17. 如权利要求16所述的半导体组装，其中，所述半导体封装的所述第一端子和所述第二端子在每个端子的整个长度上具有均匀的横截面面积，其中，所述衬底的连接到所述第一端子和所述第二端子的所述导电区域设置在所述衬底的表面上，并且其中，每个端子的至少部分未被覆盖的侧面抵靠与所述衬底的表面垂直的对应的导电区域的侧面而被按压。
18. 如权利要求16所述的半导体组装，其中，所述突起包括所述半导体管芯的一部分，从而所述半导体管芯比所述第一端子和所述第二端子向外延伸得更远，并且由所述衬底中的凹槽容纳。
19. 如权利要求15所述的半导体组装，其中，所述半导体管芯是功率晶体管管芯，所述第一电极是所述功率晶体管管芯的源极电极，所述第二电极是所述功率晶体管管芯的漏极电极，并且所述功率晶体管管芯进一步在管芯的与所述源极电极或所述漏极电极相同的表面处具有栅极电极，所述半导体封装进一步包括：
第三端子，附接到所述栅极电极，并且连接到所述衬底的所述导电区域之一，
其中，所述模制化合物包围所述第三端子的至少一部分，从而所述第三端子具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖，并且突起比所述第三端子朝向所述衬底向外延伸得更远。
20. 如权利要求15所述的半导体组装，其中，所述半导体管芯被包围在由所述模制化合物和端子形成的空气腔内。
21. 如权利要求15所述的半导体组装，其中，所述第一端子和所述第二端子中的每一个具有在相应端子的至少部分未被覆盖的侧面的端部处所设置的一个或更多个接触焊盘，其中，所述衬底的连接到所述第一端子和所述第二端子的所述导电区域的每一个包括具有接触焊盘的插槽，并且其中，端子中的每一个插入在对应的插槽中，从而端子的每个接触焊盘接触插槽的接触焊盘中的一个。
22. 如权利要求15所述的半导体组装，其中，所述半导体管芯的边缘在所述第一端子和所述第二端子的邻近所述衬底的端部处与端子齐平。
23. 如权利要求15所述的半导体组装，其中，所述第一端子和所述第二端子的每一个具有由所述模制化合物覆盖的第一端部和至少部分未被所述模制化合物覆盖的相对的第二端部，端子的所述第一端部背对所述衬底，并且端子的所述第二端部面对所述衬底。
24. 如权利要求15所述的半导体组装，其中，所述第一端子和所述第二端子的每一个具有带有凹槽的第一端部以及带有凹槽的相对的第二端部，并且其中，所述模制化合物填充在端子的所述第一端部处的凹槽和在端子的所述第二端部处的凹槽。
25. 如权利要求15所述的半导体组装，进一步包括：致冷结构，被图案化到所述第一端子和所述第二端子中的至少一个的至少部分未被覆盖的侧面，以用于增加该侧面的表面面积。
26. 如权利要求25所述的半导体组装，其中，所述致冷结构包括被图案化到所述第一端子和所述第二端子中的至少一个的至少部分未被覆盖的侧面的翅片型结构。
27. 如权利要求26所述的半导体组装，其中，所述翅片型结构沿着具有所述致冷结构的至少部分未被覆盖的侧面的宽度延伸。
28. 一种制造半导体封装的方法，所述方法包括：
将管芯附接材料施加到半导体管芯的第一主表面，所述半导体管芯还具有相对的第二主表面、与所述第一主表面和所述第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极；
旋转所述半导体管芯，从而所述半导体管芯的所述第一主表面面对第一端子；
经由施加到所述第一主表面的管芯附接材料将所述第一电极附接到所述第一端子；
将管芯附接材料施加到所述半导体管芯的所述第二主表面；
旋转带有所附接的所述第一端子的所述半导体管芯，从而所述半导体管芯的所述第二主表面面对第二端子；以及
经由施加到所述第二主表面的管芯附接材料将所述第二电极附接到所述第二端子。
29. 如权利要求28所述的方法，进一步包括：利用模制化合物包围所述半导体管芯以及所述第一端子和所述第二端子的至少一部分，从而所述第一端子和所述第二端子中的每一个具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖。
30. 如权利要求29所述的方法，进一步包括：从所述模制化合物形成突起，所述突起被设置在所述第一端子和所述第二端子之间，并且在所述半导体封装的同一侧面处比所述第一端子和所述第二端子向外延伸得更远。
31. 一种制造半导体封装的方法，所述方法包括：
将管芯附接材料施加到半导体管芯的第一主表面和所述半导体管芯的相对的第二主表面，所述半导体管芯进一步具有：与所述第一主表面和所述第二主表面垂直设置的边缘、在所述第一主表面处的第一电极以及在所述第二主表面处的第二电极；
将带有管芯附接材料的所述半导体管芯插入到第一端子与第二端子之间的间隙中；以及
在所述半导体管芯插入到所述第一端子和所述第二端子之间的间隙中之后，经由施加到所述第一主表面的管芯附接材料将所述第一电极附接到所述第一端子，并且经由施加到所述第二主表面的管芯附接材料将所述第二电极附接到所述第二端子。
32. 如权利要求31所述的方法，进一步包括：利用模制化合物包围所述半导体管芯以及所述第一端子和所述第二端子的至少一部分，从而所述第一端子和所述第二端子中的每一个具有平行于并且背对所述半导体管芯的侧面，该侧面保持为至少部分未被所述模制化合物覆盖。
33. 如权利要求32所述的方法，进一步包括：从所述模制化合物形成突起，所述突起被设置在所述第一端子和所述第二端子之间，并且在所述半导体封装的同一侧面处比所述第一端子和所述第二端子向外延伸得更远。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110785838A (zh) * 2017-05-02 2020-02-11 Abb瑞士股份有限公司 具有暴露的端子区域的树脂封装功率半导体模块

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10651201B2 (en) * 2017-04-05 2020-05-12 Samsung Electronics Co., Ltd. Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration
JP7183594B2 (ja) * 2018-07-04 2022-12-06 富士電機株式会社 半導体装置
DE102020102653A1 (de) * 2020-02-03 2021-08-19 Infineon Technologies Ag Halbleitervorrichtung mit einem Erweiterungselement zur Luftkühlung
EP3971957A1 (en) * 2020-09-16 2022-03-23 Infineon Technologies Austria AG Semiconductor package, semiconductor module and methods for manufacturing a semiconductor module
EP4310907A1 (en) * 2022-07-22 2024-01-24 Infineon Technologies Austria AG Semiconductor package and method for fabricating a semiconductor package for upright mounting

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020100963A1 (en) * 2001-01-26 2002-08-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor package and semiconductor device
US20040159927A1 (en) * 2002-11-15 2004-08-19 Stmicroelectronics Asia Pacific Pte Ltd Semiconductor device package and method of manufacture
CN1531084A (zh) * 2003-01-29 2004-09-22 �����ɷ� 具有整合于壳体并由共享接触夹完成接触之至少两芯片之半导体组件
US20060270108A1 (en) * 2003-03-31 2006-11-30 Farnworth Warren M Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts
US20070045872A1 (en) * 2005-08-31 2007-03-01 Fee Setho S Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
CN101064485A (zh) * 2006-04-27 2007-10-31 株式会社日立制作所 电路装置、电路模块和电力变换装置
CN102299117A (zh) * 2010-06-23 2011-12-28 株式会社电装 具有冷却机制的半导体模块及其生产方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
JP4138689B2 (ja) * 2004-03-30 2008-08-27 株式会社東芝 インターフェイスモジュール付ｌｓｉパッケージ及びｌｓｉパッケージ
US7168842B2 (en) * 2004-12-01 2007-01-30 Au Optronics Corporation Light emitting diode backlight package
US7397120B2 (en) 2005-12-20 2008-07-08 Semiconductor Components Industries, L.L.C. Semiconductor package structure for vertical mount and method
WO2007145237A1 (ja) * 2006-06-14 2007-12-21 Panasonic Corporation 放熱配線基板とその製造方法
US7973394B2 (en) * 2009-06-10 2011-07-05 Blondwich Limited Enhanced integrated circuit package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020100963A1 (en) * 2001-01-26 2002-08-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor package and semiconductor device
US20040159927A1 (en) * 2002-11-15 2004-08-19 Stmicroelectronics Asia Pacific Pte Ltd Semiconductor device package and method of manufacture
CN1531084A (zh) * 2003-01-29 2004-09-22 �����ɷ� 具有整合于壳体并由共享接触夹完成接触之至少两芯片之半导体组件
US20060270108A1 (en) * 2003-03-31 2006-11-30 Farnworth Warren M Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts
US20070045872A1 (en) * 2005-08-31 2007-03-01 Fee Setho S Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
CN101064485A (zh) * 2006-04-27 2007-10-31 株式会社日立制作所 电路装置、电路模块和电力变换装置
CN102299117A (zh) * 2010-06-23 2011-12-28 株式会社电装 具有冷却机制的半导体模块及其生产方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110785838A (zh) * 2017-05-02 2020-02-11 Abb瑞士股份有限公司 具有暴露的端子区域的树脂封装功率半导体模块
CN110785838B (zh) * 2017-05-02 2023-10-24 日立能源瑞士股份公司 具有暴露的端子区域的树脂封装功率半导体模块

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