CN104201100A - 小尺寸图形的制作方法 - Google Patents

小尺寸图形的制作方法 Download PDF

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CN104201100A
CN104201100A CN201410491169.1A CN201410491169A CN104201100A CN 104201100 A CN104201100 A CN 104201100A CN 201410491169 A CN201410491169 A CN 201410491169A CN 104201100 A CN104201100 A CN 104201100A
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silicon nitride
polysilicon
linear array
small size
manufacture method
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崇二敏
李全波
孟祥国
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Shanghai Huali Microelectronics Corp
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Abstract

本发明公开了小尺寸图形的制作方法，先在晶圆表面采用热氧化法生长一层氧化硅，接着沉积一层多晶硅，然后沉积一层氮化硅，通过后续光刻以及刻蚀工艺形成多晶硅线形阵列图形，接着应用LEC工艺对多晶硅线形阵列图形进行曝光和刻蚀，其中，所述小尺寸图形的制作方法还包括：利用干法刻蚀工艺打开所述多晶硅线性阵列图形上的硬掩膜层；利用低温原子层沉积技术沉积一层氮化硅薄膜；最后利用干法蚀刻对所述氮化硅薄膜进行回刻，进而形成小尺寸且可调控的图形结构。

Description

小尺寸图形的制作方法
技术领域
本发明涉及半导体制造，特别是涉及一种LEC工艺中的小尺寸图形的制作方法。
背景技术
随着工艺尺寸不断缩小，特别是在32纳米及其以下技术中，由于栅极宽度进一步减小，对光刻机的能力以及光刻工艺的要求越来越高。为了进一步降低器件关键尺寸，提高其集成度，业界出现各种不同的解决方案。
现有技术的一种解决方案是利用现有成熟光刻工艺形成线形阵列图形后，应用一道光刻和刻蚀工艺沿垂直线形阵列图形方向把线形阵列断开(即Line End Cut工艺，简称LEC工艺)，最终形成独立且重复的器件。
图1为现有技术的LEC工艺光刻曝光的制程方法的流程示意图。图2为LEC工艺光刻曝光后的剖面示意图。
在步骤S10中，在晶圆(Si)表面采用热氧化法生长一层氧化硅(SiO2)；
在步骤S12中，沉积一层多晶硅(Poly)；
在步骤S14中，沉积一层氮化硅(SiN)，通过后续光刻以及刻蚀工艺形成多晶硅线形阵列图形；
在步骤S16中，应用LEC工艺对多晶硅线形阵列图形进行曝光和刻蚀。更详细地说，首先，利用光刻涂布工艺涂一层旋涂碳氧化物(SOC)，使表面平坦；随后，涂一层含硅抗反射涂层(SHB，例如，Si-ARC)；最后，涂一层光刻胶(例如，ArF光刻胶)并进行曝光，形成如图2所示的HTH尺寸为55纳米的图形。
图3为采用三层(Tri-layer)技术通过干法刻蚀依次对SHB、SOC以及SiN进行刻蚀并停在Poly上的剖面示意图；图4为采用一步O2灰化工艺祛除SiN上的SOC的剖面示意图。图5为利用SiN作为阻挡层对Poly进行刻蚀，最终形成头到头(HeadTo Head，简称HTH)尺寸较小的多晶硅结构的剖面示意图。
为了提高器件集成度，通过LEC工艺断开线性阵列图形后，此处HTH尺寸需要做到35纳米，但是由于光刻受机台能力限制，现有技术中曝光后的HTH尺寸最小为55纳米，如何达到更小尺寸(例如，35纳米)的要求成为业界亟待解决的技术问题。
发明内容
本发明要解决的技术问题在于提供一种小尺寸图形的制作方法，其能够应用于32纳米及其以下技术中，以解决光刻机能力不够以及光刻和刻蚀工艺窗口不足等问题，同时缩小器件尺寸，提高半导体工艺集成度。
本发明一方面的小尺寸图形的制作方法，先在晶圆表面采用热氧化法生长一层氧化硅，接着沉积一层多晶硅，然后沉积一层氮化硅，通过后续光刻以及刻蚀工艺形成多晶硅线形阵列图形，接着应用LEC工艺对多晶硅线形阵列图形进行曝光和刻蚀，其中，所述小尺寸图形的制作方法还包括：利用干法刻蚀工艺打开所述多晶硅线性阵列图形上的硬掩膜层；利用低温原子层沉积技术沉积一层氮化硅薄膜；最后利用干法蚀刻对所述氮化硅薄膜进行回刻，进而形成小尺寸且可调控的图形结构。其中，所述多晶硅线性阵列图形上的硬掩膜层包括所述含硅抗反射涂层、所述旋涂碳氧化物、所述氮化硅，且所述采用低温原子层沉积技术沉积的氮化硅薄膜的厚度介于5纳米至15纳米之间。
较优地，所述干法刻蚀工艺进一步包括：祛除所述多晶硅线性阵列图形上的氮化硅薄膜，形成氮化硅侧墙；利用所述氮化硅作为阻挡层蚀刻所述多晶硅并停留在所述氧化硅上。其中，使用CF4、CHF3混合气体祛除所述多晶硅线性阵列图形上的氮化硅薄膜，使用CL2、SF6、CF4混合气体蚀刻所述多晶硅。
与现有技术相比，本发明基于LEC工艺中光刻曝光后的图形，利用业界比较成熟的低温原子层沉积技术以及干法刻蚀工艺，最终形成头到头之间的距离可自由调控的结构，极大地提高了光刻及刻蚀工艺窗口，从而解决32纳米及其以下技术中光刻和干刻工艺能力不足以及工艺窗口较小问题，进一步提高光刻工艺窗口，降低关键尺寸，大幅度提高器件的集成度。
以下结合附图和具体实施例对本发明的技术方案进行详细的说明，以使本发明的特性和优点更为明显。
附图说明
图1为现有技术的LEC工艺光刻曝光的制程方法的流程示意图；
图2为现有技术的LEC工艺光刻曝光后的剖面示意图；
图3至图5为现有技术的LEC工艺各个步骤中的剖面示意图；
图6所示为本发明一个实施例的小尺寸图形的制作方法的流程示意图；
图7至图9所示为本发明的小尺寸图形的制作方法各个步骤中的剖面示意图。
具体实施方式
以下将对本发明的实施例给出详细的说明。尽管本发明将结合一些具体实施方式进行阐述和说明，但需要注意的是本发明并不仅仅只局限于这些实施方式。相反，对本发明进行的修改或者等同替换，均应涵盖在本发明的权利要求范围当中。
另外，为了更好的说明本发明，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员将理解，没有这些具体细节，本发明同样可以实施。在另外一些实例中，对于大家熟知的方法、流程、元件和电路未作详细描述，以便于凸显本发明的主旨。
图6为本发明一个实施例的小尺寸图形的制作方法的流程示意图。如图所示，本实施例的小尺寸图形的制作方法包括与图1所示的现有技术的LEC工艺光刻曝光的制程方法相同的步骤，其区别在于，在图1的步骤S16之后，该小尺寸图形的制作方法还包括：
步骤S20，利用干法刻蚀工艺打开所述多晶硅线性阵列图形上的硬掩膜层。其中，所述硬掩膜层包括SiN。
步骤S22，利用低温原子层沉积(Atomic Layer Deposition，简称ALD)技术沉积一层ALD氮化硅(ALD SiN)薄膜(请同时参阅图7)。更具体地说，通过ALD技术精确控制氮化硅薄膜厚度(例如，使所述SiN薄膜的厚度介于5纳米至15纳米之间)，以此来自由调节LEC工艺刻蚀后的关键尺寸。
步骤S24，利用干法刻蚀工艺祛除多晶硅线性阵列图形上的SiN薄膜，形成SiN侧墙(请参阅图8)。在一个实施例中，使用CF4、CHF3混合气体祛除所述多晶硅线性阵列图形上的氮化硅薄膜。
步骤S26，最后利用SiN作为阻挡层蚀刻Poly并停留在SiO2上，形成小尺寸且可调控(例如，介于25纳米至45纳米之间)的图形结构(请同时参阅图9)。在一个较佳的实施例中，使用CL2、SF6、CF4混合气体蚀刻所述多晶硅，最终形成HTH小尺寸的图形结构。
上文具体实施方式和附图仅为本发明之常用实施例。显然，在不脱离权利要求书所界定的本发明精神和发明范围的前提下可以有各种增补、修改和替换。本领域技术人员应该理解，本发明在实际应用中可根据具体的环境和工作要求在不背离发明准则的前提下在形式、结构、布局、比例、材料、元素、组件及其它方面有所变化。因此，在此披露之实施例仅用于说明而非限制，本发明之范围由后附权利要求及其合法等同物界定，而不限于此前之描述。

Claims (6)

1.一种小尺寸图形的制作方法，先在晶圆表面采用热氧化法生长一层氧化硅，接着沉积一层多晶硅，然后沉积一层氮化硅，通过后续光刻以及刻蚀工艺形成多晶硅线形阵列图形，接着应用LEC工艺对多晶硅线形阵列图形进行曝光和刻蚀，其特征在于，所述小尺寸图形的制作方法还包括：
利用干法刻蚀工艺打开所述多晶硅线性阵列图形上的硬掩膜层；
利用低温原子层沉积技术沉积一层氮化硅薄膜；
最后利用干法蚀刻对所述氮化硅薄膜进行回刻，进而形成小尺寸且可调控的图形结构。
2.根据权利要求1所述的小尺寸图形的制作方法，其特征在于，所述多晶硅线性阵列图形上的硬掩膜层包括所述含硅抗反射涂层、所述旋涂碳氧化物、所述氮化硅。
3.根据权利要求1所述的小尺寸图形的制作方法，其特征在于，所述采用低温原子层沉积技术沉积的氮化硅薄膜的厚度介于5纳米至15纳米之间。
4.根据权利要求1所述的小尺寸图形的制作方法，其特征在于，所述干法刻蚀工艺进一步包括：
祛除所述多晶硅线性阵列图形上的氮化硅薄膜，形成氮化硅侧墙；
利用所述氮化硅作为阻挡层蚀刻所述多晶硅并停留在所述氧化硅上。
5.根据权利要求4所述的小尺寸图形的制作方法，其特征在于，使用CF4、CHF3混合气体祛除所述多晶硅线性阵列图形上的氮化硅薄膜。
6.根据权利要求4所述的小尺寸图形的制作方法，其特征在于，使用CL2、SF6、CF4混合气体蚀刻所述多晶硅。
CN201410491169.1A 2014-09-23 2014-09-23 小尺寸图形的制作方法 Pending CN104201100A (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120108068A1 (en) * 2010-11-03 2012-05-03 Texas Instruments Incorporated Method for Patterning Sublithographic Features
CN103474337A (zh) * 2013-09-22 2013-12-25 上海华力微电子有限公司 制作高均匀度栅极线条的方法
CN103928313A (zh) * 2014-04-22 2014-07-16 上海华力微电子有限公司 一种小尺寸图形的制作方法
CN103928304A (zh) * 2014-04-22 2014-07-16 上海华力微电子有限公司 一种多晶硅上小尺寸图形结构的制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120108068A1 (en) * 2010-11-03 2012-05-03 Texas Instruments Incorporated Method for Patterning Sublithographic Features
CN103474337A (zh) * 2013-09-22 2013-12-25 上海华力微电子有限公司 制作高均匀度栅极线条的方法
CN103928313A (zh) * 2014-04-22 2014-07-16 上海华力微电子有限公司 一种小尺寸图形的制作方法
CN103928304A (zh) * 2014-04-22 2014-07-16 上海华力微电子有限公司 一种多晶硅上小尺寸图形结构的制备方法

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