CN104157650B - A kind of N-channel field-effect transistor of anti-single particle effect and preparation method thereof - Google Patents
A kind of N-channel field-effect transistor of anti-single particle effect and preparation method thereof Download PDFInfo
- Publication number
- CN104157650B CN104157650B CN201410427196.2A CN201410427196A CN104157650B CN 104157650 B CN104157650 B CN 104157650B CN 201410427196 A CN201410427196 A CN 201410427196A CN 104157650 B CN104157650 B CN 104157650B
- Authority
- CN
- China
- Prior art keywords
- drain region
- region
- drain
- threshold voltage
- particle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses N-channel field-effect transistor of a kind of anti-single particle effect and preparation method thereof.The N-channel field-effect transistor of the anti-single particle effect includes Semiconductor substrate, epitaxial layer, source region, drain region, grid, first threshold voltage injection region is provided between source region and drain region, the periphery in the drain region is provided with second threshold voltage injection region provided with the deep doped drain of annular between deep doped drain and drain region.The present invention is in conventional N-channel field-effect transistor drain region periphery around the deep doped drain of a circle, additional deep doped drain effectively aids in drain region to collect electric charge after can producing funneling effect in the incident sensitive drain region of single-particle, so that device drain region after by single particle radiation absorbs the quantity of electric charge and soak time is reduced, reduce single-particle transient current pulse time and peak value, and transient voltage pulses of the single-particle of certain linear energy transfer value caused by chain of inverters are shielded, improve the Radiation hardness of device.
Description
Technical field
The present invention relates to integrated circuit technique, more particularly to a kind of N ditches of the anti-single particle effect with Radiation hardness
Road field-effect transistor and preparation method thereof.
Background technology
Irradiation can produce serious influence to the performance of integrated circuit, and radiation environment mainly causes accumulated dose to integrated circuit
The two kinds of influences of effect and single particle effect.With the progress of microelectronic technique, device feature size is less and less, total dose effect
Influence to integrated circuit is more and more weaker, and the influence of single particle effect is being continued to increase.
When single particle effect refers to single high energy particle penetrating electrons device sensitizing range, ionization is caused on its track simultaneously
Deposited charge, the deposited charge produced by these collected by sensitizing range, cause device or circuit logic state change or
Damage.Single particle effect is divided into hard error and the major class of soft error two.Hard error refers to that single-particle causes device permanently to damage.It is soft
Mistake refers to that single-particle causes circuit logic state to change, but device is not damaged.In soft error, most importantly simple grain
Son upset and single-ion transient state.Single-ion transient state gradually takes with the reduction of device feature size and the increase of clock frequency
Turn into the main source of soft error caused by single-particle for single-particle inversion.
It can be divided into device level reinforcing for the reinforcement means of single-ion transient state and circuit-level reinforces two kinds, during circuit-level is reinforced
Most commonly three times redundant circuit reinforcement means, but need to sacrifice substantial amounts of circuit area using this method, while can also increase
Plus circuit response time.And only need to sacrifice minimum area just can obtain good anti-radiation performance income for device level reinforcing, together
When will not also to circuit performance produce considerable influence.
The content of the invention
In order to solve the above-mentioned technical problem, the present invention provide a kind of anti-single particle effect N-channel field-effect transistor and
Preparation method.
In order to solve the above technical problems, the technical scheme is that：Including Semiconductor substrate (101), epitaxial layer, source
Area, drain region, are provided with first threshold voltage injection region, the periphery in the drain region is provided with the deep doped drain of annular between source region and drain region
Area, between deep doped drain and drain region be provided with second threshold voltage injection region, between source region and first threshold voltage area, drain region with
It is all provided between first threshold voltage area, between drain region and second threshold voltage area and deep doped drain and second threshold voltage area
It is equipped with lightly-doped source drain region；Groove is set to isolate with the outside of deep doped drain in source region.
In the N-channel field-effect transistor of above-mentioned anti-single particle effect, the deep doped drain is injection arsenic, injection
Dosage is 1 × 1015cm-2, Implantation Energy is 30keV.The second threshold voltage injection region be injection boron, implantation dosage be 2 ×
1015cm-2, Implantation Energy is 3keV.
A kind of preparation method of the N-channel field-effect transistor of anti-single particle effect is as follows：
The beneficial effects of the present invention are：The present invention is deep around a circle in conventional N-channel field-effect transistor drain region periphery
Doped drain, in order to prevent deep doped drain and the voltage influence of drain region each other, sets between deep doped drain and drain region
There is second threshold voltage injection region.Additional deep doped drain has after can producing funneling effect in the incident sensitive drain region of single-particle
Collect electric charge in effect ground auxiliary drain region so that device drain region after by single particle radiation absorbs the quantity of electric charge and soak time significantly
Reduce, efficiently reduce single-particle transient current pulse time and peak value, and shield the simple grain of certain linear energy transfer value
Transient voltage pulses of the son caused by chain of inverters, improve the Radiation hardness of device or circuit.Meanwhile, because second
Voltage on the voltage block effect in threshold voltage area, deep doped drain will not have an impact to drain region.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the present invention.
Fig. 2 is the layout schematic top plan view that the present invention is applied in many devices.
Charge-trapping path schematic diagram when Fig. 3 is the incident sensitive nodes of the present invention of single-particle in the present invention.
Fig. 4 is transient current pulse comparison diagram of the present invention with conventional device after single-particle incidence produced by drain region.
Fig. 5 be the present invention with conventional device different linear energy transfer values single-particle incidence after seven grades of chain of inverters ends
Voltage Pulse Width comparison diagram produced by end.
Embodiment
Below in conjunction with the accompanying drawings and embodiment the present invention is described in detail.
As shown in figure 1, Fig. 1 is the cross-sectional view of the N-channel field-effect transistor of anti-single particle effect of the present invention.
101 attach most importance to doped substrate；Epitaxial layer 102 is grown on substrate 101；On epitaxial layer 102, drain region 110 is located at source region 111
Two ends；First threshold voltage injection region 103 is located between drain region 110 and source region 111, and it is above grid oxide layer and grid；Drain region
Electrode 108 is connected with drain region 110, and connects voltage VDD；Deep doped drain 105 is located on epitaxial layer 102, the right side of drain region 110；
It is second threshold voltage injection region 104 between deep doped drain 105 and drain region 110；Deep doped drain electrode 106 and deep doped drain
Area 105 is connected, and connects voltage VDD；Between source region 111 and first threshold voltage area 103, drain region 110 and first threshold voltage area
It is provided between 103, between drain region 110 and second threshold voltage area 104 and deep doped drain and second threshold voltage area 104
Lightly-doped source drain region 109；Set groove isolate 107 in source region 111 and the outside of deep doped drain 105, groove isolation can be deep trouth every
From, or shallow-trench isolation.
N-channel field-effect transistor anti-single particle ruggedized construction in figure, including the leakage that common N-channel FET possesses
Gate-source junctions structure, while addition of second threshold voltage injection region and deep doped drain, deep doped drain all the time with VDDIt is connected.Institute
The setting for stating second threshold voltage injection region is that the deep doped drain of blocking is in access V in order to be spaced drain region and deep doped drainDDAfterwards
Produced electric field because between drain region and deep doped drain raceway groove it is too short and to the influence produced by drain region.Second threshold voltage is noted
The technique for entering area is identical with first threshold voltage injection region, and institute is compatible with standard CMOS process, can prepare the first threshold
Second threshold voltage injection region is prepared while threshold voltage injection region to shorten the production cycle.The depth of the deep doped drain is
1~3 times of drain region, its plan view shape are as shown in Fig. 2 be provided around drain region formula.Its circular mode is I-shaped, or
The shape of a hoof, rail shape etc..Both the above is for increasing deep doped drain on the setting of deep doped drain to be entered in single-particle
Penetrate behind sensitive drain region and absorb the area of electric charge, to strengthen the ability that it aids in drain region to collect electric charge.
When in single-particle incidence device, its energy will lose, and the energy of loss will cause the direct electricity of device material
From, the electronics that direct ionization is produced still has sizable energy with hole, can continue to cause the double ionization of device material,
Therefore, a large amount of electron hole pairs will be produced at the incident track of single-particle.When electric field is not present in device, produced electronics
Hole is not impacted to that will be combined automatically to device.But when there is electric field, produced electrons will be by device
Collected by part sensitive electrode, transient current is produced, so as to influence device to work, soft error is produced.In N-channel field-effect transistor
In, reverse-biased leakage/body knot is sensitive nodes, and the highfield of its depletion region will collect single-particle incidence by way of charge shift
The electronics produced afterwards.
201 be source region；The right side of source region 201 is drain region 203；It is drain region electrode 202 on drain region；The right side of drain region 203 is deep
Doped drain 204, can be " work " font, or the shape of a hoof, annular, rail shape etc.；205 be deep doped drain electrode,
It is connected with deep doped drain 204.
As shown in figure 3, charge-trapping road strength schematic diagram when Fig. 3 is single-particle incidence sensitive nodes of the present invention.Single-particle enters
A large amount of electron hole pairs will be produced by penetrating after drain region of the invention sensitive, and for N-channel field-effect transistor, sensitive nodes will be received
Set electron, and hole will diffuse to epitaxial region, and finally dissipated naturally to substrate.Electronics in the present invention will produce two kinds
Path, first path is to pass through charge shift to drain region under the forceful electric power field action of depletion region below drain region；Second path be
Pass through charge shift to deep doped drain under the influence of the electric field of deep doped drain.Because the absorption area of deep doped drain is big, inhale
Receive path short, absorption efficiency is high, and the electronics largely produced as single particle effect is collected by deep doped drain, so as to effectively subtract
Therefore the small quantity of electric charge collected by drain region, produced Peak of current pulse and duration also reduce, as shown in Figure 4.When
When applying the present invention in seven grades of chain of inverters, Voltage Pulse Width after single-particle is incident produced by chain of inverters terminal
It will be greatly reduced, voltage pulse that particularly can be produced by the single-particle of the low linear energy transfer value of masked segment, such as Fig. 5 institutes
Show.
N-channel field-effect transistor proposed by the present invention for anti-single particle effect, its implementation and conventional N-Channel
Field-effect transistor is roughly the same, and the increased second threshold voltage injection region 104 of institute can be with conventional cmos manufacturing process and with the
One threshold voltage injection region 103 is prepared simultaneously.The preparation of deep doped drain 105 can not simultaneously be prepared with source-drain area, it is necessary to individually
Prepare.Following examples be will be explained in, but following examples are only explanations, and the present invention is simultaneously not limited by the following examples.
1) p-type dope semiconductor substrates are selected, boron doping, concentration is 1 × 1018cm-3；
2) p-type epitaxial layer is made, boron doping, concentration is 1 × 1016cm-3；
3) grid oxic horizon is made, temperature is 700 DEG C, and thickness is 1.07nm；
4) gate polysilicon layer is made, temperature is 535 DEG C, and thickness is 62.93nm；
5) lightly-doped source drain region is made, lightly-doped source drain region region, arsenic doping is made by lithography, implantation dosage is 1.15 ×
1013cm-2, Implantation Energy is 12keV；
6) source-drain area is made, source and drain region, arsenic doping is made by lithography, implantation dosage is 1.15 × 1013cm-2, Implantation Energy
For 18keV, without annealing；
7) deep doped drain is made, deep doped drain region is made by lithography, arsenic is injected, implantation dosage is 1 × 1015cm-2, note
Enter energy for 30keV；
8) make annealing treatment, 600 DEG C of process annealings 1 hour, 1000 DEG C of short annealings 10 seconds；
9) the first second threshold voltage injection region is made, the first second threshold voltage region is made by lithography, boron is injected in injection,
Implantation dosage is 2 × 1015cm-2, Implantation Energy is 3keV；
10) cmos device and circuit are completed using standard CMOS process.
Above example the 6) with the 7) step order can exchange, have no special difference.Remaining ins and outs can be used
Standard CMOS process is performed, and those of ordinary skill can implement according to description of the invention, therefore no longer to more specific skill of the invention
Art details is repeated.
Specific embodiment described above, it is intended to the present invention is further described, help further understands the present invention, at this
Within the spirit and principle of invention, various substitutions and modifications should be included in the scope of the protection.
Claims (2)
1. a kind of preparation method of the N-channel field-effect transistor of anti-single particle effect, comprises the following steps：
From p-type dope semiconductor substrates, boron doping, concentration is 1 × 1018cm-3；
P-type epitaxial layer is made, boron doping, concentration is 1 × 1016cm-3；
Grid oxic horizon is made, temperature is 700 DEG C, and thickness is 1.07nm；
Gate polysilicon layer is made, temperature is 535 DEG C, and thickness is 62.93nm；
Lightly-doped source drain region is made, lightly-doped source drain region region, arsenic doping is made by lithography, implantation dosage is 1.15 × 1013cm-2, note
Enter energy for 12keV；
Source-drain area is made, source and drain region, arsenic doping is made by lithography, implantation dosage is 1.15 × 1013cm-2, Implantation Energy is
18keV, without annealing；
Deep doped drain is made, deep doped drain region is made by lithography, arsenic is injected, implantation dosage is 1 × 1015cm-2, Implantation Energy is
30keV；
Annealing, 600 DEG C of process annealings 1 hour, 1000 DEG C of short annealings 10 seconds；
The first and second threshold voltage injection regions are made, the first and second threshold voltage regions, injection injection boron, note are made by lithography
It is 2 × 10 to enter dosage15cm-2, Implantation Energy is 3keV；
Cmos device and circuit are completed using standard CMOS process.
2. the preparation method of the N-channel field-effect transistor of anti-single particle effect as claimed in claim 1：The Second Threshold
Voltage injection region is identical with the ionic type, energy and dosage of first threshold voltage injection region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410427196.2A CN104157650B (en) | 2014-08-27 | 2014-08-27 | A kind of N-channel field-effect transistor of anti-single particle effect and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410427196.2A CN104157650B (en) | 2014-08-27 | 2014-08-27 | A kind of N-channel field-effect transistor of anti-single particle effect and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104157650A CN104157650A (en) | 2014-11-19 |
| CN104157650B true CN104157650B (en) | 2017-09-26 |
Family
ID=51883112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410427196.2A Active CN104157650B (en) | 2014-08-27 | 2014-08-27 | A kind of N-channel field-effect transistor of anti-single particle effect and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104157650B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106876383B (en) * | 2017-01-03 | 2019-08-09 | 中国人民解放军国防科学技术大学 | It is a kind of for bombardment single-ion transient state reinforcement means of the NMOS transistor without area overhead |
| US10930646B2 (en) * | 2017-06-15 | 2021-02-23 | Zero-Error Systems Pte Ltd | Circuit and method of forming the same |
| CN109212398A (en) * | 2017-07-01 | 2019-01-15 | 微龛（北京）半导体科技有限公司 | A kind of method of parasitical bipolar transistor effect amplification coefficient caused by measurement single particle effect |
| EP4044214A4 (en) * | 2019-11-12 | 2022-11-02 | Huawei Technologies Co., Ltd. | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101950747A (en) * | 2010-09-14 | 2011-01-19 | 电子科技大学 | High-radiation-resistance CMOS semiconductor integrated circuit and preparation method thereof |
| CN102969316A (en) * | 2012-11-20 | 2013-03-13 | 电子科技大学 | Single-particle radiation resistant MOSFET device and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101326640A (en) * | 2005-10-12 | 2008-12-17 | 斯平内克半导体股份有限公司 | CMOS device with zero soft error rate |
-
2014
- 2014-08-27 CN CN201410427196.2A patent/CN104157650B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101950747A (en) * | 2010-09-14 | 2011-01-19 | 电子科技大学 | High-radiation-resistance CMOS semiconductor integrated circuit and preparation method thereof |
| CN102969316A (en) * | 2012-11-20 | 2013-03-13 | 电子科技大学 | Single-particle radiation resistant MOSFET device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104157650A (en) | 2014-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10615260B1 (en) | Method for forming FinFET device structure | |
| US8278719B2 (en) | Radiation hardened isolation structures and fabrication methods | |
| US8497195B2 (en) | Method for radiation hardening a semiconductor device | |
| CN104157650B (en) | A kind of N-channel field-effect transistor of anti-single particle effect and preparation method thereof | |
| DE112013002031T5 (en) | Semiconductor device and semiconductor device manufacturing method | |
| CN104078509A (en) | Power MOS device with single-particle burnout resistance | |
| CN106920843A (en) | Electrostatic discharge protection circuit and its silicon controlled rectifier (SCR) | |
| CN101924131A (en) | Transverse-diffusion MOS (Metal Oxide Semiconductor) device and manufacturing method thereof | |
| JP5651232B2 (en) | Manufacturing method of semiconductor device | |
| CN102969316A (en) | Single-particle radiation resistant MOSFET device and preparation method thereof | |
| CN205376532U (en) | Electrostatic protection circuit and gthyristor thereof | |
| CN114883381A (en) | Silicon controlled electrostatic protection device and manufacturing method thereof | |
| CN102104045B (en) | P-type one time programmable (OTP) device and manufacturing method thereof | |
| CN109087866A (en) | The n-MOSFET preparation method of boron injection composite double layer extension before a kind of extension | |
| CN109119458B (en) | Isolation structure and process method | |
| US8877594B2 (en) | CMOS device for reducing radiation-induced charge collection and method for fabricating the same | |
| JP2933796B2 (en) | Method for manufacturing semiconductor device | |
| CN103050510B (en) | ESD (electronic static discharge) device in RFLDMOS (ratio frequency laterally diffused metal oxide semiconductor) process and manufacture method of ESD device | |
| JP2001035933A (en) | Semiconductor device and fabrication thereof | |
| CN103035637B (en) | ESD device in RFLDMOS technique and manufacture method | |
| CN101877329B (en) | OTP (One Time Programming) device and manufacture method | |
| CN107919280B (en) | Integrated manufacturing method of different-voltage device | |
| CN105448708A (en) | Post-processing method of polycrystalline silicon gate, polycrystalline silicon gate and static random access memory | |
| Chiranu et al. | LDD structure influence on n-MOSFET parameters | |
| CN103972233A (en) | SCR (Semiconductor Control Rectifier) shut-off device with latching resistant capability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |