CN104157559A - Manufacture method of control gate and manufacture method of floating gate - Google Patents
Manufacture method of control gate and manufacture method of floating gate Download PDFInfo
- Publication number
- CN104157559A CN104157559A CN201310178630.3A CN201310178630A CN104157559A CN 104157559 A CN104157559 A CN 104157559A CN 201310178630 A CN201310178630 A CN 201310178630A CN 104157559 A CN104157559 A CN 104157559A
- Authority
- CN
- China
- Prior art keywords
- layer
- manufacture method
- gate
- control gate
- floating boom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007667 floating Methods 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 93
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000011241 protective layer Substances 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000007781 pre-processing Methods 0.000 abstract 2
- 230000015654 memory Effects 0.000 description 21
- 238000005516 engineering process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention brings forward a manufacture method of a control gate. After the control gate is formed and before a floating gate layer is etched, preprocessing is performed on the control gate firstly, and then a dielectric layer, the floating gate layer and the gate medium layer are etched. Since the preprocessing is performed on the control gate, a protective layer is formed on the surface of the control gate for protecting the control gate so as to prevent damage caused to the surface of the control gate by etching, and the yield rate of a semiconductor wafer is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the manufacture method of a kind of control gate and floating boom.
Background technology
Memory is for storing a large amount of digital information.Exist at present many eurypalynous memories, as RAM (random asccess memory), DRAM (dynamic random access memory), ROM (read-only memory), EPROM (Erasable Programmable Read Only Memory EPROM), FLASH (flash memory) etc.
Since first flash memory products appearance 1980s, along with development and the demand of each electronic product to storage of technology, flash memory is widely used in mobile phone, notebook, in the movements such as palmtop PC and u dish and communication apparatus, flash memory is a kind of non-volatility memory, its operation principles be the critical voltage by changing transistor or memory cell control gate pole passage switch to reach the object of storage data, the data that make to be stored in memory can not disappear because of power interruptions, flash memory is a kind of special construction of electric erasable and programmable read-only memory.
Current flash memory is divided into folded grid (stacking gate) formula flash memory and splitting bar (separate gate) formula flash memory according to the difference of memory cell device structure wherein, and the manufacture craft of flash memory comprises the making of control gate and the making of floating boom.General technology before this after etching formation control grid again etching form floating boom.
Please refer to Fig. 1 a to Fig. 1 c, in prior art, the manufacture method of control gate and floating boom generally includes: Semiconductor substrate 10 is provided; In described Semiconductor substrate 10, form successively gate dielectric layer 11, floating gate layer 20, dielectric layer 30, control grid layer 40 and mask layer 50, as shown in Figure 1a; Then described mask layer 50 and control grid layer 40 are carried out to etching, formation control grid 41, etching stopping is in the surface of described dielectric layer 30, as described in Fig. 1 b; Then dielectric layer 30, floating gate layer 20 and gate dielectric layer 11 described in etching, form floating boom 21, and etching stopping, in the surface of described Semiconductor substrate 10, please refer to Fig. 1 c.
But, along with semicon industry characteristic size continue reduce, making in the technique of control gate of flash memory, the yield on flash memory is produced impact greatly by the pattern of control gate and size.Because described floating gate layer 20 and the material of described control grid layer 40 are all polysilicon, therefore when floating gate layer described in etching 20 forms floating boom 21, also can carry out etching to the sidewall of described control gate 41, cause the damage of described control gate 41 sidewalls, make the size of described control gate 41 less than the size of technological requirement, cause the surface topography of described control gate 41 not meet the requirement of technique, affect the line resistance size of described control gate 41, also can cause the follow-up connecting line being formed on described control gate 41 to form good contacting with control gate 41, thereby can reduce the yield of semiconductor crystal wafer.
Summary of the invention
The object of the present invention is to provide the manufacture method of a kind of control gate and floating boom, can protect the control gate damage that is not etched.
To achieve these goals, the present invention proposes the manufacture method of a kind of control gate and floating boom, comprises step:
Semiconductor substrate is provided;
In described Semiconductor substrate, form successively gate dielectric layer, floating gate layer, dielectric layer, control grid layer and mask layer;
Control grid layer formation control grid described in etching;
Described control gate is carried out to preliminary treatment, form protective layer;
Dielectric layer, floating gate layer and gate dielectric layer described in etching successively, forms floating boom.
Further, the material of described floating gate layer and control grid layer is polysilicon.
Further, described preliminary treatment is plasma bombardment processing.
Further, the gas that described plasma adopts is CH
4.
Further, described plasma bombardment processing time scope is 30s～240s, and pressure range is 2mT～200mT, CH
4range of flow is 10sccm～100sccm.
Further, the gas that described plasma adopts is SiCl
4with O
2.
Further, described plasma bombardment processing time scope is 30s～240s, and pressure range is 2mT～200mT, SiCl
4range of flow is 10sccm～100sccm, O
2range of flow is 10sccm～100sccm.
Further, the gas that described plasma adopts is N
2.
Further, described plasma bombardment processing time scope is 30s～240s, and pressure range is 2mT～200mT, N
2range of flow is 10sccm～100sccm.
Further, the material of described dielectric layer is silicon oxide layer-silicon nitride-silicon oxide layer combination.
Further, the material of described mask layer is silicon nitride or silica.
Further, after forming floating boom, adopt cleaning to remove described protective layer.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: after formation control grid, before etching floating gate layer, first described control gate is carried out to preliminary treatment, then dielectric layer, floating gate layer and gate dielectric layer described in etching; Due to described control gate has been carried out to preliminary treatment, form protective layer on control gate surface and can protect control gate, thereby avoid etching to cause damage to control gate surface, improve the yield of semiconductor crystal wafer.
Brief description of the drawings
Fig. 1 a to Fig. 1 c is the structural representation in the manufacture method process of prior art control gate and floating boom;
Fig. 2 is the flow chart of the manufacture method of control gate and floating boom in one embodiment of the invention;
Fig. 3 a to Fig. 3 d is the structural representation in the manufacture method process of control gate and floating boom in one embodiment of the invention.
Embodiment
Control gate the present invention being proposed below in conjunction with the drawings and specific embodiments and the manufacture method of floating boom are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, propose in the present embodiment the manufacture method of a kind of control gate and floating boom, comprise the steps:
S100: Semiconductor substrate 100 is provided, and described Semiconductor substrate 100 is silicon substrate;
As shown in Figure 3 a, the interior shallow trench isolation that can be provided with of Semiconductor substrate 100 is from (not shown), the material of described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc., in Semiconductor substrate 100, can also form doped region etc.
S200: form successively gate dielectric layer 110, floating gate layer 200, dielectric layer 300, control grid layer 400 and mask layer 500 in described Semiconductor substrate 100, as shown in Figure 3 a;
Wherein, the material of described floating gate layer 200 and control grid layer 400 is polysilicon, described gate dielectric layer 110 is silicon dioxide, described dielectric layer 300 can be that silicon oxide layer or silicon nitride layer are preferred, described dielectric layer 300 is silicon oxide layer-silicon nitride-silicon oxide layer (ONO) combinations, the art personnel should be understood that, dielectric layer 300 also can be for forming the insulation systems such as one deck oxide etc. on one deck nitride or one deck oxide or one deck nitride; The material of described mask layer 500 is silicon nitride or silica, described mask layer 500 is as the mask of etching, in the present embodiment, described gate dielectric layer 110, floating gate layer 200, dielectric layer 300, control grid layer 400 and mask layer 500 all adopt chemical vapour deposition (CVD) to form; Certainly, described gate dielectric layer 110 can also adopt thermal oxide growth method to form, and the gate dielectric layer 110 that adopts thermal oxide growth method to form has better compact texture.
S300: mask layer 500 and control grid layer 400 formation control grid 410 described in etching successively, as shown in Figure 3 b;
Wherein, step S300 specifically comprises: first, in described mask layer 500 surface-coated photoresist layer (not shown), then described photoresist layer is carried out to patterned process; Then, using the photoresist layer of described patterning as mask layer described in mask etching 500, and the photoresist layer of patterning and mask layer 500 are as mask etching control grid layer 400, form control gate 410 as shown in Figure 3 b;
S400: the both side surface of described control gate 410 is carried out to preliminary treatment, form protective layer 600, as shown in Figure 3 c;
Wherein, described preliminary treatment is plasma bombardment processing, and the gas that described plasma can adopt is CH
4, SiCl
4with O
2mixture or N
2;
If adopt CH
4, its range of flow is 10sccm～100sccm, for example, be 50sccm, and pressure range is 2mT～200mT, for example, be 100mT, and plasma bombardment processing time scope is 30s～240s, for example, be 80s; Adopt CH
4can form in the both side surface of described control gate 410 protective layer 600 of c h bond;
If adopt SiCl
4with O
2mixture, SiCl
4range of flow is 10sccm～100sccm, for example, be 50sccm, O
2range of flow is 10sccm～100sccm, for example, be 50sccm, and pressure range is 2mT～200mT, for example, be 100mT, and plasma bombardment processing time scope is 30s～240s, for example, be 80s; Adopt SiCl
4with O
2mixture can form in the both side surface of described control gate 410 protective layer 600 of silicon dioxide;
If adopt N
2, its range of flow is 10sccm～100sccm, for example, be 50sccm, and pressure range is 2mT～200mT, for example, be 100mT, and plasma bombardment processing time scope is 30s～240s, for example, be 80s; Adopt N
2can form in the both side surface of described control gate 410 protective layer 600 of silicon nitride.
S500: dielectric layer 300, floating gate layer 200 and gate dielectric layer 110 described in etching successively, forms floating boom 210, as shown in Figure 3 d;
It is pointed out that after carrying out etching formation floating boom 210, can adopt cleaning to remove described protective layer 600.
To sum up, in the control gate providing in the embodiment of the present invention and the manufacture method of floating boom, due to after formation control grid, before etching floating gate layer, first described control gate is carried out to preliminary treatment, then dielectric layer, floating gate layer and gate dielectric layer described in etching; Due to described control gate has been carried out to preliminary treatment, form protective layer on control gate surface and can protect control gate, thereby avoid etching to cause damage to control gate surface, improve the yield of semiconductor crystal wafer.
Above are only the preferred embodiments of the present invention, the present invention is not played to any restriction.Any person of ordinary skill in the field; not departing from the scope of technical scheme of the present invention; the technical scheme that the present invention is disclosed and technology contents make any type of variations such as replacement or amendment that are equal to; all belong to the content that does not depart from technical scheme of the present invention, within still belonging to protection scope of the present invention.
Claims (13)
1. a manufacture method for control gate and floating boom, comprises step:
Semiconductor substrate is provided;
In described Semiconductor substrate, form successively gate dielectric layer, floating gate layer, dielectric layer and control grid layer;
Control grid layer formation control grid described in etching;
Described control gate is carried out to preliminary treatment, form protective layer at the sidewall of described control gate;
Dielectric layer, floating gate layer and gate dielectric layer described in etching successively, forms floating boom.
2. the manufacture method of control gate as claimed in claim 1 and floating boom, is characterized in that, the material of described floating gate layer and control grid layer is polysilicon.
3. the manufacture method of control gate as claimed in claim 2 and floating boom, is characterized in that, described preliminary treatment is plasma bombardment processing.
4. the manufacture method of control gate as claimed in claim 3 and floating boom, is characterized in that, it is CH that described plasma bombardment is processed the gas adopting
4.
5. the manufacture method of control gate as claimed in claim 4 and floating boom, is characterized in that, described plasma bombardment processing time scope is 30s～240s, and pressure range is 2mT～200mT, CH
4range of flow is 10sccm～1000sccm.
6. the manufacture method of control gate as claimed in claim 3 and floating boom, is characterized in that, it is SiCl that described plasma bombardment is processed the gas adopting
4with O
2.
7. the manufacture method of control gate as claimed in claim 6 and floating boom, is characterized in that, described plasma bombardment processing time scope is 30s～240s, and pressure range is 2mT～200mT, SiCl
4range of flow is 10sccm～1000sccm, O
2range of flow is 10sccm～1000sccm.
8. the manufacture method of control gate as claimed in claim 3 and floating boom, is characterized in that, it is N that described plasma bombardment is processed the gas adopting
2.
9. the manufacture method of control gate as claimed in claim 8 and floating boom, is characterized in that, described plasma bombardment processing time scope is 30s～240s, and pressure range is 2mT～200mT, N
2range of flow is 10sccm～1000sccm.
10. the manufacture method of control gate as claimed in claim 1 and floating boom, is characterized in that, after described control grid layer forms, before etching control grid layer, forms mask layer on described control grid layer surface.
The manufacture method of 11. control gates as claimed in claim 10 and floating boom, is characterized in that, the material of described mask layer is silicon nitride or silica.
The manufacture method of 12. control gates as claimed in claim 1 and floating boom, is characterized in that, the material of described dielectric layer is silicon oxide layer-silicon nitride-silicon oxide layer combination.
The manufacture method of 13. control gates as claimed in claim 1 and floating boom, is characterized in that, after forming floating boom, adopts cleaning to remove described protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310178630.3A CN104157559A (en) | 2013-05-14 | 2013-05-14 | Manufacture method of control gate and manufacture method of floating gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310178630.3A CN104157559A (en) | 2013-05-14 | 2013-05-14 | Manufacture method of control gate and manufacture method of floating gate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104157559A true CN104157559A (en) | 2014-11-19 |
Family
ID=51883033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310178630.3A Pending CN104157559A (en) | 2013-05-14 | 2013-05-14 | Manufacture method of control gate and manufacture method of floating gate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104157559A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992177A (en) * | 2017-02-14 | 2017-07-28 | 上海华虹宏力半导体制造有限公司 | Prevent the technique manufacturing method in flash cell control gate cavity |
| CN110634876A (en) * | 2019-09-30 | 2019-12-31 | 上海华力集成电路制造有限公司 | Method for manufacturing flash memory device |
| CN111785723A (en) * | 2020-07-24 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split-gate memory |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050095783A1 (en) * | 2003-11-05 | 2005-05-05 | Haselden Barbara A. | Formation of a double gate structure |
| CN1614751A (en) * | 2003-11-03 | 2005-05-11 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
| CN1767173A (en) * | 2004-10-26 | 2006-05-03 | 中芯国际集成电路制造(上海)有限公司 | Novel pretreatment method for alumina atom illuvium |
| CN101083207A (en) * | 2006-03-31 | 2007-12-05 | 奇梦达股份公司 | Method and device for depositing a protective layer during an etching procedure |
| CN101211770A (en) * | 2006-12-28 | 2008-07-02 | 海力士半导体有限公司 | Method of forming a gate of a semiconductor device |
| KR20090119229A (en) * | 2008-05-15 | 2009-11-19 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| CN101728252A (en) * | 2008-10-24 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming flash memory grid electrode and flash memory |
| CN101770160A (en) * | 2009-12-30 | 2010-07-07 | 上海集成电路研发中心有限公司 | Method for protecting mask |
-
2013
- 2013-05-14 CN CN201310178630.3A patent/CN104157559A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1614751A (en) * | 2003-11-03 | 2005-05-11 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
| US20050095783A1 (en) * | 2003-11-05 | 2005-05-05 | Haselden Barbara A. | Formation of a double gate structure |
| CN1767173A (en) * | 2004-10-26 | 2006-05-03 | 中芯国际集成电路制造(上海)有限公司 | Novel pretreatment method for alumina atom illuvium |
| CN101083207A (en) * | 2006-03-31 | 2007-12-05 | 奇梦达股份公司 | Method and device for depositing a protective layer during an etching procedure |
| CN101211770A (en) * | 2006-12-28 | 2008-07-02 | 海力士半导体有限公司 | Method of forming a gate of a semiconductor device |
| KR20090119229A (en) * | 2008-05-15 | 2009-11-19 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| CN101728252A (en) * | 2008-10-24 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming flash memory grid electrode and flash memory |
| CN101770160A (en) * | 2009-12-30 | 2010-07-07 | 上海集成电路研发中心有限公司 | Method for protecting mask |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992177A (en) * | 2017-02-14 | 2017-07-28 | 上海华虹宏力半导体制造有限公司 | Prevent the technique manufacturing method in flash cell control gate cavity |
| CN106992177B (en) * | 2017-02-14 | 2020-05-01 | 上海华虹宏力半导体制造有限公司 | Process manufacturing method for preventing flash memory unit control grid cavity |
| CN110634876A (en) * | 2019-09-30 | 2019-12-31 | 上海华力集成电路制造有限公司 | Method for manufacturing flash memory device |
| CN110634876B (en) * | 2019-09-30 | 2022-03-18 | 上海华力集成电路制造有限公司 | Method for manufacturing flash memory device |
| CN111785723A (en) * | 2020-07-24 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split-gate memory |
| CN111785723B (en) * | 2020-07-24 | 2023-07-11 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split gate type memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104752363B (en) | The forming method of flash memory | |
| TW407381B (en) | Manufacture of the flash memory cell | |
| KR102078187B1 (en) | Semiconductor device and fabricating method thereof | |
| CN100477132C (en) | Method for fabricating semiconductor wafer, semiconductor device and non-volatile memory device | |
| CN104425366B (en) | The forming method of semiconductor structure | |
| CN106206598B (en) | Gate-division type flash memory device making method | |
| US20150056795A1 (en) | Method of manufacturing semiconductor device | |
| CN104157559A (en) | Manufacture method of control gate and manufacture method of floating gate | |
| CN103258860A (en) | Semiconductor memory and manufacturing method thereof | |
| CN105097549A (en) | Method for manufacturing gate-all-around structure | |
| CN101630655A (en) | Shallow trench isolation corner rounding | |
| CN105336705B (en) | The manufacturing method of flash memory structure | |
| CN104091786A (en) | Method for forming flash memory | |
| CN107204339A (en) | The forming method of isolation structure and the forming method of semiconductor structure | |
| CN104867831A (en) | Manufacturing method of semiconductor device structure | |
| CN103346127B (en) | Flash memory device structure and preparation method | |
| CN108807393A (en) | Memory and forming method thereof | |
| CN110752213A (en) | Method for manufacturing semiconductor structure | |
| CN103943625B (en) | A kind of NAND flash memory device and manufacture method thereof | |
| CN103021925A (en) | STI (shallow trench isolation) manufacturing process, trench etching method and photoresist processing method | |
| CN105140229A (en) | Method for manufacturing flash memory device | |
| CN104157614A (en) | Manufacture method for separated grid type flash memory | |
| CN105405809A (en) | Method of manufacturing flash memory | |
| CN104465525A (en) | Forming method for embedded flash memory | |
| CN105140176B (en) | A kind of semiconductor devices and its manufacture method and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20141119 |