CN104134664A - 具有沟槽场板的高压双极型晶体管 - Google Patents

具有沟槽场板的高压双极型晶体管 Download PDF

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CN104134664A
CN104134664A CN201410345970.5A CN201410345970A CN104134664A CN 104134664 A CN104134664 A CN 104134664A CN 201410345970 A CN201410345970 A CN 201410345970A CN 104134664 A CN104134664 A CN 104134664A
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bipolar transistor
transistor
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C.卡道
N.克里施克
T.迈尔
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Infineon Technologies Austria AG
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Abstract

本发明涉及具有沟槽场板的高压双极型晶体管。一种双极型晶体管结构包括：半导体衬底上的外延层；在外延层中形成的双极型晶体管器件；以及在外延层中形成的沟槽结构，与双极型晶体管器件的至少两个相对的横向侧面相邻。该沟槽结构包括通过绝缘材料而与外延层隔开的场板。该双极型晶体管结构进一步包括：基极触点，连接到双极型晶体管器件的基极；发射极触点，连接到双极型晶体管器件的发射极并且与所述基极触点隔离；以及在发射极触点和场板之间的电气连接。

Description

具有沟槽场板的高压双极型晶体管
本申请是于2011年7月8日提交的申请号为201110190700.8且发明名称为“具有沟槽场板的高压双极型晶体管”的中国发明专利申请的分案申请。
技术领域
本发明涉及一种具有沟槽场板（trench field plate）的高压双极型晶体管。
背景技术
诸如VDMOS（垂直扩散金属氧化物半导体）晶体管的功率MOS（金属-氧化物-半导体）器件的击穿电压可以根据用于制造器件的技术而从约30V变化至数百伏（例如，100V至200V）。对于击穿电压以上的漏极电压，非常大量的电流在DMOS器件中流动。该条件典型地被称为雪崩击穿。雪崩击穿在不被减弱的情况下损坏功率DMOS器件。
对于双极型晶体管，对于具有浮动基极的双极型器件，最大工作电压典型地限于集电极-基极二极管击穿电压（Vcbo）以下的且集电极-发射极击穿电压（Vceo）以上的值。当双极型器件处于Vceo和Vcbo之间的有源（active）工作时，可能出现器件不稳定性。当Vce上升到特定的临界电压以上时，双极型器件进入高电流状态。高电流状态由器件的基极-集电极空间电荷区中生成的碰撞离子化电流的双极型放大驱动。在一些情况中，双极型器件可能进入横向不稳定性或收缩（pinch-in）不稳定性，其中电流流动收缩到离基极触点最远的点处的非常窄的沟道中。双极型器件可能进入垂直不稳定性或等离子体状态，其中基极和基极-集电极空间电荷区充满两种类型的载流子。该状态对应于关断器件的Vceo击穿电压。在该状态中并且根据基极和发射极上的偏置条件，由于充满基极集电极空间电荷区的载流子有效减小了峰值电场，总电流仍可能受器件自身限制。这些高电流状态中的每个导致了发射极和基极上的具有非常高幅度的振荡行为。即便双极型器件自身在该振荡状态中未损坏，但是振荡给相邻电路块中的其他低电压器件造成非常严重的威胁并且应被避免。
由于这些效应，双极型晶体管的工作电压小于诸如在相同外延半导体层中构造的垂直DMOS的对应单极型器件的工作电压。这限制了在相同管芯上提供功率晶体管和双极型晶体管的集成功率技术的技术电压，并且因此给技术的优化造成了严重的约束，尤其是对于DMOS导通电阻。本质上，必须在对于功率晶体管有利的高掺杂薄外延层和对于双极型晶体管有利的较低掺杂的较厚外延层之间进行权衡。
特别是CMOS-DMOS类型（即具有衬底上的公共漏极的垂直DMOS）的现有功率技术必须极为小心以避免触发寄生衬底双极并且控制寄生衬底双极的有源工作期间的最大集电极电压。再者，外延层的最小可用厚度是针对DMOS器件的导通电阻的非常重要的优化参数并且可能受寄生衬底双极限制。对于一些功率应用，可以使用SOI（绝缘体上硅）技术，其中器件被介电隔离并且因此可以更容易地进行单独优化。然而，SOI成本高于非SOI技术。在高级的双极型技术中，深沟槽隔离和/或浅沟槽隔离用于终止双极型器件，但是不作为核心双极型晶体管的构造元件。作为代替，沟槽结构仅用于横向隔离并且不影响核心双极型晶体管的电气特性。
发明内容
根据双极型晶体管结构的实施例，该结构包括：半导体衬底上的外延层；在外延层中形成的双极型晶体管器件；以及在外延层中形成的沟槽结构，与双极型晶体管器件的至少两个相对的横向侧面相邻。该沟槽结构包括通过绝缘材料而与外延层隔开的场板。基极触点连接到双极型晶体管器件的基极并且发射极触点连接到双极型晶体管器件的发射极。发射极触点与基极触点隔离。在发射极触点和场板之间提供电气连接。
根据制造双极型晶体管结构的方法的实施例，该方法包括：在半导体衬底上形成外延层；在外延层中形成双极型晶体管器件；以及在外延层中形成与双极型晶体管器件的至少两个相对的横向侧面相邻的沟槽结构。沟槽结构包括通过绝缘材料而与外延层隔开的场板。该方法进一步包括将基极触点连接到双极型晶体管器件的基极并且将发射极触点连接到双极型晶体管器件的发射极，从而发射极触点与基极触点彼此隔离。在发射极触点和场板之间形成电气连接。
根据集成晶体管结构的实施例，该结构包括：半导体衬底上的外延层；在外延层的第一区中形成的功率晶体管，具有漏极区、源极区和短接（short）到源极区的体区；以及在外延层的第二区中形成的双极型晶体管，与功率晶体管隔开。第一沟槽结构在外延层中形成为与功率晶体管的至少两个相对的横向侧面相邻。第一沟槽结构包括通过绝缘材料而与功率晶体管的沟道区隔开的栅极电极。第二沟槽结构在外延层中形成为与双极型晶体管的至少两个相对的横向侧面相邻。第二沟槽结构包括通过绝缘材料而与外延层隔开的沟槽电极。栅极电极、双极型晶体管的基极、以及双极型晶体管的发射极连接到彼此隔离的不同触点。发射极和沟槽电极处于相同的电位。
根据集成电路的实施例，该集成电路包括在相同外延半导体层中形成的垂直扩散MOS功率晶体管和双极型晶体管。垂直扩散MOS功率晶体管具有短接到体区的源极区以及通过绝缘材料而与沟道区隔开的栅极电极。栅极电极、双极型晶体管的基极、以及双极型晶体管的发射极连接到彼此电气隔离的不同触点。双极型晶体管的至少两个相对的横向侧面与在外延层中形成的沟槽结构相邻，该沟槽结构包括通过绝缘材料而与外延层隔开的沟槽电极。发射极和沟槽电极处于相同的电位。
本领域的技术人员在阅读下面的详细描述后并且在查看附图后将认识到另外的特征和优点。
附图说明
附图中的部件不一定按比例绘制，而是着重于说明本发明的原理。此外，在附图中，相同的附图标记表示对应部分。在附图中：
图1是根据实施例的双极型晶体管结构的俯视平面图；
图2是图1中的双极型器件的示意性横截面图；
图3是根据另一实施例的双极型晶体管结构的俯视平面图；
图4是根据又一实施例的双极型晶体管结构的俯视平面图；
图5是在与相同管芯上的双极型晶体管相同的外延层的不同区中形成的功率晶体管的实施例的俯视平面图；
图6是图5中的功率晶体管的示意性横截面图；
图7是在与相同管芯上的双极型晶体管相同的外延层的不同区中形成的功率晶体管的另一实施例的俯视平面图；
图8是图7中的功率晶体管的示意性横截面图；
图9是根据实施例的与双极型器件的至少两个相对的横向侧面相邻的沟槽结构的示意性横截面图；以及
图10是与双极型器件的至少两个相对的横向侧面相邻的沟槽结构的另一实施例的示意性横截面图。
图11图示了采用图1中的双极型器件的两个电路的实施例的电路示意图。
具体实施方式
这里描述的实施例提供了一种其中使驱动这里先前描述的不稳定性的影响最小化的器件设计。器件嵌入在台面类型结构中，即嵌入在包括场板的沟槽之间的窄的硅带（stripe）中。台面带与小的发射极-基极间距一起减少了各个晶体管单元的空间延伸，使横向不稳定性的可用距离最小化。
图1图示了根据实施例的双极型晶体管结构100的俯视平面图。图2图示了图1中的双极型晶体管结构100沿标有A-A'的线的示意性横截面图。双极型晶体管结构100包括在诸如硅衬底或化合物半导体衬底的半导体衬底104上生长的外延层102。双极型晶体管器件在外延层102中形成。双极型器件具有集电极，该集电极包括衬底104和外延层102的在衬底104和基极106之间的部分。基极106与集电极相邻并且发射极108与基极106相邻，从而基极106在垂直于衬底104的方向上置于集电极和发射极108之间。根据该实施例，基极106和发射极108具有相同的横截面宽度。
在一些实施例中，衬底104、外延层102和发射极108是n掺杂的，并且基极106是p掺杂的。在其他实施例中，双极型器件的这些区具有相反的掺杂类型。在任一配置中，例如由钨或者任何其他适当材料制成的基极触点110连接到基极106，并且例如由钨或者任何其他适当材料制成的发射极触点112连接到发射极108并且与基极触点110隔离以确保双极型器件的正确工作。基极106可以具有与每个基极触点110相邻为较高掺杂浓度而在其他位置为较低掺杂浓度的第一区。在一个实施例中，基极106的净剂量的范围是0.5e13/cm2至1e14/cm2。备选地，基极106可以具有到处大体均匀的掺杂浓度。在图1中示出了两个基极触点110，但是可以提供任何期望数目的基极触点。基极金属连接114耦合到每个基极触点110并且发射极金属连接116类似地耦合到发射极触点112以提供双极型器件的连接端子。为了易于说明起见，图2仅示出了从外延层102的上表面到衬底104的双极型器件，并且因而在图2中未示出触点110/112和金属连接114/116。
在外延层102中形成沟槽结构118，其与双极型晶体管器件的至少两个相对的横向侧面120、122相邻。根据图1中示出的实施例，沟槽结构118在双极型晶体管器件的所有横向侧面上围绕双极型晶体管器件。沟槽结构118包括通过绝缘材料126而与外延层102隔开的场板124。例如由多晶硅或任何其他适当材料制成的场板触点128连接到沟槽结构118的场板124。图1示出了发射极触点112和场板触点128之间的电气连接，从而发射极108和场板124处于相同的电位。因此，发射极108和场板124可以耦合到零或负电位以确保双极型器件的最优性能。场板124因此形成了有源双极型器件的部分，并且沟槽结构118不仅仅用于器件隔离。
由沟槽场板构造导致的基极-集电极击穿电压比模拟器件的平面阱的对应垂直击穿电压高很多。这样，针对给定电压使电场幅度最小化并且因此使碰撞离子化最小化。此外，根据该实施例，沟槽场板124电气连接到发射极108，确保寄生垂直MOS器件不接通。再者，沟槽场板124和衬底104（即集电极）之间的电容构成了针对器件振荡的阻尼元件。对于足够窄的台面带，最大电场的位置位于沟槽结构118的内部底边缘处，并且如图2中的箭头指示的，主要的双极型电流路径位于台面区的中间，使基极-集电极空间电荷区内的碰撞离子化最小化。
沟槽结构118可以延伸到外延层102中达到深度DT，DT的范围介于外延层102的厚度Tepi的1/3和1.5倍之间。沟槽结构118的宽度WT和在外延层102的由沟槽结构118围绕的区中的外延层102的宽度Wepi之间的比可以介于2/1和1/2之间。基极106和集电极之间形成的结可以处于外延层102中的深度DJ处，该深度DJ介于沟槽结构118的深度DT的1/10和4/5之间。在一些实施例中，如图2中所示，场板124远离衬底104是较厚的（TTU）而接近衬底104是较薄的（TTL）。
图3图示了根据另一实施例的双极型晶体管结构300的俯视平面图。根据该实施例，双极型晶体管器件由在外延层（在图3中看不见）中形成的多个晶体管单元302形成。每个晶体管单元302包括集电极（在图3中看不见）、与集电极相邻的基极304和与基极304相邻的发射极306，从而基极304在垂直于衬底（在图3中看不见）的方向上置于集电极和发射极306之间。每个晶体管单元302具有用于接触基极304的一个或多个基极触点308以及用于接触每个晶体管单元302的发射极306的一个或多个发射极触点310。沟槽结构312包括通过绝缘材料316而与外延层隔开的场板314。在图3中示意性地示出了每个晶体管单元302的发射极触点310和沟槽结构312的场板314之间的电气连接，从而每个单元302的发射极306和场板314处于相同的电位。根据该实施例，沟槽结构312在每个晶体管单元302的所有横向侧面318、320、322、324上围绕每个晶体管单元302，但是对于开放式沟槽技术可以与每个单元的两个相对的横向侧面相邻。其中形成双极型器件的沟槽之间的硅外延层的相对窄的区减少了各个单元的空间延伸，使横向不稳定性的可用距离最小化。在一些实施例中，各个发射极单元的宽度/长度比的范围可以是从1:3至1:20。
图4图示了根据又一实施例的双极型晶体管结构400的俯视平面图。根据该实施例，双极型晶体管器件由在外延层（在图4中看不见）中形成的多个晶体管单元402形成。每个晶体管单元402包括集电极（在图4中看不见）、与集电极相邻的基极404和与基极404相邻的发射极406，从而基极404在垂直于衬底（在图4中看不见）的方向上置于集电极和发射极406之间。每个晶体管单元402具有用于接触基极404的一个或多个基极触点408以及用于接触每个晶体管单元402的发射极406的一个或多个发射极触点410。沟槽结构412包括通过绝缘材料416而与外延层隔开的场板414。在图4中示意性地示出了每个晶体管单元402的发射极触点410和沟槽结构412的场板414之间的电气连接，从而每个单元402的发射极406和场板414处于相同的电位。不同于图3中示出的实施例，晶体管单元402直接地彼此相邻（即各个单元之间没有居间沟槽）并且相邻的单元402可以共享基极区。根据该实施例，沟槽结构412在双极型晶体管器件的所有外部横向侧面418、420、422、424上围绕多个晶体管单元402，但是对于开放式沟槽技术可以与每个单元的两个相对的横向侧面相邻。
场板沟槽构造允许高得多的基极掺杂水平而不会不利地影响集电极-基极击穿电压，提供了用于使双极型电流增益和内部基极电阻优化的更大灵活性。这使得双极型器件和功率器件能够容易地集成在相同管芯上以及处于相同外延层中，提供了在选择外延层厚度和基极掺杂方面的更大灵活性。
图5图示了在与相同管芯上的双极型晶体管相同的外延层的不同区中形成的功率晶体管的实施例的俯视平面图。图6图示了图5中的功率晶体管沿标有B-B’的线的示意性横截面图。由于双极型晶体管在外延层的不同区中形成并且与功率晶体管隔开，因此其在图5和6中看不见。双极型晶体管可以根据这里描述的任何双极型晶体管结构实施例来形成。双极型晶体管和功率晶体管一起形成集成晶体管结构。
功率晶体管的至少两个相对的横向侧面与在衬底504上的外延层502中形成的沟槽结构500相邻。不同于这里描述的双极型晶体管实施例，与功率晶体管相邻的沟槽结构500包括通过绝缘材料508而与功率晶体管的沟道区隔开的栅极电极506。栅极电极506控制在功率晶体管的体510中出现的沟道的反型，并且因此控制功率晶体管的导通状态。栅极电极506未连接到功率晶体管的体510或源极512。衬底504形成了功率晶体管的漏极。具有与基极510相同的掺杂类型的垂直带514在功率晶体管的中心形成并且穿过源极512延伸到体510中，短接功率晶体管的源极512和体510。
如图5和6中所示，功率晶体管可以是诸如VDMOS晶体管的DMOS类型功率晶体管。功率晶体管的栅极电极506、双极型晶体管的基极（在图5和6中看不见）以及双极型晶体管的发射极（在图5和6中也看不见）连接到彼此隔离的不同触点，为了易于说明功率晶体管起见未示出这些触点。如这里先前所描述的，双极型晶体管的发射极和在与双极型晶体管的至少两个相对的横向侧面相邻的沟槽结构中包括的沟槽电极处于相同的电位。根据实施例，如这里先前所描述的，在与双极型晶体管相邻的沟槽结构中包括的沟槽电极和连接到双极型晶体管的发射极的发射极触点之间形成电气连接，从而发射极和沟槽电极处于相同的电位，例如零或负电位。
图7图示了在与相同管芯上的双极型晶体管相同的外延层的不同区中形成的功率晶体管的另一实施例的俯视平面图。图8图示了图7中的功率晶体管沿标有C-C’的线的示意性横截面图。由于双极型晶体管在外延层的不同区中形成并且与功率晶体管隔开，因此其在图7和8中看不见。双极型晶体管可以根据这里描述的任何双极型晶体管结构实施例来形成。双极型晶体管和功率晶体管一起形成集成晶体管结构。
图7和8的功率晶体管具有与图5和6的功率晶体管相同的结构，除了具有交替的不同掺杂类型的源极区和体区600、602，它们具有在外延层502的顶表面上形成的公共触点604。公共触点604将功率晶体管的源极600短接到体602。这里描述的功率晶体管可以具有n型衬底、p型体和n型源极。备选地，这里描述的功率晶体管可以具有p型衬底、n型体和p型源极。在任一情况中，包括功率晶体管和双极型晶体管的集成晶体管结构实施例可以用于制造使用功率晶体管和双极型晶体管两者的电路。在一些实施例中，单片管芯包括具有DMOS功率器件的双极型和/或CMOS控制电路。一种类型的电路可以包括例如用于电机的包括输入级和输出级的驱动器。输入电路具有控制输入，其可以包括诸如具有滞后作用（hysteresis）的施密特触发器的双极型和/或CMOS电路。双极型晶体管可以根据这里公开的任何双极型晶体管结构实施例来实现。输出级可以包括诸如半桥的DMOS电路。DMOS晶体管在与双极型晶体管相同的外延层中根据这里公开的任何功率晶体管结构实施例来实现。当然，本领域的技术人员可以容易地在其他电路设计中利用这里描述的集成晶体管结构实施例。这里描述的沟槽结构实施例提供了充分的晶体管隔离同时还通过将沟槽电极集成到有源双极型晶体管单元中而使双极型晶体管更鲁棒，如这里描述的。
图9图示了根据实施例的与双极型器件的至少两个相对的横向侧面相邻的沟槽结构900的示意性横截面图。该双极型器件具有集电极，该集电极包括衬底902和外延层904的在衬底902和器件的基极906之间的部分。在外延层904中在基极906上方形成发射极908。在外延层904中形成沟槽结构910，该沟槽结构910与双极型晶体管器件的至少两个相对的横向侧面912、914相邻。沟槽结构910包括通过绝缘材料918而与外延层904隔开的场板916。根据该实施例，与发射极908和基极两者相邻的场板916具有大体均匀的宽度。场板916是连续的并且具有单体构造。
图10图示了与双极型器件的至少两个相对的横向侧面相邻的沟槽结构920的另一实施例的示意性横截面图。该双极型器件具有与图9中示出的器件相同的构造。然而，沟槽结构中的场板包括设置在沟槽结构920的下部分中的第一导电区922和在第一导电区922上方的设置在沟槽结构920的上部分中的第二导电区924。第一和第二导电区922、924通过绝缘材料926而彼此隔开。如这里先前所描述的，第二（上）导电区920经由电气连接而耦合到发射极触点（看不见），从而场板的上部分922和发射极908处于相同的电位。第一（下）导电区924处于与发射极908或基极906相同的电位。
图11图示了采用这里描述的任何双极型晶体管结构的两个电路1100和1110。第一电路1100包括耦合到电压源（Vs）和地（GND）的电压参考生成器1102、负载1104以及具有根据这里先前描述的任何实施例的结构的高压双极型晶体管1106。电压参考生成器1102的输出耦合到高压双极型晶体管1106的基极。作为响应，高压双极型晶体管1106向负载1104提供内部供给电压。该供给电压可以在闭环配置中反馈到电压参考生成器1102。第二电路1110包括耦合在差分放大器配置中的两个高压双极型晶体管1112和1114。两个高压双极型晶体管1112和1114均具有根据这里先前描述的任何实施例的结构。第二电路1110进一步包括运算放大器1116，其响应于由相应双极型晶体管1112和1114提供的差分信号输入（IN+/IN-）而产生输出（OUT）。由成对的双极型晶体管1112和1114形成的差分放大器响应于到相应双极型晶体管1112和1114的输入（IN HV+/IN HV-）中的差的幅值来驱动运算放大器1116。这里描述的双极型晶体管结构可以用在各种其他类型的电路中，并且因此图11中示出的电路是示例性电路并且不应以任何方式视为限制性的。
诸如“下面”、“以下”、“下”、“上方”、“上”等的空间相对术语用于使描述方便，以解释一个元件相对于第二元件的定位。这些术语旨在涵盖除了与图中示出的那些取向不同的取向以外的器件的不同取向。此外，诸如“第一”、“第二”等的术语还用于描述各种元件、区、部分等，并且也不旨在是限制性的。在通篇描述中相同的术语指代相同的元件。
如这里使用的，术语“具有”、“含有”、“包含”、“包括”等是开放式术语，其指示所陈述的元件或特征的存在，但是并未排除另外的元件或特征。除非上下文另外明确地指示，否则冠词“一”、“一个”和“该”旨在包括复数和单数。
考虑到变化和应用的以上范围，应理解，本发明不受前面的描述限制也不受附图限制。作为代替，本发明仅受所附权利要求及其合法等同物限制。

Claims (7)

1.一种集成晶体管结构，包括：
半导体衬底上的外延层；
在所述外延层的第一区中形成的功率晶体管，具有漏极区、源极区和短接到所述源极区的体区；
在所述外延层的第二区中形成的具有集电极、基极和发射极的双极型晶体管，与所述功率晶体管隔开；
第一沟槽结构，在所述外延层中形成为与所述功率晶体管的至少两个相对的横向侧面相邻，所述第一沟槽结构包括通过绝缘材料而与所述功率晶体管的沟道区隔开的栅极电极；
第二沟槽结构，在所述外延层中形成为与所述双极型晶体管的至少两个相对的横向侧面相邻，所述第二沟槽结构包括通过绝缘材料而与所述外延层隔开的沟槽电极；
其中所述栅极电极、所述双极型晶体管的基极、以及所述双极型晶体管的发射极连接到彼此隔离的不同触点；以及
其中所述发射极和所述沟槽电极处于相同的电位。
2.根据权利要求1所述的集成晶体管结构，包括与所述双极型晶体管相邻的所述沟槽电极和连接到所述双极型晶体管的发射极的发射极触点之间的电气连接，从而所述发射极和所述沟槽电极处于相同的电位。
3.根据权利要求1所述的集成晶体管结构，其中所述第二沟槽结构延伸到所述外延层中达到范围介于所述外延层的厚度的1/3和1.5倍之间的深度。
4.根据权利要求1所述的集成晶体管结构，其中所述第二沟槽结构的宽度和由所述第二沟槽结构围绕的所述外延层的宽度之间的比介于2/1和1/2之间。
5.根据权利要求1所述的集成晶体管结构，其中在所述第二沟槽结构的深度的1/10和4/5之间的所述外延层中的深度处，在所述双极型晶体管的所述基极和集电极之间形成结。
6.根据权利要求1所述的集成晶体管结构，其中所述发射极和所述沟槽电极处于零或负电位。
7.一种集成电路，包括在相同外延半导体层中形成的垂直扩散MOS功率晶体管和具有集电极、基极和发射极的双极型晶体管，所述垂直扩散MOS功率晶体管具有短接到体区的源极区以及通过绝缘材料而与沟道区隔开的栅极电极，所述栅极电极、所述双极型晶体管的基极、以及所述双极型晶体管的发射极连接到彼此电气隔离的不同触点，所述双极型晶体管的至少两个相对的横向侧面与在外延层中形成的沟槽结构相邻，所述沟槽结构包括通过绝缘材料而与所述外延层隔开的沟槽电极，所述发射极和所述沟槽电极处于相同的电位。
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