CN104126283A - Automatic detection and compensation of frequency offset in point-point communication - Google Patents
Automatic detection and compensation of frequency offset in point-point communication Download PDFInfo
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- CN104126283A CN104126283A CN201380010030.4A CN201380010030A CN104126283A CN 104126283 A CN104126283 A CN 104126283A CN 201380010030 A CN201380010030 A CN 201380010030A CN 104126283 A CN104126283 A CN 104126283A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
Abstract
Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication are provided. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency.
Description
Open field
The disclosed embodiment relates to clock recovery in point-to-point communication and synchronous.More specifically, each exemplary embodiment relates to frequency shift (FS) and the frequency shift (FS) in transmitter/receiver systems and this frequency shift (FS) of auto-compensation detecting between transmitter terminal and the clock at receiver end place.
Background
Generally speaking, Point-to-Point Data communication will require clock/data frequency between transmitter terminal and receiver end, to want synchronous.For example, with reference to Figure 1A, by transmitter 101 and receiver 102, explain orally one way transmitter-receiver system 100.Data transmit in channel 103.Transmitter 101 operates with the frequency deriving from reference clock 105, and receiver 102 operates with the frequency deriving from reference clock 106.Although in desirable case scenario, reference clock 105 and 106 both will be with same frequency F vibration, in the Design and manufacture of this ideal case scene due to system 100, intrinsic process variations seldom realizes.Correspondingly, the reference frequency F+ Δ F that reference clock 105 can data 103 be transmitted operates, and the reference clock 106 at receiver end place can operate by reference frequency F, wherein Δ F can be on the occasion of or negative value.This change or shifted by delta F can stop data 103 that receiver 102 places receive at receiver end place Complete Synchronization.In high-speed data communication, even if small Δ F value also may cause high bit error rate, and this may be unacceptable.
Same visible above problem in the employing transceiver 111 being explained orally in the system 110 as Figure 1B and 112 two-way communication.As shown, the reference clock 115 that transceiver 111 (comprising transmitter TX1 and receiver RX1) is located can operate by frequency F+ Δ F, and the reference clock 116 that transceiver 112 (comprising transmitter TX2 and receiver RX2) is located can operate by frequency F.Thereby, from transceiver 111, be communicated to 112 data 113 and be communicated to 111 data 114 from transceiver 112 and will suffer non-Complete Synchronization.
In system 100 and 110 in both, due to the reference clock that uses clock separately as place, data communication two ends, for synchronous known technology (such as the transfer of data with embedded clock) be poor efficiency and because frequency shift (FS) Δ F causes expensive design cost.In addition, reference clock mentioned above is easy to suffer the frequency drift (it can further aggravate frequency shift (FS)) being caused by aging, temperature change etc.Frequency shift (FS) can further make systematic function and bit error rate demote by reducing the tolerance border of clock jitter.Thereby frequency shift (FS) may cause the quality that is associated with data transmission and reception and the remarkable degradation of cost.
Referring now to Fig. 2 A-2C, explained orally the routine techniques for contrary frequency deviation effect, and will their shortcoming be discussed by reference to accompanying drawing.First, Fig. 2 A has explained orally closed-loop simulation clock and data recovery (CDR) system 200 based on phase-locked loop (PLL).System 200 can be integrated in receiver end place (such as the receiver 102 of system 100 or the transceiver 111 and 112 of system 110) to will receive that data (such as 103,113 or 114) synchronize with local reference clock.In system 200, the data of receiving (input data) are simulation non-return-to-zero (NRZ) signals, and it is the input to phase detectors 202.Phase detectors 202 are followed the tracks of the phase place of NRZ input data and signal Up (making progress) and the Dn (downwards) that frequency changer 203 is gone in generation, and frequency changer 203 and then generation are through the response of low pass filter 204 and arrival voltage controlled oscillator (VCO) 205.The output of VCO 205 is fed back to phase detectors 202 to complete loop 207.Loop 207 forms PLL, and PLL helps the phase alignment with input data by the phase place of local reference clock, thereby generates the clock through recovering in the output of VCO 205.Clock through recovering can cushion and be sampled device 201 by buffer 206 and be used for to sampling input data to generate the data through recovering.System 200 is out-of-date in its application, because it is mainly configured in analog domain.In addition,, although the PLL being formed by loop 207 helps phase alignment, it cannot contribute to the input frequency of data and the Frequency Synchronization of local reference clock.Therefore, system 200 is not effective overcoming aspect the above-mentioned shortcoming of frequency shift (FS).
With reference now to Fig. 2 B,, explained orally the closed-loop digital CDR system 210 based on phase interpolator (PI).In system 210, the local reference clock operating with frequency Fref aligns with the data phase in main PLL (MPLL) 218.Reference clock in frequency Fref is through MPLL 218 and be fed to phase interpolator (PI) 217.PI 217 also receive from CDR loop 219 another input, CDR loop 219 comprise switching regulator (bang-bang) phase detectors (! ! PD) 214, digital loop filters 214, sigma-delta modulator 215 and decoder 216.Compare with system 200, switching regulator phase detectors 213 generate binary digit output upwards (Up) and downward (Down), and this contributes to bring the CDR scheme of system 210 into numeric field.Use loop CDR 219 (especially sigma-delta modulator 215 and decoders 216), phase information through recovered clock is fed to PI 217, by these PI 217 use phase informations, together with the reference clock frequency of deriving from MPLL 218, changes the phase place through recovered clock.Receive that data (input data) are fed by equalizer 211, the analogue data output of equalizer 211 is sampled device 212 and uses from the phase place input of PI 217 and sample, and this makes the sampler 212 can be in correct position and in the correct time to sampling input data.Yet if frequency and the Fref of input data have frequency shift (FS), CDR loop 219 will not be effective.In addition,, if frequency shift (FS) is high, the building-blocks of CDR loop 219 will seriously over-burden, thereby cause the performance degradation of system 210.
With reference now to Fig. 2 C,, explained orally conventional burst mode open loop CDR system 220.System 220 is configured for receives data (input data), receive data can be attended by due to the burst of the time-out causing such as events such as channel switch receive.The local reference clock operating with frequency Fref is imported into phase-frequency detector (PFD) 221, and it is to frequency changer (CP) 222 output up/down signals.Similar with system 200, frequency-tracking piece 229 comprises the PLL being formed by PFD 221, CP 222, filter 223, shared GVCO 224 and frequency divider 225.Share GVCO 224 and be its VCO that comprises gating (GVCO) with the difference of the VCO 205 of system 200.GVCO can be configured to gating VCO, thereby realize, by the gating signal of edge or level triggers, is controlled.Frequency divider 225 is configured to carry out Fractional-N frequency to phase difference is reduced to sharing the frequency output of GVCO 225, and wherein N can be integer or the mark of suitable selection.Thereby the clock recovering from the PLL of frequency-tracking piece 229 at point 226 places is used to control copy GVCO 227.
In ideal case, it is identical with shared GVCO 224 that copy GVCO 227 will be designed to, so that the vibration of copy GVCO 112 can be mated the vibration of sharing GVCO 224 under stable state.Yet on sheet, fluctuation and process variations may cause departing from the small of this ideal case, thereby cause frequency of occurrences shifted by delta F2 between shared GVCO 224 and the frequency of oscillation of copy GVCO227.This frequency shift (FS) Δ F2 may be the frequency shift (FS) the frequency shift (FS) between the data that may Already in receive (input data) and Fref.
Continue with reference to figure 2C, by 227 pairs of sampling input datas of copy GVCO, to generate through recovered clock, this controls the clock input of d type flip flop (DFF) 228 through recovered clock.Can the input data as Serial data receiving carry out serial parallel conversion to generate output (data through recovering) by 228 couples of DFF subsequently.Yet due to above-mentioned imperfect situation, frequency shift (FS) Δ F and Δ F2 may cause error and the performance degradation of system 220.In addition the jitter tolerance that, also depends on the system 220 of frequency shift (FS) Δ F and Δ F2 also will correspondingly reduce.
Therefore, can see, in each system in above-mentioned conventional CDR system 200,210 and 220, be not enough to solve the problem relevant with frequency shift (FS).Other known technology attempts to improve the accuracy of reference clock with expensive high quality crystal oscillator, but this may obtain too high cost and remain not enough.Seek the frequency shift (FS) of estimation to bring in the reference clock of customization so that some Custom Design of compensating frequency deviation are also known in this area.Yet the accuracy of such Custom Design seriously reduces along with the increase of transmission frequency.
Therefore, exist in the art overcoming the needs of the CDR system of the problems referred to above that are associated with frequency shift (FS).
Summary of the invention
Each exemplary embodiment of the present invention relates to the system and method for the frequency shift (FS) of point-to-point communication is automatically detected and compensated.
For example, an exemplary embodiment relates to a kind of burst mode clock and data recovery (CDR) system, comprising: the input data that receive with first frequency; Reference clock with second frequency operation; The main phase-locked loop (PLL) that comprises the first gating voltage controlled oscillator (GVCO), the phase alignment in order to the phase place with reference to clock with input data, and phase error information and the clock through recovering are provided; The 2nd GVCO, its by the clock control through recovering with to sampling input data; And frequency alignment loop, comprise that feedback path from the 2nd GVCO to main PLL is to proofread and correct the frequency shift (FS) first frequency and second frequency with phase error information.
Another exemplary embodiment relates to a kind of digital dock and data based on phase interpolator (PI) and recovers (CDR) system, comprising: the input data that receive with first frequency; Reference clock with second frequency operation; Main phase-locked loop (PLL), for the phase alignment of the phase place with reference to clock and input data; Be coupled to the phase interpolator of the output of main PLL; And frequency alignment loop, it comprises that feedback path from phase interpolator to main PLL is to proofread and correct the frequency shift (FS) first frequency and second frequency.
Another exemplary embodiment relates to clock and data recovery (CDR) system, comprising: the input data that receive with first frequency; Reference clock with second frequency operation; Device for detection of the phase error information between input data and reference clock; Use detected phase error information to detect the device of the frequency shift (FS) between first frequency and second frequency; And for eliminating the device of this frequency shift (FS).
Another exemplary embodiment relates to a kind of method of carrying out clock and data recovery at receiver place, and the method comprises: with first frequency, from transmitter, receive input data; Reference clock based on integrated in receiver operates receiver with second frequency; Detect the phase error information between input data and reference clock; With detected phase error information, detect the frequency shift (FS) between first frequency and second frequency; And eliminate this frequency shift (FS) so that first frequency and second frequency are synchronous.
Another exemplary embodiment relates to the method for a kind of configuration burst mode clock and data recovery (CDR) system, and the method comprises: with first frequency, receive input data; With second frequency operation reference clock; Configuration comprises that the main phase-locked loop (PLL) of the first gating voltage controlled oscillator (GVCO) is with the phase place with reference to clock and the phase alignment of inputting data, and phase error information and the clock through recovering are provided; Configure the 2nd GVCO, its by the clock control through recovering with to sampling input data; And configuration frequency alignment loop, it comprises that feedback path from the 2nd GVCO to main PLL is to proofread and correct the frequency shift (FS) first frequency and second frequency with phase error information.
Another exemplary embodiment relates to the digital dock of a kind of configuration based on phase interpolator (PI) and the method for data recovery (CDR) system, and the method comprises: with first frequency, receive input data; With second frequency operation reference clock; Configure main phase-locked loop (PLL) with the phase alignment of the phase place with reference to clock and input data; Phase interpolator is coupled to the output of main PLL; And configuration frequency alignment loop, it comprises that feedback path from phase interpolator to main PLL is to proofread and correct the frequency shift (FS) first frequency and second frequency.
Accompanying drawing summary
Provide accompanying drawing and the embodiment of the present invention is described helping, and provide accompanying drawing only for explaining orally embodiment but not it is limited.
Figure 1A has explained orally one way transmitter-receiver system 100.
Figure 1B has explained orally bidirectional transmit-receive machine system 110.
Fig. 2 A has explained orally the closed-loop simulation CDR system 200 based on PLL.
Fig. 2 B has explained orally the closed-loop digital CDR system 210 based on PI.
Fig. 2 C has explained orally burst mode switch CDR system 220.
Fig. 3 has explained orally the burst mode CDR system 300 that comprises the frequency alignment loop configuring according to each exemplary embodiment.
Fig. 4 has explained orally the digital CDR system 400 based on PI that comprises the frequency alignment loop configuring according to each exemplary embodiment.
Fig. 5 has explained orally wherein can advantageously adopt the example wireless communications 500 of embodiment of the present disclosure.
Fig. 6 explains orally according to the flow chart of the operating process of configuration burst mode clock and data recovery (CDR) system of each exemplary embodiment.
Describe in detail
Each aspect of the present invention is disclosed in the following description for the specific embodiment of the invention and relevant accompanying drawing.Can design alternative embodiment and can not depart from the scope of the present invention.In addition, in the present invention, well-known element will not be described in detail and maybe will be removed in order to avoid fall into oblivion correlative detail of the present invention.
Wording " exemplary " is in this article for representing " as example, example or explanation ".Any embodiment that is described as " exemplary " herein must not be interpreted as being better than or surpassing other embodiment.Equally, term " embodiments of the invention " do not require that all embodiment of the present invention comprise discussed feature, advantage or mode of operation.
Term used herein is only for the object of describing specific embodiment, and is not intended to limit embodiments of the invention.As used herein, " " of singulative, " certain " and " being somebody's turn to do " are intended to also comprise plural form, unless the context clearly indicates otherwise.Also will understand, term " comprises ", " having ", " comprising " and/or " containing " indicate the existence of stated feature, integer, step, operation, element and/or assembly, but do not get rid of existence or the interpolation of one or more other features, integer, step, operation, element, assembly and/or its group while using in this article.
In addition, many embodiment describe according to the action sequence that the element by for example computing equipment is carried out.To recognize, exercises described herein can for example, by special circuit (, application-specific integrated circuit (ASIC) (ASIC)), by the program command of just being carried out by one or more processors or by the two combination, carry out.In addition, these action sequences described herein can be considered to be embodied in completely in any type of computer-readable recording medium, be stored with once just carrying out the processor that makes to be associated is carried out to functional corresponding computer instruction set described herein.Therefore, various aspects of the present invention can be with several multi-form embodiments, and all these forms is all dropped in the scope of subject content required for protection by conception.In addition, for each embodiment described herein, the corresponding form of any this type of embodiment can for example be described to " being configured to carry out the logic of described action " herein.
Those skilled in the art will understand, and information and signal can be with any expressions the in various different technologies and skill.For example, the data that above description may be quoted from the whole text, instruction, order, information, signal, position (bit), code element and chip can be represented by voltage, electric current, electromagnetic wave, magnetic field or magnetic particle, light field or optical particle or its any combination.
In addition, those skilled in the art will understand, and various illustrative logical blocks, module, circuit and the algorithm steps in conjunction with embodiment disclosed herein, described can be implemented as electronic hardware, computer software or both combinations.For clearly explaining orally this interchangeability of hardware and software, various illustrative components, piece, module, circuit and step are done vague generalization with its functional form in the above and are described.This type of is functional is implemented as the design constraint that hardware or software depend on concrete application and puts on total system.Technical staff can realize by different modes described functional for every kind of application-specific, but such realize decision-making and should not be interpreted to and cause having departed from scope of the present invention.
Method, sequence and/or the algorithm in conjunction with embodiment disclosed herein, described can be embodied directly in hardware, in the software module of being carried out by processor or in the two combination and embody.Software module can reside in the storage medium of RAM memory, flash memory, ROM memory, eprom memory, eeprom memory, register, hard disk, removable dish, CD-ROM or any other form known in the art.Exemplary storage medium is coupled to processor so that this processor can be from/to this storage medium reading writing information.Alternatively, storage medium can be integrated into processor.
Each exemplary embodiment comprises for frequency shift (FS) being carried out automatically detecting cheaply and frequency shift (FS) being carried out accurately and compensated so that the system of error minimize automatically in Point-to-Point Data communication.Each embodiment can be integrated in the system comprising for serialiser-staticizer (SerDes) framework of the CDR of receiver, transceiver etc.
With reference to figure 3, explained orally the burst mode CDR system 300 configuring according to each exemplary embodiment.Before presenting the detailed description of the configuration of system 300, usually it is also noted that, compare with the conventional burst mode CDR system 200 of Fig. 2 C, system 300 comprises additional frequency alignment loop 360.More specifically, in system 220, between shared GVCO 224 and copy GVCO 224, do not exist loop to be connected (having open loop).On the other hand, in system 300, between MPLL piece 324 and copy GVCO 322, provide the frequency loop 360 that aligns.As below will further illustrated, frequency alignment loop 360 is eliminated or reduces in fact frequency shift (FS), such as Δ F as above and Δ F2.
Continuation is with reference to figure 3, and system 300 can be included in receiver 339, and receiver 339 can receive input data 340 from transmitter 338.Transmitter 338 can operate by the frequency F+ Δ F deriving from reference clock 336.First data 340 can be imported into equalizer 302.Equalizer 302 can be configured to make the HFS of data 340 more than low frequency part amplification, so that the low pass behavior of the communication channel of data 340 is carried in compensation between transmitter 338 and receiver 339.The output of equalizer 302 can be fed subsequently and enter marginal detector 306, and marginal detector 306 is configured to detect the rising edge/trailing edge of data transaction.As directed, the output of equalizer 302 is also fed and enters phase alignment piece 304, by this, enters phase alignment loop 350.
Phase alignment loop 350 can compensate and the phase place of the data input that outputs to sampler 310 of correcting balancer 302 and phase place that clock is input to sampler 310 between local phase deviation.Phase alignment loop 350 can be assisted with phase error information the operation of frequency alignment loop 360, so that correcting frequency shift, the Δ F2 causing such as the Δ F between transmitter 338 and receiver 339 and due to the interior local frequency mismatch generating of receiver 339.
Have to be noted that phase alignment loop 350 can be activated to arrange initial condition, and afterwards in stable state, phase alignment loop 350 can be disabled.As directed, phase alignment loop 350 at least comprises phase alignment piece 304, linear phase detector (PD) 308, modulus (A2D) transducer 318, digital loop filters (DLF) 312, integrator Σ 314 and control coding piece 316.In addition, phase alignment loop 350 also can comprise branch, and this branch comprises the frequency detector 320 that is fed to the branch road that enters DLF 312.DLF 312 can comprise adder sum-product intergrator as shown, and adder sum-product intergrator is well known in the art and will be not described in detail herein.In explained orally configuration, the various said modules of phase alignment loop 350 can form PLL the phase place of receiving data flow 322 is alignd with the vibration of copy GVCO 322 during initial condition or in the transition period such as channel switches.Afterwards, once reach phase alignment, phase alignment loop 350 can be unnecessary, and phase alignment loop 350 can be disabled or separate coupling from frequency alignment loop 360.
The loop 260 of steering frequency alignment now, wherein each assembly can be configured to compensating frequency deviation Δ F and Δ F2.The reference clock 334 of the receiver 339 operating with frequency F can be the local reference clock being embedded on the chip identical with system 300.This reference clock 334 can drive the piece that is regarded as 324, and piece 324 can comprise the main PLL (MPLL) that comprises GVCO.In other words, piece 324 can comprise logic similar in the frequency-tracking piece 229 to as directed system 220.As previously mentioned, the place that system 300 is significantly different from conventional system 200 is: the connection of going to copy GVCO 322 in system 300 enters the main PLL piece 324 with GVCO from the output loopback of copy GVCO 322 with feedback.
Thereby the main PLL 224 with GVCO can control the frequency of copy GVCO 322.Yet, due to frequency alignment loop 360, may be present in there is main PLL 324 and any frequency shift (FS) between copy GVCO 322 of GVCO can be by auto-compensation.In other words, frequency alignment loop 360 has been eliminated or has been reduced in fact frequency shift (FS) Δ F2.To the various pieces that other explains orally of frequency alignment loop 360 be described now.
Turn to now sigma-delta modulator (SDM) 326, sigma-delta (Σ Δ) modulation relates to and converts high-resolution analog signal input the digital signal output of low resolution to and with binary logic this digital signal output of encoding.This conversion can use error have been fed back, and wherein can improve conversion by the difference of input and output signal.The output of encoded digital signal can thereby provide Frequency Dividing Factor (being similar to the frequency divider 225 of system 220) for the PLL of piece 324.Going to the analog signal input of SDM 326 can obtain from adder 328, and it is combined that adder 328 can arrange control 342 by the output of low pass filter LPF 330 and foreign frequency.Therefore will notice, SDM 326 can be the piece being pre-existing in conventional receiver architecture, and in each exemplary embodiment, comprises the fringe cost by can not cause configuration-system 300 time of SDM 326 as shown.
With reference now to low pass filter LPF 330,, the frequency range that LPF 330 can be configured to that frequency is alignd in loop 360 is limited to less frequency band.Threshold value piece 332 can optionally be coupled to LPF 330.Threshold value piece 332 can limit the minimum frequency offset Δ F being compensated.In other words, threshold value piece 332 can define Tolerance level, so that can be left in the basket lower than the frequency offseting value of predetermined threshold, and only will be by auto-compensation in frequency is alignd loop 360 over the frequency offseting value of predetermined threshold.Control is that so that if predetermined threshold is set to " zero ", threshold value piece 332 is got rid of effectively by controlling predetermined threshold to a kind of mode that can optionally include in of threshold value piece 332.Frequency alignment loop 360 can complete in as directed input of going to threshold value piece 332 by deriving from DLF 312.Notice again, the logic module that LPF 330 and threshold value piece 332 are also pre-existing in conventional receiver architecture, and therefore come in a manner described configuration-system 300 can not cause fringe cost.In other words, by frequency align each exemplary embodiments of loop 360 configuration can only relate to reconfigure in the manner described above or line is pre-existing in again logical block to reduce or eliminate the minimal-overhead that frequency shift (FS) is associated.
Therefore, the combined effect of above-mentioned phase alignment loop 350 and frequency alignment loop 360 is compensation and eliminates the frequency shift (FS) Δ F of two types and the Δ F2 that is illustrated as hindering conventional CDR system 200,210 and 220.Described each embodiment can be configured to during the calibration phase of system 300 and during normal manipulation mode tuning various and relevant frequency of oscillation is set by just suitable.
With reference now to Fig. 4,, explained orally another exemplary embodiment with frequency alignment loop as above of configuration in the digital CDR system 400 based on PI.To recognize, and can add the conventional digital CDR system based on PI (such as the system 210 of Fig. 2 B) to by loop 460 that frequency is alignd and carry out configuration-system 400.As directed, system 400 can be embedded in the transceiver or main frame 439 operating by the frequency F deriving from reference clock 434.Transmitter or any equipment 438 that can operate from the reference frequency F+ Δ F by deriving from reference clock 436 receive data 440.In addition, system 400 also can be configured to eliminate or reduce in fact any frequency shift (FS) relevant with the data 441 of using multiplexer 378 transmission in the reverse direction from main frame 439 to equipment 438 with driver 380, thereby expanded technology herein and do not lose the versatility to any intercommunication system.
Usually, can, according to as carried out the similar mode of configuration-system 300 with reference to the loop 260 that aligns by interpolation frequency from conventional system 220 above, by loop 460 that frequency is alignd, add conventional system 210 to and carry out configuration-system 400.More specifically, system 400 can comprise phase alignment loop 450 and frequency alignment loop 460.
Phase alignment loop 450 can be derived input from receiving the equalizer 402 of data 440.The output of equalizer 402 can be passed through sampler x8474, samples the data flow output selectivity that sampler x8474 can generate equalizer 474.The output of sampler x8474 could be passed! ! PD and withdrawal device 476, DLF 412, integrator block Σ 414, control coding piece 416 and phase interpolator 472 are to complete phase alignment loop 450.The explanation providing in view of the loop 219 of previous reference system 210 and those of ordinary skills' ability, will omit the further details of phase alignment loop 450 for succinct object.
Come now frequency alignment loop 460, the output of DLF 412 is through threshold value piece 432 and low pass filter LPF 430.Can be in adder 428 output of LPF 430 and foreign frequency are arranged and control 442 combinedly, and the output of adder 428 can be fed and enters SDM 426 as analog input signal.The encoded digital signal of binary system of the output of SDM 426 can form the Frequency Dividing Factor of MPLL 424, and it can be system 400 frequency of oscillation is set.Again, align with the frequency of system 400 similitude of loop 460 of the frequency alignment loop 360 of considering previously discussed system 300, will avoid further instruction herein for succinct object.In system 220, MPLL 218 lacks closed loop with PI 217 and is connected, and frequency in system 400 alignment loop 460 provides such loop of getting back to MPLL 424 from phase interpolator 472, thereby eliminates or reduced in fact corresponding frequency shift (FS).
With reference to figure 5, the specific illustrative embodiment of the wireless device that comprises polycaryon processor of having described to configure according to each exemplary embodiment is also shown 500 block diagram by its general terrestrial reference.Equipment 500 comprises digital signal processor (DSP) 564, digital signal processor (DSP) 564 can comprise the receiver 339 of Fig. 3, wherein receiver 339 can receive input data 340 from being coupled to any equipment of DSP 564/assembly, as shown and below further describing.DSP 564 is coupled to memory 532.Fig. 5 also illustrates the display controller 526 that is coupled to DSP 564 and is coupled to display 528.Encoder/decoder (CODEC) 534 (for example audio frequency and/or voice CODEC) can be coupled to DSP 564.Also explained orally other assembly, such as wireless controller 540 (it can comprise modulator-demodulator).Loud speaker 536 and microphone 538 can be coupled to CODEC 534.Fig. 5 also indicates wireless controller 540 can be coupled to wireless antenna 542.In a specific embodiment, DSP 564, display controller 526, memory 532, CODEC 534 and wireless controller 540 are included in system in package or SOC (system on a chip) equipment 522.
In a particular embodiment, input equipment 530 and power supply 544 are coupled to SOC (system on a chip) equipment 522.In addition, in a particular embodiment, as explained orally in Fig. 5, display 528, input equipment 530, loud speaker 536, microphone 538, wireless antenna 542 and power supply 544 are in the outside of SOC (system on a chip) equipment 522.Yet the assembly of each the be coupled to SOC (system on a chip) equipment 522 in display 528, input equipment 530, loud speaker 536, microphone 538, wireless antenna 542 and power supply 544, such as interface or controller.
It should be noted that, although Fig. 5 has described Wireless Telecom Equipment, DSP 564 and memory 532 also can be integrated in the data cell or computer of Set Top Box, music player, video player, amusement unit, navigator, personal digital assistant (PDA), fixed position.Processor (for example DSP 564) also can be integrated in such equipment.
Correspondingly, embodiments of the invention can comprise the computer-readable medium of implementing for the method for the automatic detection of CDR system and correcting frequency shift.Therefore, the present invention is not limited to explained orally example and anyly for the described functional means of execution contexts, is all included in an embodiment of the present invention.
In addition, will understand, each embodiment comprises for carrying out the whole bag of tricks of process disclosed herein, function and/or algorithm.For example, as Fig. 6 explains orally, an embodiment can comprise the method for a kind of configuration burst mode clock and data recovery (CDR) system, and the method comprises: for example, with first frequency (F+ Δ F), receive input data (for example 340)---frame 602; For example, for example, with second frequency (F) operation reference clock (334)---frame 604; Configuration comprises the main phase-locked loop (PLL) (for example 334) of the first gating voltage controlled oscillator (GVCO), it is the phase alignment with input data with the phase place with reference to clock, and phase error information and clock (334 outputs)---the frame 606 through recovering are provided; Configure the 2nd GVCO (for example 322), its by the clock control through recovering for example, so that input data (using 310) are sampled---frame 608; And configuration frequency alignment loop (for example 360), it comprises that feedback path from the 2nd GVCO to main PLL is to proofread and correct the frequency shift (FS) first frequency and second frequency---frame 610 with phase error information.
Although above-mentioned, openly show illustrative embodiment of the present invention, it should be noted that and can make various replacings and change therein and can not depart from the scope of the present invention as claims definition.According to the function of the claim to a method of the embodiment of the present invention described herein, step and/or action, needn't carry out by any certain order.In addition, although key element of the present invention may describe or advocate that right, plural number are also what to have suspected, are defined in odd number unless explicitly has been stated with odd number.
Claims (24)
1. the clock and data recovery of burst mode (CDR) system, comprising:
The input data that receive with first frequency;
Reference clock with second frequency operation;
The main phase-locked loop (PLL) that comprises the first gating voltage controlled oscillator (GVCO), in order to by the phase alignment of the phase place of described reference clock and described input data and provide phase error information and clock through recovering;
The 2nd GVCO, by the described clock control through recovering with to described sampling input data; And
Comprise the frequency alignment loop from described the 2nd GVCO to the feedback path of described main PLL, be configured to proofread and correct the frequency shift (FS) between described first frequency and described second frequency with described phase error information.
2. the CDR system of burst mode as claimed in claim 1, is characterized in that, described feedback path comprises:
Be coupled to sampler and the linear phase detector of the output of described the 2nd GVCO;
Be coupled to the analog to digital converter of the output of described linear phase detector;
Be coupled to the digital loop filters of the output of described analog to digital converter;
Be coupled to the threshold value piece of the output of described digital loop filters;
Be coupled to the low pass filter of the output of described threshold value piece;
Be coupled to first input of adder of the output of described low pass filter, and the second input that is coupled to the described adder that foreign frequency controls; And
Be coupled to the delta-sigma modulator of the output of described adder, the output of wherein said delta-sigma modulator is coupled to described main PLL.
3. the CDR system of burst mode as claimed in claim 1, is characterized in that, further comprises phase alignment loop, and in order to by the phase alignment of the phase place of the output of described the 2nd GVCO and described input data, described phase alignment loop comprises:
Be coupled to the phase alignment piece of described input data;
Be coupled to the linear phase detector of the output of described phase alignment piece and the output of described the 2nd GVCO;
Be coupled to the analog to digital converter of the output of described linear phase detector;
Be coupled to the digital loop filters of the output of described analog to digital converter;
Be coupled to the integrator of the output of described digital loop filters; And
Be coupled to the control coding piece of the output of described integrator, the output of wherein said control coding piece is coupled to described phase alignment piece.
4. the CDR system of burst mode as claimed in claim 3, is characterized in that, described input data are coupled to described phase alignment piece by equalizer.
5. the CDR system of burst mode as claimed in claim 4, is characterized in that, further comprises the marginal detector of the output that is coupled to described equalizer, and the output of wherein said marginal detector is coupled to described the 2nd GVCO.
6. the CDR system of burst mode as claimed in claim 1, is characterized in that, the CDR system of described burst mode is integrated in receiver, and wherein said input data are transmitted by transmitter.
7. the CDR system of burst mode as claimed in claim 1, is characterized in that, the CDR system of described burst mode is integrated in semiconductor element.
8. the CDR system of burst mode as claimed in claim 1, it is characterized in that, the CDR system of described burst mode is integrated in the equipment of selecting from comprise the group of the following: Set Top Box, music player, video player, amusement unit, navigator, communication equipment, personal digital assistant (PDA), the fixing data cell in position, and computer.
9. the digital dock based on phase interpolator (PI) and data are recovered (CDR) system, comprising:
The input data that receive with first frequency;
Reference clock with second frequency operation;
In order to by the main phase-locked loop (PLL) of the phase alignment of the phase place of described reference clock and described input data;
Be coupled to the phase interpolator of the output of described main PLL; And
The frequency alignment loop that comprises the feedback path from described phase interpolator to described main PLL, in order to proofread and correct the frequency shift (FS) between described first frequency and described second frequency.
10. the digital CDR system based on PI as claimed in claim 9, is characterized in that, described feedback path comprises:
Be coupled to the sampler of the output of described phase interpolator;
Be coupled to switching regulator phase detectors and the withdrawal device of the output of described sampler;
Be coupled to the filter of the output of described switching regulator phase detectors and withdrawal device;
Be coupled to the threshold value piece of the output of described filter;
Be coupled to the low pass filter of the output of described threshold value piece;
Be coupled to first input of adder of the output of described low pass filter, and the second input that is coupled to the described adder that foreign frequency controls; And
Be coupled to the delta-sigma modulator of the output of described adder, the output of wherein said delta-sigma modulator is coupled to described main PLL.
The 11. digital CDR systems based on PI as claimed in claim 10, is characterized in that, further comprise the equalizer that is coupled to described input data, the output of wherein said equalizer is coupled to described sampler.
The CDR system of 12. burst modes as claimed in claim 9, is characterized in that, the CDR system of described burst mode is integrated in receiver, and wherein said input data are transmitted by transmitter.
The CDR system of 13. burst modes as claimed in claim 9, is characterized in that, the CDR system of described burst mode is integrated in semiconductor element.
The CDR system of 14. burst modes as claimed in claim 9, it is characterized in that, the CDR system of described burst mode is integrated in the equipment of selecting from comprise the group of the following: Set Top Box, music player, video player, amusement unit, navigator, communication equipment, personal digital assistant (PDA), the fixing data cell in position, and computer.
15. 1 kinds of clock and data recoveries (CDR) system, comprising:
The input data that receive with first frequency;
Reference clock with second frequency operation;
Device for detection of the phase error information between described input data and described reference clock;
Use detected phase error information to detect the device of the frequency shift (FS) between described first frequency and described second frequency; And
For eliminating the device of described frequency shift (FS).
16. 1 kinds of methods of carrying out clock and data recovery at receiver place, described method comprises:
With first frequency, from transmitter, receive input data;
Reference clock based on integrated in described receiver operates described receiver with second frequency;
Detect the phase error information between described input data and described reference clock;
With detected phase error information, detect the frequency shift (FS) between described first frequency and described second frequency; And
Eliminate described frequency shift (FS) so that described first frequency and described second frequency are synchronous.
17. 1 kinds of methods that configure clock and data recovery (CDR) system of burst mode, described method comprises:
With first frequency, receive input data;
With second frequency operation reference clock;
The main phase-locked loop (PLL) that configuration comprises the first gating voltage controlled oscillator (GVCO) is with by the phase alignment of the phase place of described reference clock and described input data and provide phase error information and through the clock of recovery;
Configuration by the 2nd GVCO of the described clock control through recovering with to described sampling input data; And
Configure the frequency comprising from described the 2nd GVCO to the feedback path of described main PLL and align loop so that proofread and correct the frequency shift (FS) described first frequency and described second frequency with described phase error information.
18. methods as claimed in claim 17, is characterized in that, form described feedback path and comprise:
Sampler is coupled to the output of described the 2nd GVCO;
Digital loop filters is coupled to the output of described sampler;
Threshold value piece is coupled to the output of described digital loop filters;
Low pass filter is coupled to the output of described threshold value piece;
The first input of adder is coupled to the output of described low pass filter, and the second input of described adder is coupled to foreign frequency control;
Sigma-delta modulator is coupled to the output of described adder; And
The output of described sigma-delta modulator is coupled to described main PLL.
19. methods as claimed in claim 17, is characterized in that, further comprise that configuration phase alignment loop with by the phase alignment of the phase place of the output of described the 2nd GVCO and described input data, wherein configures described phase alignment loop and comprises:
Phase alignment piece is coupled to described input data;
Linear phase detector is coupled to the output of described phase alignment piece and the output of described the 2nd GVCO;
Analog to digital converter is coupled to the output of described linear phase detector;
Digital loop filters is coupled to the output of described analog to digital converter;
Integrator is coupled to the output of described digital loop filters;
Control coding piece is coupled to the output of described integrator; And
The output of described control coding piece is coupled to described phase alignment piece.
20. methods as claimed in claim 19, is characterized in that, further comprise by equalizer described input data coupling to described phase alignment piece.
21. methods as claimed in claim 20, is characterized in that, further comprise:
Marginal detector is coupled to the output of described equalizer, and
The output of described marginal detector is coupled to described the 2nd GVCO.
22. 1 kinds of methods that the clock and data recovery based on phase interpolator (PI) (CDR) system is configured, described method comprises:
With first frequency, receive input data;
With second frequency operation reference clock;
Configure main phase-locked loop (PLL) with by the phase alignment of the phase place of described reference clock and described input data;
Phase interpolator is coupled to the output of described main PLL; And
Configuration comprises that the frequency alignment loop of the feedback path from described phase interpolator to described main PLL is to proofread and correct the frequency shift (FS) described first frequency and described second frequency.
23. methods as claimed in claim 22, is characterized in that, form described feedback path and comprise:
Sampler is coupled to the output of described phase interpolator;
Switching regulator phase detectors and withdrawal device are coupled to the output of described sampler;
By the filter coupled output to described switching regulator phase detectors and withdrawal device;
Threshold value piece is coupled to the output of described filter;
Low pass filter is coupled to the output of described threshold value piece;
The first input of adder is coupled to the output of described low pass filter, and the second input of described adder is coupled to foreign frequency control;
Sigma-delta modulator is coupled to the output of described adder; And
The output of described sigma-delta modulator is coupled to described main PLL.
24. methods as claimed in claim 23, is characterized in that, further comprise:
The input of equalizer is coupled to described input data; And
The output of described equalizer is coupled to described sampler.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/401,020 US9077349B2 (en) | 2012-02-21 | 2012-02-21 | Automatic detection and compensation of frequency offset in point-to-point communication |
| US13/401,020 | 2012-02-21 | ||
| PCT/US2013/026923 WO2013126440A2 (en) | 2012-02-21 | 2013-02-20 | Automatic detection and compensation of frequency offset in point-to-point communication |
Publications (1)
| Publication Number | Publication Date |
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| CN104126283A true CN104126283A (en) | 2014-10-29 |
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| CN201380010030.4A Pending CN104126283A (en) | 2012-02-21 | 2013-02-20 | Automatic detection and compensation of frequency offset in point-point communication |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9077349B2 (en) |
| EP (1) | EP2817914A2 (en) |
| JP (1) | JP2015513831A (en) |
| KR (1) | KR20140126388A (en) |
| CN (1) | CN104126283A (en) |
| TW (1) | TW201338427A (en) |
| WO (1) | WO2013126440A2 (en) |
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|---|---|---|---|---|
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Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013044249A1 (en) * | 2011-09-22 | 2013-03-28 | Aviat Networks, Inc. | Systems and methods for synchronization of clock signals |
| US20130216003A1 (en) * | 2012-02-16 | 2013-08-22 | Qualcomm Incorporated | RESETTABLE VOLTAGE CONTROLLED OSCILLATORS (VCOs) FOR CLOCK AND DATA RECOVERY (CDR) CIRCUITS, AND RELATED SYSTEMS AND METHODS |
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| US9992049B1 (en) * | 2016-06-17 | 2018-06-05 | Xilinx, Inc. | Numerically controlled oscillator for fractional burst clock data recovery applications |
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| US11349485B2 (en) | 2019-01-28 | 2022-05-31 | Mediatek Inc. | Clock and data recovery and associated signal processing method |
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Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3133885B2 (en) | 1993-12-24 | 2001-02-13 | 富士通株式会社 | Signal processing device having PLL circuit |
| KR100603180B1 (en) * | 2004-08-06 | 2006-07-20 | 학교법인 포항공과대학교 | A CMOS Burst-Mode Clock Data Recovery Circuit using Frequency Tracking Scheme |
| JP4657662B2 (en) * | 2004-09-10 | 2011-03-23 | ルネサスエレクトロニクス株式会社 | Clock and data recovery circuit |
| US20060083343A1 (en) * | 2004-10-19 | 2006-04-20 | Kawasaki Microelectronics, Inc. | Clock generation using phase interpolators |
| TWI242929B (en) | 2004-12-01 | 2005-11-01 | Ind Tech Res Inst | Clock and data recovery apparatus and method thereof |
| TWI277302B (en) * | 2004-12-28 | 2007-03-21 | Ind Tech Res Inst | Clock and data recovery circuit |
| US7512203B2 (en) | 2005-03-30 | 2009-03-31 | Silicon Laboratories Inc. | Data cleaning with an asynchronous reference clock |
| US7542533B2 (en) * | 2005-07-07 | 2009-06-02 | Agere Systems Inc. | Apparatus and method for calibrating the frequency of a clock and data recovery circuit |
| JP4971861B2 (en) * | 2007-04-13 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | Clock and data recovery circuit |
| US8228126B2 (en) * | 2007-04-19 | 2012-07-24 | Mediatek Inc. | Multi-band burst-mode clock and data recovery circuit |
| US7929654B2 (en) * | 2007-08-30 | 2011-04-19 | Zenko Technologies, Inc. | Data sampling circuit and method for clock and data recovery |
| US8509371B2 (en) * | 2009-09-29 | 2013-08-13 | Analog Devices, Inc. | Continuous-rate clock recovery circuit |
| JP2012049863A (en) * | 2010-08-27 | 2012-03-08 | Renesas Electronics Corp | Semiconductor device |
-
2012
- 2012-02-21 US US13/401,020 patent/US9077349B2/en active Active
-
2013
- 2013-02-20 CN CN201380010030.4A patent/CN104126283A/en active Pending
- 2013-02-20 WO PCT/US2013/026923 patent/WO2013126440A2/en active Application Filing
- 2013-02-20 EP EP13708306.9A patent/EP2817914A2/en not_active Withdrawn
- 2013-02-20 JP JP2014557877A patent/JP2015513831A/en active Pending
- 2013-02-20 KR KR1020147026110A patent/KR20140126388A/en not_active Application Discontinuation
- 2013-02-21 TW TW102106069A patent/TW201338427A/en unknown
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201338427A (en) | 2013-09-16 |
| US20130216014A1 (en) | 2013-08-22 |
| US9077349B2 (en) | 2015-07-07 |
| KR20140126388A (en) | 2014-10-30 |
| JP2015513831A (en) | 2015-05-14 |
| EP2817914A2 (en) | 2014-12-31 |
| WO2013126440A3 (en) | 2013-10-31 |
| WO2013126440A2 (en) | 2013-08-29 |
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