JPH10233768A - Digital clock reproduction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely provide the clock of a frame period, which is equal to a transmission-side, by providing a non-signal area control circuit and controlling the non-signal area in accordance with the shift of a multi-phase clock at the time of control in a signal reception area. SOLUTION: A non-signal area control circuit samples a clock phase selection signal at every clock and obtains a difference with a previous sampling result at the output terminal 215 of a subtractor 202. Differential information of the terminal 215 is counted in a counting circuit 203. Thus, information to which direction and how much clock phases are shifted in the signal reception area is obtained in an output terminal 216. The positive/negative judgment of the control direction for clock phase selection is executed by the highest digit in the output terminal 217 of the control information operation circuit 204. Control pulses are outputted from output terminals A4 and A5 so that the clock phase is advanced when it is positive, and the clock phase is delayed when it is negative. Clock phase selection information is controlled by the control pulse of the output terminals A4 and A5 in the non-signal area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital clock recovery circuit and, more particularly, to a PLL (Phase Lock Loop) for recovering a clock signal correctly synchronized with a signal intermittently in a burst.

[0002]

2. Description of the Related Art In a digital device such as a computer or a digital communication device, a clock (or a clock pulse) is used as a reference signal for correctly operating these circuits.
Is required. In particular, in a communication device or a transmission device that receives a burst signal, in a device configuration in which a separate oscillator having a frequency deviation between a transmission device and a reception device is mounted, a transmission / reception device of a system that transmits and receives a burst signal by ping-pong transmission or the like. A clock is required for frequency reproduction.

In the receiving apparatus of such a system, clock phase selection control is performed in a no-signal area based on clock phase selection control information in a signal receiving area, and a clock frequency is reproduced. As a prior art in such a technical field, Japanese Patent Application No.
JP-A-41132 and JP-A-63-240216.

In the former digital PLL circuit, FIG.
As shown in FIG.
Selection circuit (selector) 6 for selecting N-phase clocks 2-1 to 2-N shifted by degrees / N (N is an integer of 2 or more)
And a data sampling circuit 3 for sampling a received signal by each of the N-phase clocks; a second phase to an N-th phase clock; A rearranging circuit that rearranges the N sampling circuit outputs and rearranges them as the first to N-th sampling signals, latches the rearranged sampling signals with a selection clock, and detects edges based on the levels of adjacent phases. And an arithmetic circuit 5 for calculating the average of the edge position information output from the edge position detecting circuit 4 every clock cycle.

A digital PLL circuit having such a configuration detects an edge of an input signal and calculates an average value thereof, thereby selecting a clock having a phase most suitable for the input signal as clock phase selection information. Is reproduced.

The latter digital phase-locked loop is a PL
It has a phase comparison circuit that compares the phases of the L input clock and the PLL output clock, an integration circuit that digitally integrates the output of the phase comparison circuit, and a frequency division circuit that inserts and removes a clock with the output of the integration circuit. A digital PL comprising a phase control circuit and a frequency divider circuit for further dividing the output clock of the phase control circuit to generate a PLL output clock
In L, the circuit comprises an input disconnection detection circuit for detecting the disappearance of the PLL input clock, a counter for counting the PLL output clock, and a memory for storing the output of the integration circuit using the count value of this counter as an address.

This digital phase locked loop circuit operates the phase control circuit by the output of the integration circuit and writes the output of the integration circuit to the memory when the input disconnection information is not output from the input group detection circuit. When the input disconnection information is being output, the phase control circuit is operated by the information read from the memory, and operates so as to control the frequency when the PLL input clock is disconnected.

[0008]

In the case of the latter prior art described above, a digital PL that performs clock control in a no-signal area is used.
The L circuit writes control information to the memory, and controls the clock in the non-signal area using the control information read from the memory. Therefore, in this method, in order to increase the frequency accuracy in the no-signal region, high-precision control information is required, and a large-capacity bit memory is required.

For example, as shown in (D) of the time chart of FIG. 5, when a burst signal having a constant frame period is received and it is intended to be dependent on the received signal, the signal reception area has 10,000 bits. , The no-signal area is also 1
If there are 0000 bits, 10,
It is assumed that 000 bits are written in the memory and the non-signal area is controlled based on the information. When an input signal that requires control of the clock three times with 2,000 bits is received, two cases are performed, one in which control is performed twice with 1,000 bits and the other in which one control is performed with 1,000 bits. Two cases occur. As a result, there has been a problem that the frequency accuracy of the reproduced clock in the no-signal region deteriorates.

On the other hand, in the former case, a multi-phase clock whose phase is shifted by 360 degrees / N is selected so as to be optimal for the received signal, and thus no control is performed in the no-signal region. In this method, when a burst signal with a steady frame period is received and the signal is to be subordinated, the non-signal area is controlled only by the control information of the signal reception area immediately before the signal is interrupted. If the clock frequency of the receiving clock is not equal to the clock frequency of the receiving side, there is a problem that an accurate clock cannot be obtained over a long burst period.

Therefore, an object of the present invention is to provide a burst signal having a frame period, in which a clock phase selection control in a no-signal area is performed based on clock phase selection information in a signal reception area, so that a burst signal having a frame period exactly equal to that on the transmission side is obtained. An object of the present invention is to provide a digital clock reproducing circuit capable of obtaining a clock having a frame period.

[0012]

In order to solve the above-mentioned problems, a digital clock recovery circuit according to the present invention is a digital clock recovery circuit using a multi-phase clock selected by a clock selector.
A digital clock recovery circuit that includes an L circuit and recovers a clock in a signal receiving area and a no-signal area;
A non-signal area control circuit that operates with the output of the L circuit is provided, and during control in the signal reception area, how many phases of the multiphase clock are shifted in either the positive or negative direction, and in the non-signal area, Perform control.

Here, the non-signal area control circuit includes a counting circuit and a control information calculation circuit, and the control information calculation circuit includes an adder, a D-type flip-flop circuit, and a frequency divider. Further, the no-signal area control circuit obtains the current and previous control information by weighted averaging.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the digital clock recovery circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the entirety of a preferred embodiment of a digital clock recovery circuit according to the present invention. 2 and 3 are detailed block diagrams of main parts of the digital clock recovery circuit of FIG. 1, respectively. FIG. 5 is a time chart for explaining the operation of the digital clock reproducing circuit of the present invention shown in FIG. 1 and the conventional circuit shown in FIG.

First, the configuration of the digital clock recovery circuit of the present invention will be described with reference to FIG. The digital clock recovery circuit includes an input terminal 11 to which an input signal to be received is applied, input clock terminals 12-1 to 12-N to which an N-phase input clock is applied, a no-signal area indication terminal 18, and an output clock terminal 20. including.

Input terminal 11 and polyphase input clock terminal 12
The data sampling circuit 13 is connected to -1 to 12-N. The data sampling circuit 13 receives a multi-phase clock and also receives an output of a clock selector (selection circuit) 16 for selecting an optimum clock.

The output of the data sampling circuit 13 is input to B1 of the edge counter 15 via the edge detection circuit 14. The output B5 of the edge counter 15 is input to the A1 terminal of the no-signal area control circuit 17. The output B5 of the edge counter 15 is further input to the clock selector 16 and the data sampling circuit 13. The output of the clock selector 16 not only outputs the output clock to the output clock terminal 20 but also outputs the data sampling circuit 1.
3, also input to the input B2 of the edge counter 15 and the input A3 of the no-signal area control circuit 17. The outputs A4 and A5 of the non-signal area control circuit 17 are the edge counter 1 respectively.
5 are input to inputs B3 and B4. Further, the terminal A2 of the no-signal area control circuit 17 is connected to the no-signal area indication terminal 1 described above.
8 is connected.

As can be understood from FIG. 1, the digital clock recovery circuit of the present invention comprises a conventional digital PLL circuit substantially as shown in FIG. 4 and a non-signal area control circuit 17 whose detailed block diagram is shown in FIG. Composed of

As shown in FIG. 2, a preferred example of the no-signal area control circuit 17 used in the digital clock recovery circuit of FIG. 1 has input terminals A1 to A3 and output terminals A4 and A5. In the D-type flip-flop 201, the input terminal D receives the output B5 of the edge counter 15 from the input terminal A1, and the clock terminal CK receives the output clock of the clock selector 16 via the input terminal A3. The Q output and the input signal of the D-type flip-flop 201 are input to an adder 203-1 forming a counting circuit 203 via a subtractor 202. The counting circuit 203 includes a gate 203-2 and another D-type flip-flop 20 in addition to the adder 203-1.
3-3.

The Q output of the D flip-flop 203-3, which is the output of the counting circuit 203, is input to the adder 204-1. The adder 204-1 constitutes the control information calculation circuit 204 together with the D-type flip-flop 204-2 and the frequency divider 204-3. The input terminals A2 and A3 are input to the rising edge detector 207, the input A2 is input to one input terminal of the gate 203-2 of the counting circuit 203, and the input A3 is the clock CK of the D-type flip-flop 203-3. Is input to Also, a rising edge detector 2
The output of 07 is input to the D input terminal of the D-type flip-flop 208 and also to the clock CK terminal of the D-type flip-flop 204-2 forming the control information operation circuit 204.

Output terminal 217 of control information calculation circuit 204
Is input directly to the selector 210 and to the selector 210 via the two's complement circuit 209. The output of the selector 210 is supplied to a counter 21 via a division circuit 211.
2 A input terminal. L of this counter 212
D-type flip-flops 20 are connected to the D, EN and CK terminals, respectively.
8, the clock of the input terminal A2 and the clock of the input terminal A3 are input. Output signals are output to output terminals A4 and A5 via gates 213 and 214 that receive the CR output of the counter 212 and the output of the control information calculation circuit 204, respectively.

The no-signal area control circuit 17 shown in FIG. 1 samples the clock phase selection signal output from the edge counter 15 at the input terminal A1 for each clock, and compares the difference from the previous sampling result with the subtractor 202. Output terminal 21
Get 5 The difference information of this terminal 215 is counted by the counting circuit 203.
Count with. As a result, information indicating in which direction (positive / negative) and how many clock phases the clock phase has moved in the signal receiving area is obtained at the output terminal 216. Output terminal 2 of this counting circuit 203
The count value of 16 is initialized to 0 at the head (first) of the signal receiving area.

Next, the control information calculation circuit 204 calculates a weighted average of the count value of the output terminal 216 of the counting circuit 203 for each frame. The weighted average is obtained by adding the calculation result at the output terminal 217 of the control information calculation circuit 204 in the previous frame and the count value at the output terminal 216 of the counting circuit 203 by an adder 204-1, and dividing the added value by two (と す る).

Here, the count value of the counting circuit 203 of the current frame is y (0), the count value of the previous frame is y (1), and the count values of the previous frame are y (2) and y (3). Then, the calculation result at the output terminal 217 of the current frame is a value obtained by cumulatively adding y (n) / 2 (n + 1) from n to zero to infinity.

The output terminal 2 of the control information calculation circuit 204
When the operation result at 17 is negative, a 2's complement is taken. When the operation result is positive, the number of bits in the no-signal area is divided by the division circuit 211 as it is. The counter 212 that outputs a control pulse in the cycle of the division result is operated. The control direction of the clock phase selection depends on the control information arithmetic circuit 2
A positive / negative determination is made based on the most significant digit (MSB) at the output terminal 217 of the terminal 04. When the signal is positive, the clock phase is advanced, and when the signal is negative, a control pulse is output from the output terminals A4 and A5 so as to control the clock phase to be delayed.

In the no-signal area, the output terminal A described above is used.
4, the edge counter 15 of FIG.
And controls the clock phase selection information.

As shown in FIG. 3, the edge counter 15 used in the digital clock recovery circuit shown in FIG. 1 includes adders 301 and 302 receiving inputs from input terminals B1 and B3, respectively.
The subtractor 303 subtracts the output of the adder 302 from the input terminal B4, and the storage unit 304 receives the output of the subtracter 303 and the input of the input terminal B2. Storage unit 304
Is output to the output terminal B5 and to one input terminal of the input adder 301.

FIG. 5 is a time chart showing the operation of the above-described digital clock reproducing circuit of the present invention shown in FIG. 1 and the conventional circuit shown in FIG. (A) shows a received (input) signal,
10,000-bit signal receiving area (shaded area), 1 bit
This shows a case in which 000 non-signal areas (blank areas) are alternately repeated in a burst form. (B) shows the clock control of the signal receiving area. (C) shows a memory write cycle.
(D) shows a reproduced clock of the conventional circuit of FIG. 10,
An area that follows a 000-bit received signal;
As described above, there is an area where clock control is performed once per bit or twice per 1,000 bits.
(E) shows a recovered clock by the digital clock recovery circuit of the present invention, which follows the received signal in the signal receiving area of 10,000 bits, and the 10,000 bits of the no signal area are the average of the clock control information up to now. Indicates that the area is for clock control.

The preferred embodiment of the digital clock recovery circuit of the present invention has been described above. However, the present invention is not limited to the specific embodiment, and various modifications can be made in accordance with the specific application. Will be readily understood by those skilled in the art. Therefore, the present invention includes such modifications.

[0031]

As described above, according to the digital clock recovery circuit of the present invention, even if the signal reception area and the non-signal area are burst-like digital data, the signal reception area can be controlled. Since information is counted by the counter, a large-capacity memory is not required. In addition, since the weighted average of the control information is calculated for each frame to control the no-signal area, it is possible to minimize the influence of instantaneous fluctuations such as jitters, and to use a high-precision clock. Since it can be reproduced, the digital data transmission device has a practically remarkable effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a preferred embodiment of a digital clock recovery circuit according to the present invention.

FIG. 2 is a detailed configuration diagram of a no-signal area control circuit used in the digital clock recovery circuit of FIG. 1;

FIG. 3 is a detailed configuration diagram of an edge counter used in the digital clock recovery circuit of FIG. 1;

FIG. 4 is a block diagram of a conventional clock recovery circuit.

FIG. 5 is a time chart for explaining the operation of the clock recovery circuit of FIGS. 1 and 4;

[Explanation of symbols]

 13, 14, 15, 16 PLL circuit 12-1 to 12-N polyphase input clock 17 no-signal area control circuit 203 counting circuit 204 control information operation circuit 204-1 adder 204-2 D-type flip-flop circuit 204-3 Divider

Claims (4)

[Claims] 1. A digital clock recovery circuit that includes a PLL circuit that uses a multi-phase clock selected by a clock selector and that recovers a clock in a signal receiving area and a no-signal area. A digital control device comprising: an area control circuit, which determines how many phases of the multi-phase clock have been moved in the positive or negative direction during control in the signal reception area, and performs control in the non-signal area. Clock recovery circuit. 2. The digital clock reproducing circuit according to claim 1, wherein said non-signal area control circuit includes a counting circuit and a control information calculation circuit. 3. The digital clock recovery circuit according to claim 21, wherein said control information operation circuit includes an adder, a D-type flip-flop circuit and a frequency divider. 4. The digital clock reproducing circuit according to claim 1, wherein said non-signal area control circuit obtains the current and previous control information by weighted averaging.