CN104124155A - Manufacturing method of indium phosphide hetero-junction crystal tube side wall protection emitting electrode - Google Patents
Manufacturing method of indium phosphide hetero-junction crystal tube side wall protection emitting electrode Download PDFInfo
- Publication number
- CN104124155A CN104124155A CN201410309065.4A CN201410309065A CN104124155A CN 104124155 A CN104124155 A CN 104124155A CN 201410309065 A CN201410309065 A CN 201410309065A CN 104124155 A CN104124155 A CN 104124155A
- Authority
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- China
- Prior art keywords
- emitter
- side wall
- indium phosphide
- metal
- etching
- Prior art date
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- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000013078 crystal Substances 0.000 title abstract 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000005260 corrosion Methods 0.000 claims abstract description 8
- 230000007797 corrosion Effects 0.000 claims abstract description 8
- 239000007788 liquid Substances 0.000 claims abstract description 5
- 238000001039 wet etching Methods 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- CLCPDSJUXHDRGX-UHFFFAOYSA-N 6-(1,3-dihydroxyisobutyl)thymine Chemical compound CC1=C(CC(CO)CO)NC(=O)NC1=O CLCPDSJUXHDRGX-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
Abstract
The invention discloses a manufacturing method of an indium phosphide hetero-junction crystal tube side wall protection emitting electrode. The method comprises the following steps: manufacturing an emitting electrode metal bar by using an evaporative stripping method; depositing an SiN film; etching to form an SiN side wall; corroding an emitting area material by using a wet method; manufacturing a base electrode contact metal by means of self-aligning to finish manufacturing of the indium phosphide hetero-junction crystal tube side wall protection emitting electrode. The manufacturing method has the advantages that the SiN side wall is used for providing chemical protection for the emitting electrode metal, thereby preventing corrosive liquid from corroding the emitting electrode metal during wet-method corrosion of the emitting area material; the emitting electrode is fixed mechanically, thereby preventing the bar from falling; the emitting electrode and a base electrode are electrically insulated by using a self-aligning process, thereby increasing and improving the yield and reliability of a finished indium phosphide-based hetero-junction crystal tube side emitting electrode.
Description
Technical field
What the present invention relates to is a kind of manufacture method of heterojunction of indium phosphide transistor side wall protection emitter, belongs to semiconductor transistor technology field.
Background technology
Bipolar transistor with heterojunction of indium phosphide (InP HBT) has very excellent high frequency characteristics, and in ultrahigh speed Digital Analog Hybrid Circuits, submillimeter wave circuit and optoelectronic IC, tool has been widely used.InP HBT is divided into indium phosphide single heterojunction bipolar transistor (InP SHBT) and indium phosphide double hetero bipolar transistor npn npn (InP DHBT) according to the difference of collector region material.The collector region of InP SHBT is indium gallium arsenic (InGaAs), and the collector region of InP DHBT is indium phosphide (InP).The relative InP SHBT of InP DHBT, have higher puncture voltage and better heat dissipation characteristics, so range of application is more wide, is the focus of research both at home and abroad at present and application.For InP HBT, high-frequency parameter mainly contains two, and the one, current gain cutoff frequencies (f
t); The 2nd, maximum frequency of oscillation (f
max).For making device high-frequency parameter be increased to γ doubly, emitter live width need foreshorten to original γ
-1/2doubly, for obtaining the better high frequency characteristics of HBT device, must further reduce emitter live width.Narrower emitter live width has proposed severe challenge to emitter rate of finished products, reliability.
At present conventional emitter preparation technology directly uses emitter metal as mask when corrosion or etching emitter region epitaxial material, emitter metal sidewall will inevitably be corroded or etching, when making sub-micron live width emitter, may cause emitter metal to rupture, peel off.In addition, be to improve bipolar transistor with heterojunction of indium phosphide high frequency characteristics, emitter region material thickness reduces and becomes conventional method for designing, yet thin emitter region easily causes emitter and base stage in base stage contacting metal self-registered technology to open circuit.Therefore, traditional for the method for making emitter when making InP HBT sub-micron emitter metal, there is certain shortcoming.
Summary of the invention
What the present invention proposed is a kind of manufacture method of heterojunction of indium phosphide transistor side wall protection emitter; its object is intended to overcome the emitter metal running in the preparation of the legacy transmission utmost point and comes off; and the base stage running in self-registered technology and the emitter problem such as open circuit; adopt SiN side wall to fix for emitter provides chemoproection, electricity isolation, machinery, improve indium phosphide heterojunction transistor emitter rate of finished products and reliability.
Technical solution of the present invention: the manufacture method of heterojunction of indium phosphide transistor side wall protection emitter, comprises the following steps:
1) on heterojunction of indium phosphide transistor epitaxial material, by evaporation stripping means or lithographic method, make emitter metal bar shaped;
2) at front wafer surface deposit ground floor SiN film, thickness range is 5 nanometers to 1 micron;
3) utilize etching apparatus, the SiN on etching emitter top and epitaxial material, leaves emitter metal sidewall SiN film, forms SiN side wall;
4) take emitter metal as etching mask, adopt wet etching to remove emitter region epitaxial material;
5) adopt Alignment Method to prepare base stage contacting metal, complete indium phosphide heterojunction transistor side wall protection emitter and make.
Advantage of the present invention: the feature of maximum of the present invention is to adopt SiN side wall to provide passivation protection for emitter metal, avoids corrosive liquid when wet etching or dry etching emitter region material to cause corrosion or etching to emitter metal; For emitter provides machinery fixing, avoid bar shaped to come off; For self-registered technology provides the isolation of the electricity between emitter and base stage, thereby improve indium phosphide heterojunction transistor emitter rate of finished products and reliability.
Accompanying drawing explanation
Fig. 1 makes emitter metal bar shaped device profile map afterwards.
Fig. 2 is the device profile map after deposit SiN film.
Fig. 3 has been the device profile map after SiN side wall.
Fig. 4 removes emitter region epitaxial material device profile map afterwards.
Fig. 5 makes base stage contacting metal device profile map afterwards by Alignment Method.
Embodiment
A manufacture method for heterojunction of indium phosphide transistor side wall protection emitter, comprises the following steps:
1) on heterojunction of indium phosphide transistor epitaxial material, by evaporation stripping means or lithographic method, make emitter metal bar shaped;
2) at front wafer surface deposit layer of sin film, thickness range is 5 nanometers to 1 micron;
3) utilize etching apparatus, the SiN on etching emitter top and epitaxial material, leaves emitter metal sidewall SiN film, forms layer of sin side wall;
4) take emitter metal as etching mask, adopt wet etching to remove emitter region epitaxial material;
5) adopt Alignment Method to prepare base stage contacting metal, complete indium phosphide heterojunction transistor side wall protection emitter and make.
The described layer of sin side wall of making after completing emitter metal bar shaped and making provides passivation protection for emitter metal, avoids corrosive liquid when wet etching or dry etching emitter region material to cause corrosion or etching to emitter metal; For emitter provides machinery fixing, avoid bar shaped to come off; For self-registered technology provides the isolation of the electricity between emitter and base stage.
Below in conjunction with accompanying drawing, further describe technical scheme of the present invention;
Concrete grammar is as follows:
1) on heterojunction of indium phosphide transistor epitaxial material, by evaporation stripping means or lithographic method, make bar shaped emitter metal, altitude range is 50 nanometers to 1 micron, and width range is 25 nanometers to 5 micron.As shown in Figure 1.
Described evaporation stripping means makes bar shaped emitter region cover without photoresist by photoetching, peripheral region has photoresist to cover, vaporizing emitter metal is peeled off the emitter metal on photoresist when finally removing photoresist simultaneously, leaves bar shaped emitter metal.
Described lithographic method makes bar shaped emitter region have photoresist to cover by photoetching, peripheral region covers without photoresist, be placed on etching in dry etching equipment, do not have photoresist overlay area emitter metal to be etched, there is photoresist overlay area intact, finally remove photoresist, leave bar shaped emitter metal.
2) at front wafer surface deposit layer of sin film, thickness range is 5 nanometers to 1 micron.As shown in Figure 2.
3) utilize etching apparatus, the SiN on etching emitter top and epitaxial material, leaves emitter metal sidewall SiN film, forms layer of sin side wall.As shown in Figure 3.
Described SiN side wall side parcel emitter metal, fitting with emitter region material in bottom, has fixed the relative position of emitter metal and emitter region material, and having embodied SiN side wall provides mechanical fixing effect for emitter metal.
4) take emitter metal as etching mask, adopt wet etching to remove emitter region epitaxial material.As shown in Figure 4.
Described wet etching is to take emitter metal as etching mask, adopts sour corrosion corrosion and removes emitter region epitaxial material.In this process, have the emitter metal surface of SiN side wall parcel can avoid directly contacting with acid etching solution, reduced the corrosion of corrosive liquid to emitter metal, having embodied SiN side wall provides chemoprotectant effect for emitter metal.
5) adopt Alignment Method to prepare base stage contacting metal, complete indium phosphide heterojunction transistor side wall protection emitter and make.As shown in Figure 5.
Described Alignment Method is: first make covering emitter by lithography, and the figure wider than emitter metal, graphics field is covered without photoresist, peripheral region has photoresist to cover, evaporation base stage contacting metal, when finally removing photoresist, the base stage contacting metal on photoresist is peeled off simultaneously, left the base stage contacting metal of emitter both sides and cover the base stage contacting metal on emitter.Because material width in wet etching course in emitter region is inevitable, shrink to some extent, the base stage contacting metal of emitter both sides does not contact with emitter region material; Because having SiN side wall, emitter metal skin provides dielectric layer, the base stage contacting metal of emitter both sides does not contact with emitter metal, therefore the base stage contacting metal of emitter both sides and the isolation of emitter electricity, has embodied the effect that SiN side wall provides the electricity between emitter and base stage to isolate for self-registered technology.
Claims (2)
1. heterojunction of indium phosphide transistor side wall is protected a manufacture method for emitter, it is characterized in that the method comprises the following steps:
1) on heterojunction of indium phosphide transistor epitaxial material, by evaporation stripping means or lithographic method, make emitter metal bar shaped;
2) at front wafer surface deposit layer of sin film, thickness range is 5 nanometers to 1 micron;
3) utilize etching apparatus, the SiN on etching emitter top and epitaxial material, leaves emitter metal sidewall SiN film, forms layer of sin side wall;
4) take emitter metal as etching mask, adopt wet etching to remove emitter region epitaxial material;
5) adopt Alignment Method to prepare base stage contacting metal, complete indium phosphide heterojunction transistor side wall protection emitter and make.
2. a kind of heterojunction of indium phosphide transistor side wall according to claim 1 is protected the manufacture method of emitter, it is characterized in that described after emitter metal bar shaped is made, make layer of sin side wall and providing passivation protection for emitter metal completing, avoid corrosive liquid when wet etching or dry etching emitter region material to cause corrosion or etching to emitter metal; For emitter provides machinery fixing, avoid bar shaped to come off; For self-registered technology provides the isolation of the electricity between emitter and base stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410309065.4A CN104124155A (en) | 2014-07-02 | 2014-07-02 | Manufacturing method of indium phosphide hetero-junction crystal tube side wall protection emitting electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410309065.4A CN104124155A (en) | 2014-07-02 | 2014-07-02 | Manufacturing method of indium phosphide hetero-junction crystal tube side wall protection emitting electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104124155A true CN104124155A (en) | 2014-10-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410309065.4A Pending CN104124155A (en) | 2014-07-02 | 2014-07-02 | Manufacturing method of indium phosphide hetero-junction crystal tube side wall protection emitting electrode |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107895696A (en) * | 2017-11-03 | 2018-04-10 | 厦门市三安集成电路有限公司 | A kind of high-precision HBT preparation technologies |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5344786A (en) * | 1990-08-31 | 1994-09-06 | Texas Instruments Incorporated | Method of fabricating self-aligned heterojunction bipolar transistors |
| US20060113634A1 (en) * | 2003-11-17 | 2006-06-01 | Shahriar Ahmed | Bipolar junction transistor with improved extrinsic base region and method of fabrication |
| CN102201339A (en) * | 2011-05-30 | 2011-09-28 | 中国电子科技集团公司第五十五研究所 | Method for reducing capacity of B-C junction of InP DHBT (Indium Phosphide Double Heterojunction Bipolar Transistor) |
| CN102244003A (en) * | 2011-06-20 | 2011-11-16 | 中国科学院微电子研究所 | Preparation method for side wall of InP HBT device |
| CN103137675A (en) * | 2011-11-23 | 2013-06-05 | 上海华虹Nec电子有限公司 | Germanium-silicon heterojunction bipolar transistor structure with high breakdown voltage and manufacture method thereof |
-
2014
- 2014-07-02 CN CN201410309065.4A patent/CN104124155A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5344786A (en) * | 1990-08-31 | 1994-09-06 | Texas Instruments Incorporated | Method of fabricating self-aligned heterojunction bipolar transistors |
| US20060113634A1 (en) * | 2003-11-17 | 2006-06-01 | Shahriar Ahmed | Bipolar junction transistor with improved extrinsic base region and method of fabrication |
| CN102201339A (en) * | 2011-05-30 | 2011-09-28 | 中国电子科技集团公司第五十五研究所 | Method for reducing capacity of B-C junction of InP DHBT (Indium Phosphide Double Heterojunction Bipolar Transistor) |
| CN102244003A (en) * | 2011-06-20 | 2011-11-16 | 中国科学院微电子研究所 | Preparation method for side wall of InP HBT device |
| CN103137675A (en) * | 2011-11-23 | 2013-06-05 | 上海华虹Nec电子有限公司 | Germanium-silicon heterojunction bipolar transistor structure with high breakdown voltage and manufacture method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107895696A (en) * | 2017-11-03 | 2018-04-10 | 厦门市三安集成电路有限公司 | A kind of high-precision HBT preparation technologies |
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Application publication date: 20141029 |