CN104124148B - Silicon chip etching method - Google Patents
Silicon chip etching method Download PDFInfo
- Publication number
- CN104124148B CN104124148B CN201310150615.8A CN201310150615A CN104124148B CN 104124148 B CN104124148 B CN 104124148B CN 201310150615 A CN201310150615 A CN 201310150615A CN 104124148 B CN104124148 B CN 104124148B
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- Prior art keywords
- gas
- etching
- silicon chip
- side wall
- hydrogen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000005530 etching Methods 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title claims abstract description 77
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 46
- 239000010703 silicon Substances 0.000 title claims abstract description 46
- 239000007789 gas Substances 0.000 claims abstract description 115
- 238000006243 chemical reaction Methods 0.000 claims abstract description 62
- 238000002161 passivation Methods 0.000 claims abstract description 35
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000001257 hydrogen Substances 0.000 claims abstract description 34
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 34
- 229910004014 SiF4 Inorganic materials 0.000 claims description 9
- 239000011261 inert gas Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- 229910003910 SiCl4 Inorganic materials 0.000 claims description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 6
- -1 oxonium ion Chemical class 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000002633 protecting effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
This hair, which is said, is related to a kind of silicon chip etching method, and for carrying out deep silicon etching technique to being positioned in reaction chamber the silicon chip on electrostatic chuck, this method comprises the following steps：Process gas is passed through into reaction chamber, process gas includes etching gas, side wall passivation gas and hydrogen-containing gas, and hydrogen-containing gas accounts for the ratio of process gas less than 50%, and the flow proportional of hydrogen-containing gas and etching gas is 1:10 to 1:2；Apply radio-frequency power to reaction chamber, technique and side wall passivation technology are performed etching to silicon chip to produce plasma.This method is beneficial to the balance for reaching etching reaction and side wall passivation reaction in stead state deep silicon etching techniques, so that the probability that pinhole patterns occurs in side wall is substantially reduced, pinhole quantity also says aobvious reduction.
Description
Technical field
This hair, which is said, is related to field of semiconductor processing and manufacturing, more specifically to a kind of silicon chip etching method.
Background technology
In field of semiconductor processing and manufacturing, through-silicon-via（Through silicon via, abbreviation TSV）Technology can
Make chip density that three-dimensional is stacked is maximum, the interconnection line between chip is most short, appearance and size is minimum, so as to produce
Structure is more complicated, performance is more powerful, more cost-efficient chip, so as to be applied widely.
Traditional TSV etching technics is the process of an etching technics and side wall protection technique alternately, i.e., first to lining
A bottom etching part, then carries out polymer deposits to carry out side wall protection in side wall, prevents that etching opening next time is excessive,
The etching and polymer deposits of next round are further continued for, so alternately, is removed until by etching stopping layer material（Part TSV
Etching stop layer is not set in etching technics）, reach substrate.It is the gas with etching reaction in the realization of concrete technology（For example
SF6）Gas used is protected with side wall（Usually C4F8）It is switched fast, to realize that etching reaction and polymer deposits are anti-
Should alternately.But very quick switching can not possibly be realized by etching and depositing due to the limitation of hardware, in traditional technique, from
And waveform occurs in the sidewall profile etched.
At present, it is stead-state deep silicon etching techniques using a kind of wider TSV etching technics, it can effectively be prevented
The appearance of wavy sidewalls pattern, it is mainly characterized in that etching reaction and side wall passivation reaction are carried out simultaneously, wherein etching reaction
Process gas used is SF6, side wall passivation reaction gas used is usually O2And SiF4, it carries out reaction formation with side wall
Sidewall passivation layer, with protective side wall pattern.
However, in some technique occasions, side wall passivation can not provide the side wall protecting effect of abundance, in etching reaction and
In the case that side wall passivation reaction can not reach balance, some apertures (pinhole) can be often formed on the wall of side, make sidewall profile
Say aobvious deterioration.And in deep silicon etching technique, especially stead-state techniques, due to etching reaction and side wall passivation reaction
Carry out simultaneously, both is in poised state can to reach that comparatively ideal sidewall profile is not in most cases
In control state.
Therefore, reduce in stead-state deep silicon etching techniques and pinhole patterns occur on the wall of side, be that this hair says needs
The technical problem of solution.
The content of the invention
The purpose that this hair is said is to provide a kind of silicon chip etching method, and it can avoid side wall appearance to the full extent
Pinhole patterns.
To achieve the above object, the technical scheme that this hair is said is as follows：
A kind of silicon chip etching method, for carrying out deep silicon etching to being positioned in reaction chamber the silicon chip on electrostatic chuck
Technique, this method comprises the following steps：A, it is passed through process gas into reaction chamber, process gas includes etching gas, side wall
Passivation gas and hydrogen-containing gas, hydrogen-containing gas account for the ratio of process gas less than 50%, the flow-rate ratio of hydrogen-containing gas and etching gas
Example is 1:10 to 1:2；B, to reaction chamber apply radio-frequency power, technique and side wall are performed etching to silicon chip to produce plasma
Passivation technology.
Preferably, hydrogen-containing gas includes at least one of following gas：CH4；C4H10；H2；And CHxFy, wherein, x and
Y is positive integer.
Preferably, inert gas is also included in process gas.
Preferably, inert gas is helium.
This hair says the silicon chip etching method provided, in silicon chip etching technology, has been passed through into reaction chamber comprising hydrogeneous
Process gas including gas, in the presence of radio-frequency power, process gas can be changed into plasma, on the one hand, plasma
H ions in body can be combined with part F ion, relax the progress of etching reaction；Another hair says that hydrogen-containing gas is also to reaction chamber
Etching gas concentration in room is diluted, and equally serves the effect for having relaxed etching reaction.In the deep silicon of stead-state
In etching technics, in the case where etching reaction obtains mitigation, it is easier to reach the balance of etching reaction and side wall passivation reaction,
So as to which the probability that pinhole patterns occurs in side wall is substantially reduced, pinhole quantity also says aobvious reduction.
Brief description of the drawings
Fig. 1 shows that this hair says the silicon chip etching method schematic flow sheet of first embodiment；
Fig. 2 shows that this hair says the silicon chip etching method schematic flow sheet of 3rd embodiment.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment said to this hair is made further to have a talk about in detail.
As shown in figure 1, this hair says the silicon chip etching method that first embodiment is provided, for quiet in reaction chamber to being positioned over
Silicon chip on electric card disk carries out deep silicon etching technique, and it includes following two steps：
Step S10, be passed through process gas into reaction chamber, process gas include etching gas, side wall passivation gas and
Hydrogen-containing gas, wherein, the ratio that hydrogen-containing gas accounts for process gas is less than 50%.
Specifically, etching gas include SF6, side wall passivation gas is mainly O2And SiF4, hydrogen-containing gas is following gas
It is any or appoint it is a variety of：CH4；C4H10；H2；And CHxFy, wherein, x and y are positive integer.It is passed through the hydrogen of reaction chamber
The ratio that body flow accounts for process gas total flow should not be greater than 50%, meanwhile, the flow proportional of hydrogen-containing gas and etching gas is 1:
10 to 1:2, it otherwise can be difficult to realize the technological effect of silicon chip etching technology；
Process gas can also include the gases such as HBr and Ar.
Under preferable case, the flow that each predominant gas is passed through into reaction chamber is：SF6Flow is 500-2000SCCM, O2
Flow is 50-300SCCM, SiF4Flow is 200-600SCCM.
Further, process gas pressure is 20-150mTorr in reaction chamber.
O in side wall passivation gas2Hydrocarbon, oxynitrides and O can also be used3Can be in radio frequency work(Deng other
The gas that oxonium ion is dissociated under rate effect is replaced.
According to another embodiment of the embodiment, side wall passivation gas is mainly O3And SiCl4, it is equally in electricity
From for that can react to form sidewall passivation layer with side wall after plasma, with protective side wall pattern.
Step S11, to reaction chamber apply radio-frequency power, technique and side wall are performed etching to silicon chip to produce plasma
Passivation technology, wherein, radio-frequency power includes RF source power and RF bias power.
Specifically, it is plasma to be ionized including the process gas including hydrogen-containing gas in the presence of RF source power,
Perform etching reaction and side wall passivation reaction simultaneously in reaction chamber in the presence of RF bias power.
The above-mentioned first embodiment said according to this hair, on the one hand, the H ions in plasma can be combined with part F ion,
The progress of etching reaction is relaxed；Another hair says that hydrogen-containing gas is also diluted to the etching gas concentration in reaction chamber,
Equally serve the effect for relaxing etching reaction.It is anti-so as to be conducive to reaching in stead-state deep silicon etching techniques etching
The balance that should be reacted with side wall passivation, the probability for making etched sidewall pinhole patterns occur substantially reduces, while pinhole
Quantity also says aobvious reduction.
This hair says the silicon chip etching method that second embodiment is provided, only to reaction chamber within a period of time after technique starts
A certain amount of hydrogen-containing gas is passed through in room as regulation gas, the ratio that hydrogen-containing gas flow accounts for process gas is 10%-30%, its
In, the flow proportional of hydrogen-containing gas and etching gas is 1:10 to 1:2；So that etching reaction is relaxed, etching reaction is formed
The balance reacted with side wall passivation, so that avoid the occurrence of pinhole patterns or repair the pinhole patterns occurred on a small quantity, with
Stop being passed through hydrogen-containing gas afterwards, continue subsequent technique.
It is appreciated that in some technique occasions, the hydrogen-containing gas of first flow can be also first passed through within the very first time, with
Stop being passed through afterwards, then as needed, the hydrogen-containing gas of second flow can be passed through within the second time.But it also should strictly limit and contain
The ratio that hydrogen flow accounts for process gas total flow is less than 50%, meanwhile, the flow proportional of hydrogen-containing gas and etching gas is 1:
10 to 1:2.
According to the difference of etching object, there are difference the difference of technological parameter, the be passed through time, flow of hydrogen-containing gas；Can
The data counted according to test of many times, are specifically determined.
Under preferable case, the time that is passed through of hydrogen-containing gas adds up to 1-3 minutes, and flow adds up to 200-800SCCM.Reaction
Process gas pressure is 20-150mTorr in chamber.
In addition, in addition to hydrogen-containing gas, the process gas being passed through to reaction chamber can also include at least one inert gas,
Inert gas is further diluted to etching gas, side wall passivation gas, is reacted etching reaction and side wall passivation and is all obtained
To relaxing to a certain extent, this two kinds reactions are made all will be relatively slowly to carry out, so as to be more conducive to control the pattern of side wall.
Further, the inert gas that the embodiment is used is helium.
As shown in Fig. 2 this hair says the silicon chip etching method that 3rd embodiment is provided, for carrying out deep silicon etching work to silicon chip
Skill, including following three step：
S20, it is passed through process gas into reaction chamber, process gas includes etching gas, side wall passivation gas and hydrogeneous
Gas, wherein, hydrogen-containing gas accounts for the ratio of process gas less than 50%, and the flow proportional of hydrogen-containing gas and etching gas is 1:10
To 1:2.
Specifically, etching gas, side wall passivation gas may come from conventional gas of the prior art, for example, side
Wall passivation gas can be O2, hydrocarbon, oxynitrides and O3Etc. can radio-frequency power effect under be dissociated into oxonium ion
Gas, with SiF4And/or SiCl4Mixed gas.Hydrogen-containing gas is any of following gas or appoints a variety of：CH4；C4H10；
H2；And CHxFy, wherein, x and y are positive integer.Process gas also includes the gases such as HBr and Ar.
S21, the temperature of the electrostatic chuck of regulation reaction chamber bottom are -50 to 50 degrees Celsius.
Specifically, chip to be processed is positioned on the electrostatic chuck of reaction chamber bottom, is fixed with Electrostatic Absorption.From reality
Know in testing, when by the temperature control of electrostatic chuck at -50 to 50 degrees Celsius, be more conducive to the realization pair in subsequent step S22
Balance between etching reaction and the side wall passivation reaction of chip, so as to further avoid the appearance of pinhole patterns.
S22, to reaction chamber apply radio-frequency power, technique and side wall passivation are performed etching to silicon chip to produce plasma
Technique, wherein, radio-frequency power includes RF source power and RF bias power.
Specifically, in plasma H ions and the combination of part F ion, and hydrogen-containing gas is to the dilute of etching gas
Effect is released, etching reaction has been relaxed, side wall is eventually reduced and the probability of pinhole patterns and pinhole number occurs
Amount.
Further, inert gas, such as helium can also be included in process gas, further to relax etching reaction
With side wall passivation reaction.
Under preferable case, the flow that each predominant gas is passed through into reaction chamber is：With SF6For etching gas, flow is
500-2000SCCM, with O3And SiF4For side wall passivation gas, O3Flow is 50-300SCCM, SiF4Flow is 200-
600SCCM。
Further, process gas pressure is 20-150mTorr in reaction chamber.
Above-described is only the preferred embodiment that this hair is said, the embodiment simultaneously is not used to limit the patent guarantor that this hair is said
Protect scope, thus it is every change with having a talk about of saying of this hair and equivalent structure that accompanying drawing content is made, similarly should be included in
In the protection domain that this hair is said.
Claims (9)
1. a kind of silicon chip etching method, for carrying out deep silicon etching work to being positioned in reaction chamber the silicon chip on electrostatic chuck
Skill, it is characterised in that the deep silicon etching technique is that etching reaction and side wall passivation reaction are carried out simultaneously all the time, methods described bag
Include following steps：
A, it is passed through process gas into reaction chamber, the process gas includes etching gas, side wall passivation gas and hydrogen
Body, the ratio that the hydrogen-containing gas accounts for the process gas is less than 50%；
B, the temperature of the electrostatic chuck of the regulation reaction chamber bottom are -50 to 50 degrees Celsius；And to the reaction chamber
Apply radio-frequency power, to produce plasma to the silicon chip while carrying out the etching technics and the side wall passivation technology,
Wherein described etching gas produce the plasma of F ion, and the hydrogen-containing gas produces the plasma of H ions.
2. silicon chip etching method as claimed in claim 1, it is characterised in that the hydrogen-containing gas is included in following gas extremely
Few one kind：
CH4；
C4H10；
H2；
And CHxFy, wherein, x and y are positive integer.
3. silicon chip etching method as claimed in claim 2, it is characterised in that also include inert gas in the process gas.
4. silicon chip etching method as claimed in claim 3, it is characterised in that the inert gas is helium.
5. silicon chip etching method as claimed in claim 2, it is characterised in that the etching gas include SF6。
6. silicon chip etching method as claimed in claim 5, it is characterised in that the side wall passivation gas includes：
O2And O3At least one of；And
SiF4And SiCl4At least one of.
7. silicon chip etching method as claimed in claim 6, it is characterised in that the side wall passivation gas is O2And SiF4。
8. silicon chip etching method as claimed in claim 7, it is characterised in that the SF in the etching gas6Flow is 500-
2000SCCM, O2Flow is 50-300SCCM, SiF4Flow is 200-600SCCM.
9. silicon chip etching method as claimed in claim 8, it is characterised in that process gas pressure is in the reaction chamber
20-150mTorr。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310150615.8A CN104124148B (en) | 2013-04-26 | 2013-04-26 | Silicon chip etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310150615.8A CN104124148B (en) | 2013-04-26 | 2013-04-26 | Silicon chip etching method |
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| Publication Number | Publication Date |
|---|---|
| CN104124148A CN104124148A (en) | 2014-10-29 |
| CN104124148B true CN104124148B (en) | 2017-08-22 |
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| CN201310150615.8A Active CN104124148B (en) | 2013-04-26 | 2013-04-26 | Silicon chip etching method |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107887269A (en) * | 2017-11-03 | 2018-04-06 | 通威太阳能（安徽）有限公司 | A kind of crystal silicon solar energy battery etching technics |
| CN108254811A (en) * | 2018-01-19 | 2018-07-06 | 电子科技大学 | A kind of infrared optical window with three step anti-reflection structures and preparation method thereof |
| CN110648909B (en) * | 2019-09-30 | 2022-03-18 | 福建北电新材料科技有限公司 | Back grinding method, substrate wafer and electronic device |
| CN115116843A (en) * | 2022-07-29 | 2022-09-27 | 捷捷微电(南通)科技有限公司 | Deep silicon etching method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562122B (en) * | 2008-04-16 | 2010-09-01 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Dry etching method and silicon wafer etching method |
| CN102031525A (en) * | 2009-09-29 | 2011-04-27 | 中微半导体设备(上海)有限公司 | Method for etching deep through silicon via (TSV) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100230981B1 (en) * | 1996-05-08 | 1999-11-15 | 김광호 | Plasma etching method for manufacturing process of semiconductor device |
| US8043973B2 (en) * | 2008-05-22 | 2011-10-25 | Texas Instruments Incorporated | Mask overhang reduction or elimination after substrate etch |
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2013
- 2013-04-26 CN CN201310150615.8A patent/CN104124148B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562122B (en) * | 2008-04-16 | 2010-09-01 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Dry etching method and silicon wafer etching method |
| CN102031525A (en) * | 2009-09-29 | 2011-04-27 | 中微半导体设备(上海)有限公司 | Method for etching deep through silicon via (TSV) |
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Address after: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee after: Medium and Micro Semiconductor Equipment (Shanghai) Co., Ltd. Address before: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee before: Advanced Micro-Fabrication Equipment (Shanghai) Inc. |