CN104103681A - Floating gate structure and manufacturing method thereof - Google Patents
Floating gate structure and manufacturing method thereof Download PDFInfo
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- CN104103681A CN104103681A CN201410315925.5A CN201410315925A CN104103681A CN 104103681 A CN104103681 A CN 104103681A CN 201410315925 A CN201410315925 A CN 201410315925A CN 104103681 A CN104103681 A CN 104103681A
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- 238000007667 floating Methods 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 111
- 238000000034 method Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000002955 isolation Methods 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 33
- 238000002347 injection Methods 0.000 claims abstract description 7
- 239000007924 injection Substances 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims description 101
- 230000008569 process Effects 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 15
- 238000005516 engineering process Methods 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 230000008878 coupling Effects 0.000 abstract description 7
- 238000010168 coupling process Methods 0.000 abstract description 7
- 238000005859 coupling reaction Methods 0.000 abstract description 7
- 230000008021 deposition Effects 0.000 description 14
- 238000004321 preservation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a floating gate structure and a manufacturing method thereof. The method comprises the steps of providing a substrate which comprises a first part and a second part, performing well injection on the substrate, continuously forming a gate oxide layer, then forming a plurality of first polycrystalline silicon structures, forming shallow grooves in the substrate between the adjacent first polycrystalline silicon structures, forming shallow groove isolation, depositing a second polycrystalline silicon layer on the first polycrystalline silicon structures and the shallow groove isolation on the first part, etching the second polycrystalline silicon layer, forming second polycrystalline silicon structures, exposing partial shallow groove isolation, and allowing side walls of the second polycrystalline silicon structures on the two sides of the exposed partial shallow groove isolation to be smooth. The method saves a photomask, simplifies a technology, and achieves perfect alignment of floating gate polycrystalline silicon and an active region. An application of a floating gate polycrystalline silicon side wall technique meets a control gate and floating gate coupling requirement, eliminates a sharp corner, and facilitates storing charge in floating gate polycrystalline silicon.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of floating gate structure and manufacture method thereof.
Background technology
Along with the high speed development of portable electric appts, more and more higher to the requirement of data storage.Be divided into volatile memory and nonvolatile memory for the semiconductor memory of storing data.In nonvolatile memory, flash memory (flash memory) is due to its very high chip-stored density, and Technological adaptability preferably, become a kind of very important device.And the flash memory of floating gate structure is the big hot topic in flash memory.
In floating gate flash memory product, current floating polysilicon grid technique mainly contains two kinds:
1. common process, comprising: 1. active area photoetching, etching, 2. shallow trench isolation from oxide deposition, eat-back 3. floating gate polysilicon deposition, 4. floating gate polysilicon photoetching, 5. floating gate polysilicon etching.
2. floating boom-active area self-registered technology, comprising: 1. active area photoetching, etching, 2. shallow trench isolation from oxide deposition, eat-back (more etch-back amount), 3. floating gate polysilicon deposition, 4. floating gate polysilicon planarization.
Through inventor's discovery that studies for a long period of time, above-mentioned two kinds of conventional process exist this many constant.For example: for conventional method, (1) has been used active area, the photoetching of floating boom twice, has increased light shield and process costs.(2) multi-crystal silicon floating bar is a technique challenge to the alignment issues of active area, easily occurs the skew of floating gate polysilicon to active area.Therefore be not suitable for 65 nanometers and more advanced technique.(3) corner of floating gate polysilicon is sharp-pointed, is unfavorable for the deposition of follow-up floating boom-control gate separator, and sharp-pointed corner easily forms the passage that stored charge is escaped.
For floating boom-active area self-registered technology, exist following defect: (1) is determined by follow-up polysilicon deposition because of the etch-back amount of shallow trench isolating oxide layer, is unfavorable for controlling the coupling amount of control gate polysilicon to floating gate polysilicon.(2), easily there is polysilicon deposition space in the technique challenge of polysilicon deposition.(3) due to the process technology limit of polysilicon deposition and polysilicon planarization, cause floating gate polysilicon thickness partially thin, be unfavorable for the preservation of stored charge.
Therefore,, in the urgent need to improving existing technique, provide a kind of manufacture method of more reliable floating gate structure.
Summary of the invention
One object of the present invention is, a kind of floating gate structure and manufacture method thereof are provided, and simplifies manufacture craft.
One object of the present invention is, a kind of floating gate structure and manufacture method thereof are provided, and improves grid coupling mass, optimizes grid coupling coefficient.
One object of the present invention is, a kind of floating gate structure and manufacture method thereof are provided, and improves the hold capacity of electric charge in floating gate polysilicon.
To this, the invention provides a kind of manufacture method of floating gate structure, comprising:
Substrate is provided, and described substrate comprises the Part I that is used to form memory cell and the Part II that is used to form peripheral area structure;
Described substrate is carried out to trap injection;
On described substrate, form gate oxide;
On described substrate, form multiple the first polysilicon structures, and form shallow trench in substrate between adjacent the first polysilicon structure;
Form shallow trench isolation from;
Multiple the first polysilicon structures and shallow trench isolation from deposit the second polysilicon layer;
Etching is positioned at shallow trench isolation from the second upper polysilicon layer, forms the second polysilicon structure, expose part shallow trench isolation from, and make the part shallow trench isolation that exposes round and smooth from the second polysilicon structure sidewall of both sides.
Optionally, for the manufacture method of described floating gate structure, described gate oxide comprises tunnel oxide on the Part I that is positioned at described substrate, be positioned at high tension apparatus grid oxide layer and low-voltage device grid oxide layer on the Part II of described substrate.
Optionally, for the manufacture method of described floating gate structure, the thickness of described tunnel oxide is
the thickness of described high tension apparatus grid oxide layer is
the thickness of described low-voltage device grid oxide layer is
Optionally, for the manufacture method of described floating gate structure, on described substrate, form multiple the first polysilicon structures, and in substrate between adjacent the first polysilicon structure, form shallow trench and comprise:
Deposit the first polysilicon layer, cover described gate oxide;
Carry out active area photoetching, form multiple the first polysilicon structures with the first polysilicon layer described in this etching, between the first adjacent polysilicon structure, expose gate oxide;
The gate oxide that etching exposes, exposes part substrate;
The part substrate that etching exposes, forms shallow trench.
Optionally, for the manufacture method of described floating gate structure, the first polysilicon layer is N-type doping, and thickness is
Optionally, for the manufacture method of described floating gate structure, when the first polysilicon layer, make etch-stop be left to gate oxide by controlling etching selection ratio described in etching.
Optionally, for the manufacture method of described floating gate structure, the gate oxide that etching exposes, gate oxide is 1:1 to the etching selectivity of silicon.
Optionally, for the manufacture method of described floating gate structure, form shallow trench isolation from comprising:
In described shallow trench, fill isolation oxide;
Described isolation oxide is carried out to flatening process;
Return and carve described isolation oxide, remove the segment thickness between adjacent the first polysilicon structure.
Optionally, for the manufacture method of described floating gate structure, described the second polysilicon layer is N-type doping, and thickness is
Optionally, for the manufacture method of described floating gate structure, described the second polysilicon structure sidewall is up-narrow and down-wide structure.
Accordingly, the invention provides a kind of floating gate structure, comprising: be positioned at the main part on substrate and be positioned at the round and smooth sidewall of described main part both sides.
Optionally, for described floating gate structure, described sidewall is up-narrow and down-wide structure.
Compared with prior art, in floating gate structure provided by the invention and manufacture method thereof, there is following advantage:
Utilize the autoregistration of floating boom and active area, save the light shield expense of floating boom.
Floating boom and active area autoregistration, can realize floating gate polysilicon and aim at the accurate of active area.
The application of floating gate polysilicon sidewall technology, can, by adjusting the collocation of the first polysilicon structure and the second polysilicon layer thickness, easily realize the coupling amount of needed control gate to floating boom.The application of floating gate polysilicon sidewall technology, can realize floating boom-control gate separator even deposition, has eliminated wedge angle phenomenon, is conducive to the preservation of electric charge in floating gate polysilicon.
Brief description of the drawings
Fig. 1 is the flow chart of the manufacture method of embodiment of the present invention floating gate structure;
Fig. 2-Fig. 8 is device architecture schematic diagram in the process of manufacture method of embodiment of the present invention floating gate structure.
Embodiment
Below in conjunction with schematic diagram, the manufacture method of floating gate structure of the present invention is described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of floating gate structure and manufacture method thereof are provided, and the method comprises:
Step S101: substrate is provided, and described substrate comprises the Part I that is used to form memory cell and the Part II that is used to form peripheral area structure;
Step S102: described substrate is carried out to trap injection;
Step S103: form gate oxide on described substrate;
Step S104: form multiple the first polysilicon structures on described substrate, and form shallow trench in substrate between adjacent the first polysilicon structure;
Step S105: form shallow trench isolation from;
Step S106: multiple the first polysilicon structures on the Part I of described substrate and shallow trench isolation from deposit the second polysilicon layer;
Step S107: etching is positioned at shallow trench isolation from the second upper polysilicon layer, forms the second polysilicon structure, expose part shallow trench isolation from, and make the part shallow trench isolation that exposes round and smooth from the second polysilicon structure sidewall of both sides.
By said process, can obtain the floating gate structure with round and smooth sidewall.
Below enumerate the preferred embodiment of the manufacture method of described floating gate structure, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by those of ordinary skill in the art's routine techniques means are also within thought range of the present invention.
Please refer to Fig. 1 and Fig. 2-Fig. 8, Fig. 1 is the flow chart of the manufacture method of embodiment of the present invention floating gate structure, and Fig. 2-Fig. 8 is device architecture schematic diagram in the process of manufacture method of embodiment of the present invention floating gate structure.The manufacture method of the floating gate structure of the present embodiment comprises:
Step S101: substrate 10 is provided, and described substrate 10 comprises the Part I 101 that is used to form memory cell and the Part II 102 that is used to form peripheral area structure.The constituent material of described substrate 10 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.As example, in the present embodiment, described substrate 10 selects single crystal silicon material to form.In described substrate 20, can also be formed with buried regions (not shown) etc.
Step S102: described substrate 10 is carried out to trap injection.Please continue to refer to Fig. 2, first on substrate 10, form a sacrificial oxide layer 11, the thickness of described sacrificial oxide layer 11 is preferably
described trap injects the memory cell areas trap injection that is included in Part I 101 and carries out, the higher-pressure region trap carrying out at Part II 102 injects and low-pressure area trap injects.As shown in Figure 2, can utilize photoresist 12 to carry out the injection of ion as mask.Described memory cell areas trap injects, higher-pressure region trap injects and low-pressure area trap injects and can carry out according to existing technique and specification, and the present invention is not construed as limiting this.
Step S103: form gate oxide on described substrate 10.Specifically please refer to Fig. 3, sacrificial oxide layer is removed, and described gate oxide comprises tunnel oxide 21 on the Part I 101 that is positioned at described substrate, be positioned at high tension apparatus grid oxide layer 22 and low-voltage device grid oxide layer 23 on the Part II 102 of described substrate.Preferably, the thickness maximum of described high tension apparatus grid oxide layer 22, the thickness of tunnel oxide 21 takes second place, the thickness minimum of low-voltage device grid oxide layer 23.For example, in a preferred embodiment, the thickness of described tunnel oxide is
with
left and right is best; The thickness of described high tension apparatus grid oxide layer is
with
left and right is best; The thickness of described low-voltage device grid oxide layer is
with
left and right is best.
In this step, before the deposition of gate oxide is formed on to active area formation, can improves the round and smooth degree in corner of gate oxide, thereby the grid oxygen puncture voltage of corner is improved.
Step S104: form multiple the first polysilicon structures 31 on described substrate 10, and form shallow trench 32 in substrate 10 between adjacent the first polysilicon structure 31, as shown in Figure 4.Concrete, comprising: first deposit the first polysilicon layer and carry out N-type doping, doping content is about 1e-20cm
-3for good, be covered on described gate oxide, the thickness of described the first polysilicon layer can be
then carry out active area photoetching, form multiple the first polysilicon structures 31 with the first polysilicon layer described in this etching.Described in etching when the first polysilicon layer, make etch-stop be left to gate oxide by controlling etching selection ratio, between the first adjacent polysilicon structure 31, expose gate oxide.Then, the gate oxide that etching exposes, sets the height that gate oxide is tried one's best to the etching selectivity of silicon, for example, be 1:1 left and right, thereby expose part substrate 10.Finally the part substrate 10 exposing is carried out to etching, by controlling the reaction time to form required shallow trench 32.
This step is also a key point in the present invention, adopts self-registered technology to carry out etching, can either save light shield, can realize again floating gate polysilicon and aim at the accurate of active area.Each etching in this step, the present invention does not lay down hard-and-fast rule, and those skilled in the art can make suitable selection according to existing etching technics.
Step S105: form shallow trench isolation from 40, please refer to Fig. 5.The present invention sets forth emphatically the manufacture process of memory cell areas after this step, i.e. manufacture craft on the Part I 101 of substrate.Forming shallow trench isolation comprises from 40: first in described shallow trench, fill isolation oxide, expire and be advisable to fill.Then described isolation oxide is carried out to flatening process, remove the part being positioned on the first polysilicon structure 31.Then, utilizing wet processing to return and carve described isolation oxide, for example, can be hydrofluoric acid solution, removes the segment thickness between adjacent the first polysilicon structure 31.The number that isolation oxide is eat-back can be controlled the height of follow-up polysilicon deposition, thereby can adjust the coupling amount of control gate polysilicon to floating gate polysilicon.
Step S106: multiple the first polysilicon structures 31 on the Part I 101 of described substrate and shallow trench isolation deposit the second polysilicon layer 50 on from 40.Please refer to Fig. 6, described the second polysilicon layer 50 is N-type doping, and doping situation is consistent with the first polysilicon layer, and thickness is
can be for example
deng.The thickness of deposition determines the width of final floating gate polysilicon, and the thickness that can adjust the second polysilicon layer according to actual demand reaches best floating boom width and height.
Step S107: please refer to Fig. 7 etching and be positioned at shallow trench isolation from the second polysilicon layer on 40, form the second polysilicon structure 50, expose part shallow trench isolation from 40, and making the part shallow trench isolation that exposes round and smooth from the second polysilicon structure sidewall 60 of 40 both sides, this second polysilicon structure sidewall 60 is up-narrow and down-wide structure.The first polysilicon structure 31 combines with the second polysilicon structure 50 so, obtains floating boom of the present invention.The etching period of the second polysilicon layer can determine height and the width of final floating gate polysilicon, therefore, should be according to actual needs and operational characteristic, selectively carry out etching planning, obtain best height and width.
In Fig. 7, the floating gate structure in the present invention forms, and this floating gate structure can be planned to the round and smooth sidewall 60 that comprises the main part 61 on the Part I 101 that is positioned at substrate and be positioned at described main part 61 both sides.Described sidewall 60 is up-narrow and down-wide structure.
This step is also the floating gate polysilicon sidewall technology in the present invention, can, by adjusting the collocation of the first polysilicon structure and the second polysilicon layer thickness, easily realize the coupling amount of needed control gate to floating boom.The application of floating gate polysilicon sidewall technology, can realize floating boom-control gate separator even deposition, has eliminated wedge angle phenomenon, is conducive to the preservation of electric charge in floating gate polysilicon.
Then, as shown in Figure 8, on the second polysilicon structure 50, form one deck isolating oxide layer 70, with by isolated to the control gate of follow-up formation and floating boom.As mentioned above, the isolating oxide layer 70 of acquisition is level and smooth, has eliminated wedge angle phenomenon, is conducive to the preservation of electric charge in floating gate polysilicon.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (12)
1. a manufacture method for floating gate structure, comprising:
Substrate is provided, and described substrate comprises the Part I that is used to form memory cell and the Part II that is used to form peripheral area structure;
Described substrate is carried out to trap injection;
On described substrate, form gate oxide;
On described substrate, form multiple the first polysilicon structures, and form shallow trench in substrate between adjacent the first polysilicon structure;
Form shallow trench isolation from;
Multiple the first polysilicon structures on the Part I of described substrate and shallow trench isolation from deposit the second polysilicon layer;
Etching is positioned at shallow trench isolation from the second upper polysilicon layer, forms the second polysilicon structure, expose part shallow trench isolation from, and make the part shallow trench isolation that exposes round and smooth from the second polysilicon structure sidewall of both sides.
2. the manufacture method of floating gate structure as claimed in claim 1, it is characterized in that, described gate oxide comprises tunnel oxide on the Part I that is positioned at described substrate, be positioned at high tension apparatus grid oxide layer and low-voltage device grid oxide layer on the Part II of described substrate.
3. the manufacture method of floating gate structure as claimed in claim 2, is characterized in that, the thickness of described tunnel oxide is
the thickness of described high tension apparatus grid oxide layer is
the thickness of described low-voltage device grid oxide layer is
4. the manufacture method of floating gate structure as claimed in claim 1, is characterized in that, forms multiple the first polysilicon structures on described substrate, and in substrate between adjacent the first polysilicon structure, forms shallow trench and comprise:
Deposit the first polysilicon layer, cover described gate oxide;
Carry out active area photoetching, form multiple the first polysilicon structures with the first polysilicon layer described in this etching, between the first adjacent polysilicon structure, expose gate oxide;
The gate oxide that etching exposes, exposes part substrate;
The part substrate that etching exposes, forms shallow trench.
5. the manufacture method of floating gate structure as claimed in claim 4, is characterized in that, the first polysilicon layer is N-type doping, and thickness is
6. the manufacture method of floating gate structure as claimed in claim 4, is characterized in that, when the first polysilicon layer, makes etch-stop be left to gate oxide by controlling etching selection ratio described in etching.
7. the manufacture method of floating gate structure as claimed in claim 4, is characterized in that, the gate oxide that etching exposes, and gate oxide is 1:1 to the etching selectivity of silicon.
8. the manufacture method of floating gate structure as claimed in claim 1, is characterized in that, forms shallow trench isolation from comprising:
In described shallow trench, fill isolation oxide;
Described isolation oxide is carried out to flatening process;
Return and carve described isolation oxide, remove the segment thickness between adjacent the first polysilicon structure.
9. the manufacture method of floating gate structure as claimed in claim 1, is characterized in that, described the second polysilicon layer is N-type doping, and thickness is
10. the manufacture method of floating gate structure as claimed in claim 1, is characterized in that, described the second polysilicon structure sidewall is up-narrow and down-wide structure.
11. 1 kinds of floating gate structure, comprising: be positioned at the main part on substrate and be positioned at the round and smooth sidewall of described main part both sides.
The manufacture method of 12. floating gate structure as claimed in claim 11, is characterized in that, described sidewall is up-narrow and down-wide structure.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576397A (en) * | 2014-11-20 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for split-gate flash memory |
| CN105789137A (en) * | 2014-12-25 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electronic device |
| CN105826271A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of flash |
| CN106158613A (en) * | 2015-04-15 | 2016-11-23 | 上海格易电子有限公司 | A kind of method improving floating-gate device electronics retentivity and FGS floating gate structure |
| CN108054092A (en) * | 2017-12-25 | 2018-05-18 | 深圳市晶特智造科技有限公司 | A kind of polysilicon fill method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040195616A1 (en) * | 2003-04-03 | 2004-10-07 | Vanguard International Semiconductor Corporation | Floating gates having improved coupling ratios and fabrication method thereof |
| US20050142749A1 (en) * | 2003-12-31 | 2005-06-30 | Dongbuanam Semiconductor Inc. | Flash memory device and fabricating method thereof |
| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| CN1725470A (en) * | 2004-07-23 | 2006-01-25 | 海力士半导体有限公司 | Method for manufacturing a flash memory device |
| CN101140909A (en) * | 2006-09-04 | 2008-03-12 | 东部高科股份有限公司 | Method of fabricating flash memory device |
-
2014
- 2014-07-02 CN CN201410315925.5A patent/CN104103681A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040195616A1 (en) * | 2003-04-03 | 2004-10-07 | Vanguard International Semiconductor Corporation | Floating gates having improved coupling ratios and fabrication method thereof |
| US20050142749A1 (en) * | 2003-12-31 | 2005-06-30 | Dongbuanam Semiconductor Inc. | Flash memory device and fabricating method thereof |
| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| CN1725470A (en) * | 2004-07-23 | 2006-01-25 | 海力士半导体有限公司 | Method for manufacturing a flash memory device |
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