CN104103501A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method therefor Download PDFInfo
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- CN104103501A CN104103501A CN201410138566.0A CN201410138566A CN104103501A CN 104103501 A CN104103501 A CN 104103501A CN 201410138566 A CN201410138566 A CN 201410138566A CN 104103501 A CN104103501 A CN 104103501A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- High Energy & Nuclear Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
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- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Electron Beam Exposure (AREA)
Abstract
A semiconductor device manufacturing method is disclosed by which electron beam irradiation is accomplished at a low cost while exhibiting uniform characteristics. A wafer stack consisting of multiple stacked wafers is irradiated with an electron beam from both the front surface and reverse surface. As such, a semiconductor device manufacturing method is provided whereby the electrical characteristics are extremely uniform between wafers, and costs are reduced by reducing the number of electron beam irradiations.
Description
Technical field
The present invention relates to a kind of have to semiconductor substrate irradiate the manufacturing method for semiconductor device of operation of electron ray and the semiconductor device that utilizes the method manufacture to form.
Background technology
Generally speaking, become in the bipolar-type power semiconductor device of conducting charge carrier at minority carrier, have p-i-n diode, insulated gate bipolar transistor (IGBT) etc.The amplitude of the rated voltage of bipolar-type power semiconductor device is larger, is 600V～6500V left and right.
On the other hand, what majority carrier became conducting charge carrier is monopole type power semiconductor arrangement, and it is represented as power MOSFET (MOSFET: insulated-gate type field effect transistor).Power MOSFET, in the time of forward conduction, utilizes majority carrier (electronics) to move.On the other hand, in the time of reverse bias, the parasitic diode being made up of p-type base layer and N-shaped drift layer and N-shaped drain electrode layer moves., minority carrier (hole) is injected into N-shaped drift layer from p-type base layer, has reverse-conducting characteristic.Thus, power MOSFET when reverse-conducting becomes bipolar action.The rated voltage of power MOSFET is several 10V～1000V left and right.
The in the situation that of bipolar-type power semiconductor device, in the time of conducting, the charge carrier (electronics, hole) of the high several orders of magnitude of the concentration of concentration ratio drift layer is stored in this drift layer, realize thus lower voltage drop.On the other hand, in the time transferring to cut-off state from conducting state,, in the time of switch, if this storage charge carrier is not all cleared out, drift layer cannot exhaust.Therefore, in the time of switch, need the regular hour.Thereby, how in maintaining lower voltage drop, clear out rapidly to become and take into account the low loss characteristic of bipolar-type power semiconductor device and the key of speed-sensitive switch characteristic storing charge carrier.
As making bipolar-type power semiconductor device become the means of speed-sensitive switch, there is electron ray to irradiate.By irradiating electron ray to power semiconductor arrangement, thereby to the particularly crystal defect of large (darker) of drift layer importing of semiconductor substrate, form recombination center.Thus, can shorten switching time.As general electron ray method, make the acceleration energy of electron ray become 2MeV～5MeV left and right, and carry out electron ray irradiation to single-crystal wafer.In addition, the control of crystal defect concentration is adjusted by the exposure dose of electron ray.Afterwards, by more than 200 DEG C 500 DEG C carry out below the annealing of the scheduled time, thereby can form recombination center, make switch high speed.
In patent documentation 1, record following method: be increased to 10MeV by will speed up energy, thereby irradiate electron ray to multi-disc silicon wafer simultaneously, reduce thus and irradiate number of times to realize cost.
In patent documentation 2, record for the structure of wafer stacking body to multi-disc wafer illumination electron ray and the manufacture method of stacked body.
Prior art document
Patent documentation
Patent documentation 1: Japanese Patent Laid-Open 2004-273863 communique
Patent documentation 2: No. 6475432 specification of United States Patent (USP)
Summary of the invention
Invent problem to be solved
In electron ray irradiates, the exposure dose that once can irradiate is generally about 10kGy left and right.In the case of in order to realize desired speed-sensitive switch characteristic, needed exposure dose is 100kGy, need to irradiate 10 times, deviation each time can increase along with irradiating the increase of number of times.Need to irradiate the reasons are as follows repeatedly for fixing exposure dose: generally, in commercial kitchen area, the trickle adjustment of the exposure to each product becomes the reason that cost is high, output reduces.Therefore,, if repeat the irradiation of 10 left and right, can in exposure dose, produce the deviation of 20% left and right.The deviation of this exposure dose becomes the deviation of the crystal defect concentration of semiconductor substrate, therefore becomes the reason of element characteristic deviation.
For example, as described in Patent Document 1, in the situation that once multi-disc being irradiated, between the wafer nearest from electronic radial source and wafer farthest, thickness is several mm, and therefore the difference of exposure dose or deviation easily become large.
The exposure dose of speed-sensitive switch characteristic and electron ray has positive correlation.Therefore,, if the number of times that electron ray irradiates is more, can shortens switching time, and can improve speed-sensitive switch characteristic.But, as mentioned above because the deviation of exposure dose is more, therefore can be because of the deviation occurrence features of crystal defect inhomogeneous.Particularly, the in the situation that of vehicle-mounted purposes, require to reduce deviation and strict management, need to take into account the electron ray cost degradation irradiating and the inhomogeneity means that improve characteristic.
In addition, in patent documentation 2, do not record the method for irradiating electron ray to wafer stacking body.
The object of the present invention is to provide one to address the above problem, realize the manufacturing method for semiconductor device of the electron ray irradiation of characteristic homogenizing with low cost.
The technical scheme that technical solution problem adopts
In order to achieve the above object, the invention of recording according to claim,
Adopt a kind of manufacturing method for semiconductor device, the interarea of the wafer stacking body forming from stacked more than two semiconductor substrate irradiates electron ray, and this manufacturing method for semiconductor device has following operation:
Irradiate the first irradiation process of electron ray from an interarea of described wafer stacking body; And
With the acceleration energy identical with acceleration energy in the irradiation of described electron ray, irradiate the second irradiation process of electron ray from another interarea of described wafer stacking body.
The exposure dose of described the second irradiation process also can be identical with the exposure dose of described the first irradiation process.
The number of times of described the first irradiation process also can be identical with the number of times of described the second irradiation process.
The exposure dose of described the second irradiation process also can be different from the exposure dose of described the first irradiation process.
The exposure dose of an irradiation process among described the first and second irradiation process is more than 1% and less than 100% value of exposure dose of another irradiation process among described the first and second irradiation process also.
Also can, using described the first irradiation process and described the second irradiation process as a pair of, this pair of operation be repeated repeatedly.
Also can carry out semiconductor substrate adjacent in described wafer stacking body stacked, to make between the first interarea separately or between the second interarea toward each other.
The gross thickness of the semiconductor-based plate thickness in described wafer stacking body also comparable described electron ray is thin for the range of described semiconductor substrate.
The gross thickness of the semiconductor-based plate thickness in described wafer stacking body also comparable described electron ray is thin for the half of the range of described semiconductor substrate.
Acceleration energy in described the first irradiation process also makes to import to by described the first irradiation process the acceleration energy that the CONCENTRATION DISTRIBUTION of two crystal defects in the above semiconductor substrate increases towards another interarea from an interarea of described wafer stacking body.
Also can be and comprise: irradiate electron ray to exposure dose monitor in advance, to obtain the operation of obtaining of exposure dose data from an interarea of described wafer stacking body to multiple semiconductor substrates of another interarea; And
Obtain according to this described exposure dose data that operation obtains, required exposure to the identical electron ray of the acceleration energy when exposing to described exposure dose monitor and irradiate the calculation process that number of times calculates, based on this required exposure and irradiate number of times and carry out described the first irradiation process and described the second irradiation process.
Also described in can be, obtain in operation, the exposure dose of the semiconductor substrate nearest electronic radial source from irradiating described electron ray in the semiconductor substrate in described wafer stacking body be made as to x,
Described obtaining in operation, is made as y by the exposure dose of the semiconductor substrate farthest of the electronic radial source from the described electron ray of irradiation in the semiconductor substrate in described wafer stacking body,
In described calculation process, minimum required exposure dose required semiconductor substrate is made as to D, makes the total electron ray irradiation number of times of described the first irradiation process and the second irradiation process become 2D/ (x+y).
Also can be after described the second irradiation process, also comprise that the electron ray of heat-treating irradiates after-baking operation.
In the atmosphere of described electron ray irradiation after-baking operation, also can comprise hydrogen.
Also can be before described electron ray irradiates postprocessing working procedures, also comprise the operation that forms surface electrode.
Also can be, after described electron ray irradiates postprocessing working procedures, also comprise the operation that forms surface electrode.
Described surface electrode also can comprise barrier metal.
Adopt the semiconductor device being formed by above-mentioned manufacture method manufacture.
Invention effect
In the present invention, can realize with low cost the manufacturing method for semiconductor device of characteristic homogenizing.
Brief description of the drawings
Fig. 1 be the related manufacturing method for semiconductor device of embodiments of the present invention 1 want portion's manufacturing procedure picture.
Fig. 2 be embodiments of the present invention 2 related want portion's manufacturing procedure picture.
Fig. 3 be embodiments of the present invention 3 related want the cross section structure figure of portion.
Fig. 4 be embodiments of the present invention 4 related want the cross section structure figure of portion.
Fig. 5 is the distribution map that represents the relative exposure dosage of semiconductor wafer.
Fig. 6 is the distribution map that represents the relative exposure dosage of the related semiconductor wafer of embodiments of the present invention 2.
Fig. 7 is the related performance plots of embodiments of the present invention 5.
Fig. 8 is the related performance plots of embodiments of the present invention 6.
Fig. 9 is the related performance plots of embodiments of the present invention 6.
Figure 10 be represent the manufacture method of the related MOSFET of embodiments of the present invention 1 manufacturing process want portion's cutaway view.
Figure 11 be represent the manufacture method of the related MOSFET of embodiments of the present invention 1 manufacturing process want portion's cutaway view.
Figure 12 be represent the manufacture method of the related MOSFET of embodiments of the present invention 1 manufacturing process want portion's cutaway view.
Figure 13 be represent the manufacture method of the related MOSFET of embodiments of the present invention 1 manufacturing process want portion's cutaway view.
Figure 14 be represent the manufacture method of the related MOSFET of embodiments of the present invention 1 manufacturing process want portion's cutaway view.
Figure 15 be represent the manufacture method of the related MOSFET of embodiments of the present invention 1 manufacturing process want portion's cutaway view.
Figure 16 be represent the manufacture method of the related MOSFET of embodiments of the present invention 1 manufacturing process want portion's cutaway view.
Figure 17 be represent the manufacture method of the related MOSFET of embodiments of the present invention 1 manufacturing process want portion's cutaway view.
Figure 18 is the manufacturing process's flow chart that represents the related manufacturing method for semiconductor device of embodiments of the present invention 1.
Figure 19 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.
Figure 20 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.
Figure 21 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.
Figure 22 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.
Figure 23 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.
Figure 24 is the manufacturing process's flow chart that represents embodiments of the present invention 7 and 8 related manufacturing method for semiconductor device.
Figure 25 is other manufacturing process's flow charts that represent embodiments of the present invention 7 and 8 related manufacturing method for semiconductor device.
Figure 26 is the distribution map that represents the relative exposure dosage of the related semiconductor wafer of embodiments of the present invention 6.
Embodiment
Below, embodiments of the present invention are described.The exposure (dosage etc.) of electron ray that in the following description, will be irradiated to irradiated body (semiconductor wafer etc.) from electron beam irradiation device is as electron ray exposure.In addition, using the dosage suffered irradiated body of illuminated electron ray as exposure dose.This exposure dose is the dosage being determined by the exposure of electron ray and the component of non-irradiation body (structure of atom, molecule) etc.
(execution mode 1)
Manufacturing method for semiconductor device to embodiments of the present invention 1 describes.
Fig. 1 is the related manufacturing method for semiconductor device of one embodiment of the present of invention, is according to wanting portion's manufacturing procedure picture shown in process sequence.
For example, on surface 11, the separator that the two chip semiconductor wafers 10 that make to have the surface element 16 of the mos gate utmost point and the source electrode etc. that have formed multiple longitudinal type MOSFET clip macromolecular material stacks gradually, and puts in special macromolecular material housing.Here, the surface texture that is formed at the MOSFET on surface 11 is the structure very fine with respect to the diameter of semiconductor wafer 10, the description of therefore omitting Surface Structures.Semiconductor wafer has silicon, SiC, GaN etc.In present embodiment 1, use silicon.Thus, form the wafer stacking body 100 of semiconductor wafer 10.The thickness of each chip semiconductor wafer 10 is for example 200 μ m～1000 μ m left and right.In addition, be laminated into make the surface 11 of the second block semiconductor wafer 10 relative with the back side 12 of first semiconductor wafer 10.
Then,, from the face side of the semiconductor wafer 10 in wafer stacking body 100, carry out the first electron ray and irradiate 31.The acceleration energy of the first electron ray irradiation 31 is for example 5MeV left and right.Primary electron radiation exposure is 20kGy, irradiates 10 times.Operation is hereto the operation shown in Fig. 1 (a), as the first electron ray irradiation process.
Then, make the reversion up and down (reversion 20 of housing) of above-mentioned macromolecular material housing, carry out the second electron ray from the back side 12 1 sides of the semiconductor wafer 10 in wafer stacking body 100 and irradiate 32.The acceleration energy irradiating is the 5MeV identical with front operation.In addition, primary electron radiation exposure is 20kGy, irradiates 10 times.Thus, all electron ray exposures become the value identical with front operation.This operation is the operation shown in Fig. 1 (b), as the second electron ray irradiation process.
Afterwards, take out semiconductor wafer 10 from wafer stacking body, the semiconductor wafer 10 taking out is heat-treated.Utilize this heat treatment, near the defect of raceway groove of MOSFET is recovered.Heat treated temperature is for example 320 DEG C～380 DEG C left and right.
After heat treatment step, through the operation of the back of the body surface forming electrode at semiconductor wafer 10, complete wafer fabrication processes.
Then, the operation after electron ray pre-irradiation is described in advance.Figure 10～17th, represents the cutaway view of the manufacture method of semiconductor device more specifically.In present embodiment 1, using semiconductor device as MOSFET, particularly super junction type MOSFET describes.Surface texture is flow to the active region at the back side from the surface of semiconductor substrate by the electric current (principal current) that makes to carry out switch; And surround active region and utilize the depletion layer that is extended to off-state to make the electric field strength increasing at the outer surface of active region the electric field relief areas that reduces, Zhe Liangge region in engagement end region forms.In active region, arrange and flow through the source electrode of principal current and the gate electrode to mos gate utmost point transmitted signal abreast.In addition,, in Figure 10～Figure 17 and the following description, the cross section of semiconductor wafer 10 is cross sections of any a slice semiconductor wafer in above-mentioned wafer stacking body.In addition, although semiconductor is using silicon as example, even carborundum (SiC), gallium nitride (GaN), the such compound semiconductor of GaAs (GaAs) are set up too.
First, as shown in figure 10, form semiconductor substrate 56.For example, using CZ (Czochralski method: Czochralski method) silicon wafer (N-shaped high concentration substrate) as N-shaped drain electrode layer 42, this CZ silicon wafer by the N-shaped such as antimony or arsenic impurity (alloy) high concentration be doping to oversaturated degree till and form.A surface (surface) at N-shaped drain electrode layer 42 is upper, makes the N-shaped drift layer 41 that impurity concentration is lower than N-shaped drain electrode layer 42 carry out epitaxial growth with impurity concentration and the thickness be scheduled to.Alloy is now for example phosphorus.Then,, after the N-shaped layer that makes predetermined thickness carries out epitaxial growth, import p-type alloy (for example boron) by modes such as Implantations selectively to predetermined position.After repeating repeatedly the operation till the Implantation that is epitaxially grown to p-type alloy of this N-shaped layer, apply heat treatment so that its activation.Thus, the super knot drift structure that be provided with abreast the structure of pn side by side 55 of N-shaped layer and p-type layer, forms abreast by N-shaped the first post layer 43, p-type the second post layer 44 is formed on the surface of N-shaped drift layer 41.The impurity concentration of N-shaped the first post layer 43 also impurity concentration of comparable N-shaped drift layer 41 wants high.The thickness of N-shaped drift layer 41 also can be 0 μ m (not forming)～30 μ m left and right.The thickness of N-shaped the first post layer 43 and p-type the second post layer 44 also can be 20 μ m～60 μ m.
Secondly, form the engagement end regions such as not shown guard ring at the periphery of active region.Then, as shown in figure 11, in active region, on the surface of N-shaped the first post layer 43 and p-type the second post layer 44, form selectively gate insulating film 45 and gate electrode 46.Form p-type base layer 48 and N-shaped source layer 49 by Implantation and heat treatment, to make carrying out autoregistration with this gate insulating film 45 and gate electrode 46.Then, utilize known psg film, bpsg film etc. to form interlayer dielectric 47, to make cover gate electrode 46, further selectively etching interlayer dielectric 47 so that the surface of p-type base layer 48 and N-shaped source layer 49 expose, thereby form peristome.Hereto, in active region, form mos gate electrode structure (surface texture).
After interlayer dielectric is annealed, utilize AlSi alloy membrane etc., form source electrode 50, carry out sintering by heat treatment.Now, also can, before forming above-mentioned AlSi alloy membrane etc., form using titanium (Ti), tungsten (W), cobalt (Co) etc. as the barrier metal that contains metal.As mentioned above, form surface electrode (source electrode 50), complete basic MOSFET structure.In addition, hereto to add thermal history as follows: until the annealing of interlayer dielectric 47 is for example more than 900 DEG C, the sintering of source electrode is for example 200～500 DEG C of left and right.In addition, also can be after sintering, utilize polyimide film etc. to form known surface protection film (passivating film).
Then, as shown in figure 12, for example, carry out the first electron ray from the face side of wafer with the dosage of being scheduled to and irradiate 31.Arrow illustrates the direction of irradiating electron ray.
Then, as shown in figure 13, for the wafer that has formed grid defect 51 (being mainly point defect) by the first electron ray irradiation 31, as shown in Figure 1, make wafer housing reversion, carry out the second electron ray and irradiate 32 to irradiate 31 identical dosage with the first electron ray from the rear side of wafer.In Figure 13 × mark is the mark of schematically illustrated grid defect 51, and position and the distribution of grid defect 51 is not shown closely.In addition, the second electron ray irradiates in 32, and it is 31 identical that the direction of illumination of the electron ray from radiographic source to wafer housing and the first electron ray irradiate.The second electron ray irradiates in 32, by making the reversion of wafer housing, thereby carries out electron ray irradiation from another interarea (being rear side Figure 13) of wafer., Tu13Zhong, shows by making to represent that arrow that the second electron ray irradiates and the first electron ray irradiate 31 on the contrary, reverses 20 thereby carried out the housing in Fig. 1.
Then, as shown in figure 14, irradiate 32 by increasing by the second electron ray beyond irradiating 31 at the first electron ray, thereby grid defect 51 is increased, to the whole irradiate wafer obtaining thus, heat-treat (electron ray irradiation after-baking).The object that electron ray irradiates after-baking is, by by utilize the first electron ray irradiate 31 and second electron ray irradiate 32 defect concentrations of grid defect 51 after importing and be reduced to predetermined value, thereby become desired value the reverse recovery time that makes to be built in the diode-built-in (also referred to as parasitic diode, reverse-conducting diode) of MOSFET.Diode-built-in is the diode being made up of p-type base layer 48-p type second post layer 44-n type the first post layer 43-n type drift layer 41-n type drain electrode layer 42 of MOSFET.In addition, under the state of not heat-treating carrying out electron ray irradiation, the density of grid defect 51 is excessive, and the carrier concentration storing in pn structure 55 and N-shaped drift layer 41 side by side in the time of reverse-conducting diminishes, and the value of the forward drop of diode-built-in is higher than desired value.Therefore, utilize electron ray to irradiate after-baking, the density also with grid defect of making 51 reduces and makes the value of forward drop drop to the effect of predetermined value.In addition, also there is following object: form MOSFET raceway groove (be formed on p-type base layer 48 and gate insulating film between interface on electron inversion layer) p-type base layer 48 near defect recover.Thus, can suppress to irradiate by electron ray the variation of produced gate threshold.
Figure 15 represents that irradiating after-baking by electron ray makes the schematic diagram of state after the defect concentration of grid defect 51 reduces.For example utilize the electric furnace that can obtain uniform heat (identical Temperature Distribution) to carry out this electron ray irradiation after-baking.Thus, irradiate the density of grid defect 51 of all wafers after electron ray in the inhomogeneity while that maintains electron ray two sides and irradiate the density distribution obtaining, similarly reduce, consequently, all wafers all possesses grid defect density same degree, desired.
Then, as shown in figure 16, grind 52 for the N-shaped drain electrode layer 42 (said n type high concentration substrate) that is positioned at chip back surface side, thereby make the thickness attenuation of wafer.As the object of this sheet, because the application's semiconductor device is generally equipped on metal frame via scolder, therefore, can make to be relaxed because of the different stress that produce of the thermal coefficient of expansion between semiconductor device and metal frame.In addition, by making the thickness attenuation of current lead-through direction, thus the effect of the resistance (conducting resistance) while also thering is reduction MOSFET conducting.And, by sheet, also there is following effect: reduce the thermal capacity of MOSFET, the heating while more easily making to move is escaped from two surfaces of substrate, reduces the operating temperature of MOSFET.
Finally, as shown in figure 17, form the N-shaped contact layer 54 of high concentration with N-shaped at the back side of wafer, form drain electrode 53.About N-shaped contact layer 54, if for example after the Implantation phosphorus of the back side, injection face is carried out to laser annealing, can be in the case of there is no surface electrode melting or p-type base layer, the pn junction configuration such as pn structure changes such thermal impact side by side, forms low-resistance ohmic contact.In addition, use arsenic at the alloy to N-shaped high concentration substrate, also can save N-shaped contact layer 54.This be because: the saturated concentration of arsenic is higher one more than the order of magnitude than antimony, also can form the ohmic contact between drain electrode 53 even if do not form N-shaped contact layer 54.Above, the two sides of irradiating by electron ray has irradiated to have the super junction type MOSFET60 that uniform defect concentration distributes.
The formation flow process of the semiconductor device of the invention described above has been shown in Figure 18 and Figure 19.Figure 18 is the manufacturing process's flow chart that represents the related manufacturing method for semiconductor device of embodiments of the present invention 1.In Figure 18, form operation (step S1) afterwards at the surface texture forming till interlayer dielectric, the surface electrode that carries out source electrode etc. forms operation (step S2).The surface protection film that then, also can carry out for improving moisture-proof forms operation (step S3).Then, carry out the first electron ray irradiation process (step S4) from the surface of wafer with the dosage of being scheduled to, make the reversion of wafer housing, carry out the second electron ray irradiation process (step S5) of the dosage identical with S4 from the back side of wafer.Then, carry out electron ray with the temperature and time of being scheduled to and irradiate after-baking (step S6), be reduced to desired value maintaining the inhomogeneity density that makes grid defect simultaneously.Afterwards, utilize the substrate foil chemical industry order (step S7) of grinding the thickness attenuation that makes wafer, the back side contact layer that carries out the N-shaped contact layer that forms high concentration on abradant surface forms operation (step S8), finally carries out the such backplate of drain electrode and forms operation (step S9).In addition, N-shaped back side contact layer formation operation S8 uses arsenic and also can save at the alloy to N-shaped high concentration substrate.
In addition also the first electron ray irradiation process (step S4) and the second electron ray irradiation process (step S5) can be exchanged.That is, also can first carry out the second electron ray irradiation process (S5) from the rear side of wafer, then make the reversion of wafer housing, carry out the first electron ray irradiation process (S4) from the face side of wafer.Figure 19 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.As shown in figure 19, after the operation of step S5, carry out the operation of step S4.
And, also the each operation (step) beyond S4 and S5 suitably can be exchanged.For example, also can after the first electron ray irradiation process S4 or the second electron ray irradiation process S5, carry out surface protection film and form operation S3.Figure 20 is other manufacturing process's flow charts of the related manufacturing method for semiconductor device of embodiments of the present invention 1.As shown in figure 20, also can after the first electron ray irradiation process S4 and the second electron ray irradiation process S5, carry out surface protection film and form operation S3, then carry out electron ray and irradiate the step S6 of after-baking operation.
And, also can after electron ray irradiates after-baking operation S6, carry out surface protection film and form operation S3.Figure 21 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.As shown in figure 21, also can be after electron ray irradiate after-baking operation S6, carry out surface protection film and form operation S3.Particularly; utilize formation and the postradiation heat treatment temperature of electron ray (for example 300～350 DEG C) of the surface protection film that the such organic film of polyimides carries out to be in a ratio of same degree or higher (for example 350～400 DEG C), therefore can first carry out each process in that higher processing for the treatment of temperature.Thus, utilize electron ray to irradiate after-baking operation S6 and electron ray can be irradiated to the grid defect density obtaining and be reduced to desired value, and under the treatment temperature of operation after this, prevent the reduction of unforeseeable grid defect density.
In addition, also can make the first electron ray irradiation process S4, the second electron ray irradiation process S5 and electron ray irradiate after-baking S6 overleaf after electrode forming process S9.Figure 22 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.As shown in figure 22, also can make the first electron ray irradiation process S4, the second electron ray irradiation process S5 and electron ray irradiate after-baking S6 overleaf after electrode forming process S9.Thus, the treatment temperature that contact layer forms or backplate forms overleaf, than in the high situation of the treatment temperature of electron ray irradiation after-baking operation S6, is utilized electron ray irradiation after-baking operation S6 electron ray can be irradiated to the grid defect density obtaining and is reduced to desired value.And, under the treatment temperature of operation that can be after electron ray irradiates after-baking operation S6, prevent the reduction of unforeseeable grid defect density.
Or, also can after surface texture forms operation S1 and before surface electrode formation operation S2, carry out.Figure 23 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 1.As shown in figure 23, after surface texture forms operation S1, carry out the first electron ray irradiation process S4, the second electron ray irradiation process S5 and electron ray and irradiate after-baking S6.Afterwards, also can carry out surface electrode and form the later operation of operation S2.In addition, carry out aftermentioned for the order of the operation shown in this Figure 23.In addition, the first electron ray irradiation process S4 in Figure 20～Figure 23 and the second electron ray irradiation process S5 exchange order also can be shown in above-mentioned Figure 19.
The relation of next, irradiating between after-baking and gate threshold for electron ray describes.Irradiate by electron ray, with do not carry out electron ray irradiate time compared with, gate threshold reduce.The countermeasure reducing about this gate threshold, can be by changing in advance the impurity concentration of p-type base layer or the thickness of gate insulating film is dealt with, also can by make to form raceway groove (electron inversion layer) p-type base layer and gate insulating film between the grid defect that produces of near interface recover to deal with.This be because: because the gate threshold of grid defect change may change chronically, may make MOSFET long-term reliability reduce.The reduction of this gate threshold can be irradiated after-baking by electron ray and be recovered, and now can make the atmosphere that electron ray irradiates after-baking become hydrogeneous atmosphere.Its reason is, for the particularly dangling bonds of grid defect of above-mentioned near interface, makes hydrogen become end, can reduce the impact of defect for raceway groove (electron inversion layer).
In addition, irradiate the stage of after-baking at electron ray, if be formed with the barrier metals such as titanium (Ti) on surface electrode (source electrode), the recovery extent of gate threshold dies down.Therefore, in the situation that being formed with titanium etc., also can estimate that gate threshold reduces, the concentration of the Implantation amount while making to form p-type base layer uprises etc., adjusts in advance as described above threshold value.Or, as shown in figure 23, also can make the surface electrode that comprises barrier metal form operation S2 after electron ray irradiates after-baking operation S6.Thus, can be in the case of not being subject to the impact of barrier metal, make near dangling bonds groove become end with hydrogen.In the case of the process sequence shown in this Figure 23, for example, for example, as long as the treatment temperature that makes surface electrode form operation is irradiated after-baking operation S6 treatment temperature (300～380 DEG C) low (200～350 DEG C) than electron ray, can carry out the low temperature sputter of barrier metal etc.Thus, utilize electron ray to irradiate after-baking operation S6 and electron ray can be irradiated to the grid defect density obtaining and be reduced to desired value, and under the treatment temperature of operation after this, prevent the reduction of unforeseeable grid defect density.
Next, concrete technical characterictic of the present invention is described.
Fig. 5 is that the one side side that represents the wafer stacking body 100 of the semiconductor wafer 10 (silicon) from being laminated with any thickness is irradiated the distribution map of relative exposure dosage when electron ray, semiconductor wafer 10 with respect to the cumulative thickness (gross thickness) of semiconductor wafer 10.The relative exposure dosage (hereinafter referred to as relative dosage) of the longitudinal axis is that the exposure dose of the electron ray shadow surface to semiconductor wafer 10 is carried out the value after standardization.As described below, electron ray shadow surface when semiconductor wafer 10 is multiple is the plane of incidence of the semiconductor wafer 10 of the initial incident of electron ray.Electron ray, according to the electronic stopping ability of semiconductor (silicon) and the acceleration energy of electron ray, produces exposure dose and distributes in semiconductor.The distribution shape of this exposure dose is basically identical with the shape of the CONCENTRATION DISTRIBUTION of the crystal defect generating in semiconductor by irradiating electron ray., the CONCENTRATION DISTRIBUTION of crystal defect decides by being irradiated to semi-conductive exposure dose, therefore generally close to Gaussian Profile.Therefore, as shown in Figure 5, if the acceleration energy of electron ray uprises, range Rp also uprises.
In fact, as shown in Figure 5, from the most surface of semiconductor wafer 10 until the front of Rp (several mm left and right), exposure dose (or crystal defect concentration) distributes and can regard the mode monotone increasing with linear function as.Therefore, the semiconductor wafer 10 of the most surface of electron ray incident and approaching in the semiconductor wafer 10 of Rp, exposure dose has 40% difference nearly.The deviation of such exposure dose can be destroyed the uniformity that the defect concentrations in crystals between semiconductor wafer 10 distributes, and becomes the deviation of characteristic.If adopt power MOSFET as present embodiment 1, can impact the characteristic deviation of the conduction loss of diode-built-in (positive voltage drops) and reverse recovery characteristic (reverse recovery time, oppositely recover maximum current etc.).
For fear of the deviation of the exposure dose between the semiconductor wafer 10 in such wafer stacking body 100, as described above, make the reversion up and down of macromolecular material housing, also irradiate electron ray with identical illuminate condition from the rear side of wafer stacking body 100.This illuminating method being called to two sides below, irradiates.In addition, in order to irradiate and to distinguish with two sides, be only called one side irradiation from the electron ray illuminating method of one side by existing.
(execution mode 2)
Fig. 2 is the figure that represents the manufacturing process of the related semiconductor device of execution mode 2.Be with the difference of execution mode 1, overlapping two above, for example the semiconductor wafer 10 of 10 to be to form wafer stacking body 100.
As shown in Figure 5, the sheet number of the semiconductor wafer 10 of wafer stacking body 100 is more, and to irradiate the deviation (difference) of the exposure dose obtaining larger for one side.On the other hand, by carrying out irradiating from the both sides of wafer stacking body 100 the two sides irradiation of electron ray, thereby even if the sheet number in wafer stacking body 100 is more, also can obtain the uniformity of high exposure dose (defect concentrations in crystals distribution).
Particularly, the sheet number of wafer stacking body 100 increases, and the effect that the homogenizing that the defect concentration that obtains distributes is irradiated on two sides of the present invention is better.Under regard to this action effect and describe.Fig. 6 represents with the same terms (acceleration energy, electron ray exposure), electron ray to be carried out to the distribution map that the relative exposure dosage of two sides while irradiating distributes from the face side of wafer stacking body 100 and rear side.Identical with Fig. 5, the value of the longitudinal axis in wafer stacking body 100 the exposure dose of the most surface of the semiconductor wafer 10 of close electronic radial source carried out standardization.The second exposure dose distribution 14 that the first exposure dose distribution 13 that the first electron ray irradiation process S4 obtains and the second electron ray irradiation process S5 obtain is with respect to the roughly middle distributions that become line symmetry of wafer stacking body 100.The exposure dose of the semiconductor wafer 10 in the wafer stacking body 100 after the second electron ray irradiation process S5 finishes distributes and becomes total radiation dose distribution 15.Distributing than the first exposure dose, 13 ranges (Rp2) that become peaked range (Rp1) and the second exposure dose distribution 14 more lean on respectively in the region A of shadow surface one side, total radiation dose 15 constants that distribute, known uniformity is better.Particularly, the amplitude (standard deviation) that exposure dose in the A of region distributes is about 0.5%, and uniformity improves compared with the deviation (40% left and right) while irradiation with one side.
In fact,, although electron ray exposure when electron ray exposure when the irradiating from the first and second one sides in irradiating of two sides is irradiated than one side is only little, even if considered this point, the uniformity that defect concentration when also known two sides is irradiated distributes is high.In addition, carry out aftermentioned for the computational methods of the electron ray exposure in the irradiation of two sides.
During the repeatedly two sides of electron ray is irradiated, also can using the once irradiating from surperficial and from the once irradiating at the back side as a pair of, repeat repeatedly this to irradiating.Or also can be, first carry out repeatedly, from surperficial irradiation, then carrying out the repeatedly irradiation from the back side.Step number in operation is that the latter is less, but should be noted that make from the irradiation number of times of face side identical with the irradiation number of times from rear side.
(execution mode 3)
Fig. 3 is the figure that represents the cross section in the manufacturing process of the related semiconductor device of execution mode 3.Be with the difference of execution mode 1, make the surface of the second chip semiconductor wafer 10 relative with the back side 12 of first semiconductor wafer 10 become the identical back side 12.The advantage of carrying out two sides irradiation is to improve the uniformity that exposure dose (or defect concentrations in crystals) distributes as shown in Figure 6.Here as shown in present embodiment 3, by alternately configuration surface 11 and the back side 12, thereby can further absorb the deviation between wafer.Thus, can further improve the uniformity of element characteristic.
(execution mode 4)
Fig. 4 is the figure that represents the cross section in the manufacturing process of the related semiconductor device of execution mode 4.Be with the difference of execution mode 2, make adjacent semiconductor wafer 10 face respect to one another as Embodiment 3, become between surface 11 or between the back side 12, carry out stacked, thereby form wafer stacking body 100.
By the semiconductor wafer 10 that disposes for example 10 of multiple longitudinal type MOSFET (thickness of 1 is 200 μ m～1000 μ m left and right) as shown in Figure 4, all repeatedly overlapping as surface-back side, the back side-surface, surface-back side, and put in special macromolecular material housing.
Then, will speed up energy and be made as 10MeV, irradiate electron ray.Exposure is: repeat 10kGy 20 times, amount to 200kGy.In the acceleration energy of 10MeV, electron range is about 20mm, if 10 left and right do not reach range, can irradiate fully overlapping all semiconductor wafers 10.Wherein, as shown in Figure 5, although from the most surface side of semiconductor wafer 10 till range is irradiated to exposure dose (or defect concentrations in crystals) increase of semiconductor wafer 10, sharply reduce after range.Therefore,, as the roughly target of the cumulative thickness of semiconductor wafer 10, need to become below range.In the situation that one side irradiates, exposure dose can produce the deviation (inhomogeneous) of 40% left and right in the irradiation most surface wafer of electron ray and the wafer of its end, opposition side.Particularly, the sheet number of semiconductor wafer 10 increases, and cumulative thickness increases, and it is large that the difference that its exposure dose and defect concentration distribute becomes, and inhomogeneities increases.Therefore, for each housing, by wafer stacking body 100 is reversed, and utilize identical electron ray exposure implement two sides irradiate, thereby the increase and decrease of exposure dose cancel out each other, can make characteristic homogenizing.
In addition, as shown in Figure 2, because the operating efficiency of overlapping semiconductor wafer 10 is in one direction better, therefore also can be by overlapping enforcement in one direction, but deviation can slightly larger (0.1% left and right).Therefore, carry out, stricter deviation reduction and management, can adopting present embodiment 4 at needs.
(execution mode 5)
Fig. 7 is the figure that represents the characteristic of the related semiconductor device of execution mode 5.
After concentrating on studies according to inventor, the result of gained is known, if the range Rp (mm) of the electron ray in the silicon substrate of wafer stacking body 100 is made as to y, the acceleration energy E (MeV) of electron ray is made as to x, can utilizes y=5.0 × 10
-7x
4-9.0 × 10
-5x
3+ 0.0046x
2the formula of+2.2591x-0.3599 is described.Chart and obtain Fig. 7 for this formula.That is, if the wafer cumulative thickness of wafer stacking body 100 is made as to W (mm), W is made as electron ray range Rp for example 80%, the acceleration energy of the electron ray while utilizing above formula to calculate this 0.8Rp, the two sides of carrying out electron ray is irradiated.Thus, can disposable (corresponding to the irradiation number of times of required exposure) carry out electron ray irradiation to the multi-disc semiconductor wafer 10 in wafer stacking body 100, and can obtain the high exposure dose defect concentration distribution of uniformity.
Or, also can, according to attainable acceleration energy E in electron beam irradiation device, utilize above-mentioned formula to calculate range Rp, and obtain making wafer cumulative thickness to become that Rp is following, the W of for example 0.8Rp according to this value.
And be preferably, if wafer cumulative thickness W is made as to 50% of range Rp, can further improve the uniformity of defect concentrations in crystals.Particularly, from most surface wafer one side of wafer stacking body 100, until the cumulative thickness of about a few mm, the defect concentration mode of showing greatly linear function that distributes increases.Therefore, for example, in the situation that range is 20mm, by using than the abundant short region of range, below for example 10mm left and right, thereby can improve uniformity.
(execution mode 6)
The irradiation number of times irradiating for the two sides in above-mentioned execution mode 1 and 2 describes.
For wafer stacking body 100, only irradiate to carry out electron ray irradiation by one side, import defect to semiconductor wafer 10, in the case, the exposure dose of the wafer of close electronic radial source is minimum.The object that electron ray irradiates to shorten reverse recovery time or switching time is carried out, and therefore need to carry out electron ray irradiation with the exposure dose that can realize desired characteristic in the semiconductor wafer 10 of the most close electronic radial source.For example, in order to obtain desired characteristic, the situation that the required exposure dose of every a slice of considering semiconductor wafer 10 is 100kGy.Now, as mentioned above, need to irradiate into make in wafer stacking body 100 the exposure dose of the wafer of close electronic radial source become 100kGy.Therefore, the acceleration energy of electron ray is fixed on to predetermined acceleration energy at for example 4MeV in the scope of 10MeV.Utilize this acceleration energy, for an interarea side of wafer stacking body 100, carry out the electron ray that electron ray exposure is 10kGy each time and irradiate, and repeat 10 times.Like this, in wafer stacking body, in the wafer of electronic radial source another interarea side farthest, the exposure dose of electron ray for example becomes 150kGy, becomes the exposure dose of excessive 50kGy.
In order to reduce the difference of above-mentioned exposure dose, the exposure dose needing to be grasped in wafer stacking body distributes.About the confirmation of exposure dose, can consider all to prepare dosimetry chip that monitor uses etc. in the time of each irradiation, pack into together with wafer in wafer stacking body, assess this dosage by irradiating electron ray.But monitor is all prepared in each irradiation, can reduce operating efficiency.
Therefore, can be by irradiating electron ray with lower exposure dose to monitor in advance, thus grasp in advance the distribution proportion of exposure dose.Lower exposure dose refers to the exposure dose of irradiated body in the electron ray exposure that for example in electron beam irradiation device, once can irradiate etc.If consideration makes the fixing situations of illuminate condition such as the exposure dose of acceleration energy, electron ray, the distribution proportion of exposure dose on the depth direction of wafer stacking body fixed, and irrelevant with the size of exposure dose.Thereby, even need to for example be equivalent to the semiconductor device of exposure dose of 600kGy in the case of manufacturing, also without the so high dosage of 600kGy is monitored, as long as obtain this distributed data with 10kGy left and right.The electron ray exposure that is irradiated to monitor for example also can be the minimum irradiation unit of irradiation unit.
Fig. 8 is the figure that the exposure dose of semiconductor wafer 10 while representing that exposure dose in the semiconductor wafer 10 of the most close electronic radial source of wafer stacking body 100 is 10kGy, in wafer stacking body 100 distributes.Here, " bottom side " of transverse axis refers among the semiconductor wafer 10 in wafer stacking body 100 from electronic radial source semiconductor wafer 10 farthest.Known as shown in Figure 8, the exposure dose of each wafer, along with away from electronic radial source, is roughly linearly and increases.
The exposure dose of supposing to be positioned at the semiconductor wafer 10 of the most surface (the most close electronic radial source) of wafer stacking body 100 is x, and the exposure dose of the wafer of bottom surface (from electronic radial source farthest) is y.In exposure dose, with respect to being from the distance of electronic radial source increase linearly, its mean value is roughly (x+y)/2.Therefore, under the condition of x<y, electron ray exposure is once made as to above-mentioned exposure dose x, minimum required exposure dose required desired characteristic is made as to D.Now, if just one side irradiates, the irradiation number of times that required electron ray irradiates is D/x time.On the other hand, in the situation that carrying out two sides irradiation, the irradiation number of times that two sides adds up to becomes the number of times after making D divided by above-mentioned average exposure dose (x+y)/2, therefore becomes 2 × D/ (x+y) inferior.That is, the number of times irradiating with respect to one side, the number of times that two sides is irradiated has lacked the ratio of 2x/ (x+y) <1.Therefore, can not only realize the uniformity between the wafer of exposure dose as described above, and can also irradiate number of times etc. by minimizing and realize cost degradation.
< embodiment >
Specific embodiment in present embodiment 6 is described.Distribute based on the exposure dose obtaining as shown in Figure 8, calculate actual exposure, calculate the irradiation of desired multiple.In example shown in Fig. 8, the mean value of exposure dose (central value) is (10kGy+15kGy) ÷ 2=12.5kGy.This means in two sides is irradiated, irradiate for compared with the electron ray exposure of most surface wafer with utilizing one side, the dosage that once irradiating obtains in fact becomes 1.25 times.That is, compare with the situation of utilizing one side to irradiate the identical irradiation of enforcement, two sides needs only 80% number of times in irradiating.
Fig. 9 is after obtaining the distributed data of Fig. 8, the number of times irradiating according to this data setting electron ray, and the actual wafer illumination dosage carrying out in the wafer stacking body of electron ray while irradiating distributes.As shown in Figure 9, in order to obtain 600kGy, the electron ray exposure that is irradiated to each time silicon during one side is irradiated is made as 20kGy, amounts to the irradiation that needs 30 times.On the other hand, two sides in the first electron ray irradiation process S4, is made as 20kGy by electron ray exposure each time in irradiating, and carries out 12 times and irradiates.Next make the reversion of wafer stacking body, carry out the second electron ray irradiation process S5.In the second electron ray irradiation process S5, electron ray exposure is each time identical with the first electron ray irradiation process S4, is all 20kGy, implements 12 times.Consequently, the exposure dose can irradiate taking one side time on most surface wafer becomes 600kGy as the exposure of 480kGy (20kGy × 12 time) makes stacked body WBR dosage.
Similarly, if each wafer needs the exposure dose of 100kGy, the exposure of most surface wafer can be made as to the exposure corresponding to 80kGy, in the first electron ray irradiation process S4 and the second electron ray irradiation process S5, be made as respectively 40kGy.Similarly, if each wafer needs the exposure dose of 1000kGy, the exposure of most surface wafer can be made as to the exposure corresponding to 800kGy, in the first electron ray irradiation process S4 and the second electron ray irradiation process S5, be made as respectively 400kGy.
Here, if the aggregate values of the exposure dose of the first electron ray irradiation process S4 and the second electron ray irradiation process S5 is that WBR dosage (also referred to as total radiation dose) is identical, also the exposure dose of the first electron ray irradiation process S4 (exposure dose each time, its irradiate number of times) can be made as to the value different from the exposure dose of the second electron ray irradiation process S5 (exposure dose each time, its irradiate number of times).Its reason is: by electron ray is irradiated from only becoming as the irradiation from two sides from the irradiation of one side side, thereby exposure dose must reduce with respect to the deviation (difference) of silicon thickness.As the hypothetical example of simplifying, consider to carry out the electron ray irradiation of exposure dose as 100kGy taking 10MeV from face side as shown in Figure 5 with acceleration energy, the example of being scheduled to, on the other hand, be the situation that 1GeV carries out electron ray irradiation from rear side with the more than 100 times acceleration energy of face side.The exposure dose distribution of considering the electron ray irradiation of 1GeV distributes because range is fully long with respect to the exposure dose of 10MeV, therefore general planar.Be 10kGy even if the exposure dose that the electron ray of 1GeV is irradiated is made as from 10% of the exposure dose of face side, the distribute distribution of the exposure dose that also becomes average 110kGy of the postradiation exposure dose in two sides.In the situation that one side only irradiates, if be 1.5 from the maximum of the relative dosage of the exposure dose of the 10MeV of face side, minimum value is 1.0, and the maximum of relative dosage is 1.5 with the ratio of minimum value.On the other hand, if irradiate electron ray from rear side with exposure dose 10kGy, can improve the exposure dose corresponding to this amount, therefore the maximum of relative dosage and the ratio of minimum value after rear side is irradiated becomes (1.5+0.1)/(1.0+0.1)=1.45, and deviation is reduced reliably.
Figure 26 is the distribution map that represents the relative exposure dosage of the related semiconductor wafer of embodiments of the present invention 6.The distribution of relative dosage when length is shown in dotted line the electron ray that only for example, irradiates any exposure dose a (unit is for example as kGy) from one side side (face side) taking 10MeV.On the other hand, solid line illustrate carry out from face side taking identical acceleration energy exposure dose as the irradiation of 0.5a, from rear side also carry out exposure dose as the irradiation of 0.5a be the distribution of relative dosage of two sides while irradiating.The coefficient of a is described above, is modified to make WBR dosage identical with the WBR dosage that only one side irradiates.
Here the value obtaining after the exposure dose that makes for example, exposure dose from the electron ray of an interarea side (rear side) divided by for example, electron ray from another interarea side (face side) is defined as to dose ratio.The long dose ratio being shown in dotted line is 0.5a/0.5a=1.0.In addition, be more than 1.0 values for dose ratio, if get its inverse, with the situation equivalence of just direction of illumination of face side and rear side being exchanged.Thereby the scope of dose ratio is greater than 0 and be below 1.Dose ratio be 0 refer to one side irradiate.
Short dash line in Figure 26 represents from face side similarly with exposure dose 0.4a, with exposure dose 0.6a, electron ray is carried out to the distribution of relative dosage of two sides while irradiating from rear side.Dose ratio is 1.5.And a chain-dotted line represents from face side similarly with exposure dose 0.66a, with exposure dose 0.33a, electron ray is carried out to the distribution of relative dosage of two sides while irradiating from rear side.Dose ratio is 0.5.The long dotted line irradiating with respect to one side only, relative dosage distribution close to smooth be the exposure dose of face side and rear side identical be that dose ratio is 1.0 situation.On the other hand, even be 1.5 times from the exposure dose of face side in the exposure dose from rear side, similarly in the case of 0.5 times of face side, in the case of the exposure dose from face side is different with exposure dose from rear side, relative dosage distributes compared with one side irradiation, maximum also can diminish with the ratio of minimum value, and the deviation that known relative dosage distributes improves.Like this, if the electron ray of wafer (stacked body) is irradiated and adopts two sides to irradiate, even different from the dose ratio from rear side from face side, deviation also can improve.
In theory, even if for example dose ratio is 0.1 or below it, deviation also can improve as mentioned above.On the other hand, in actual irradiation, the ratio of exposure dose can be the value of 0.1～1 scope, further can be the value of 0.2～1 scope, preferably can be the value of 0.5～1 scope, more preferably can be the value of 0.8～1 scope, further preferably can be the value of 0.9～1 scope.Thus, obviously the improvement degree of the deviation of relative dosage diminishes.The deviation that consequently, can be reflected to reliably the such device electrical characteristics of the reverse recovery characteristic etc. of the diode-built-in of MOSFET reduces.In other words, for example, in multiple wafer stacking bodies, even under the condition different with the exposure dose surperficial from another from surperficial exposure dose, irradiate as long as the irradiation of electron ray is two sides, the deviation of the electrical characteristics of each wafer is also enough little.
(execution mode 7)
Execution mode 7 is the situations that the manufacture method of execution mode 1 are applied to IGBT.Figure 24 is the manufacturing process's flow chart that represents the related manufacturing method for semiconductor device of embodiments of the present invention 7.The process flow of the manufacture method in execution mode 7 is substantially the same with Figure 19 with Figure 18 of execution mode 1, but has following difference.
The first, the in the situation that of IGBT, to semiconductor substrate, use FZ (floating zone method) wafer, CZ wafer, the such high resistivity piece of MCZ (magnetic field CZ method) wafer to cut out wafer, using as N-shaped drift layer.In addition, the second, identical in principle till step S1～S5, but owing to having used piece wafer, therefore, after the second electron ray irradiation process S5, grind to the back side of N-shaped drift layer self (substrate foil chemical industry order S7).The 3rd, after substrate foil chemical industry order S7, for example, import N-shaped alloy from the rear side as abradant surface by the mode of Implantation, form N-shaped electric field stop layer.N-shaped alloy is for example phosphorus, hydrogen etc.Afterwards, carry out electron ray and irradiate after-baking operation S6, N-shaped electric field stop layer is also activated simultaneously.The 4th, contact layer forms in operation S8 overleaf, injects the p-type alloy such as boron of non-N-shaped to abradant surface, for example, carry out laser annealing etc. it is activated, and forms p-type collector layer.Thus, complete IGBT.
In addition, as shown in figure 25, also can after the second electron ray irradiation process S5, carry out electron ray and irradiate after-baking operation S6, after electric field stop layer forms operation S10, carry out separately the heat treatment of electric field stop layer.Figure 25 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 7.Although operation increases, the grid defect can control individually respectively electron ray and irradiates the grid defect that obtains and the formation of electric field stop layer time.
In addition manufacture method that, certainly also can application implementation mode 2～6.In addition, in the time that using selenium, the alloy to N-shaped electric field stop layer is also fine.In this case, make the first electron ray irradiation process S4 and the second electron ray irradiation process S5 and electron ray irradiate after-baking operation S6 after substrate foil chemical industry order S7 and selenium importing and thermal diffusion to abradant surface.This be due to: be 850～950 DEG C of such high temperature for the diffusion temperature that makes selenium diffusion.
By applying above-mentioned manufacture method, thereby in the IGBT that needs high speed motion, can provide the High Speed I GBT that has very evenly and do not have grid defect density devious.
(execution mode 8)
Execution mode 8 is the situations that the manufacture method of execution mode 1 are applied to p-i-n type diode (hereinafter referred to as diode).The manufacturing process's flow chart that represents the related manufacturing method for semiconductor device of execution mode 8 is identical with Figure 24.The process flow of the manufacture method in execution mode 8 is substantially the same with Figure 19 with Figure 18 of execution mode 1, but has following difference.
The first, the in the situation that of diode, to semiconductor substrate, use FZ (floating zone method) wafer, wafer, CZ wafer, the such high resistivity piece of MCZ (magnetic field CZ method) wafer to cut out wafer, using as N-shaped drift layer.In addition, the second, identical in principle till step S1～S5, but owing to having used piece wafer, therefore, after the second electron ray irradiation process S5, grind to the back side of N-shaped drift layer self (substrate foil chemical industry order S7).The 3rd, after substrate foil chemical industry order S7, for example, import N-shaped alloy from the rear side as abradant surface by the mode of Implantation, form N-shaped electric field stop layer.N-shaped alloy is for example phosphorus, hydrogen etc.Afterwards, carry out electron ray and irradiate after-baking operation S6, N-shaped electric field stop layer is also activated simultaneously.The 4th, without the mos gate utmost point, for example, form the anode of p-type on the surface of semiconductor substrate.Thus, complete diode.
In addition, identical with execution mode 7, as shown in figure 25, also can after the second electron ray irradiation process S5, carry out electron ray and irradiate after-baking operation S6, after forming operation S10, electric field stop layer carries out separately the heat treatment of electric field stop layer.Figure 25 is other manufacturing process's flow charts that represent the related manufacturing method for semiconductor device of embodiments of the present invention 7.Although operation increases, the grid defect can control individually respectively electron ray and irradiates the grid defect that obtains and the formation of electric field stop layer time.
In addition manufacture method that, certainly also can application implementation mode 2～6.In addition, in the time that using selenium, the alloy to N-shaped electric field stop layer is also fine.In this case, make the first electron ray irradiation process S4 and the second electron ray irradiation process S5 and electron ray irradiate after-baking operation S6 after substrate foil chemical industry order S7 and selenium importing and thermal diffusion to abradant surface.This be because: be 850～950 DEG C of such high temperature for the diffusion temperature that makes selenium diffusion.
By applying above-mentioned manufacture method, thereby needing high-speed reverse to recover in the diode of action, can provide the high speed diode that has very evenly and do not have grid defect density devious.
The semiconductor substrate that above-mentioned execution mode 1～8 uses also can be silicon epitaxy substrate (makes n-drift layer at thicker n
+drain electrode layer or p
+epitaxially grown substrate on collector layer).Or, even if be not the such super junction type of execution mode 1, but the power MOSFET of the drift layer with same impurities concentration distribution of existing N-shaped, the present application can be applied too.In the case of the power MOSFET of this existing drift structure, as semiconductor substrate, there is high concentration and adulterated the substrate that is formed with N-shaped epitaxial loayer on the CZ of antimony or arsenic or MCZ wafer.Or, also can, for piece wafers such as the FZ of high resistivity, CZ, MCZ, use the wafer of the phosphorus-diffused layer with the high concentration diffuseing to form on single interarea.No matter be in the situation that using which kind of semiconductor substrate (wafer), in the time using this semiconductor substrate, the surface texture formation operation S1 that can record from any of above-mentioned Figure 18～23 comes into effect the manufacture of semiconductor device.
In addition, for IGBT, the execution mode 8 of execution mode 7, also can not adopt piece wafer, as semiconductor substrate, also can use high concentration be formed with the substrate of N-shaped epitaxial loayer on the CZ of adulterated antimony or arsenic or MCZ wafer.The surface texture formation operation S1 that also can record from any of above-mentioned Figure 18～23 in this case, comes into effect the manufacture of semiconductor device.
In addition, can apply semiconductor device of the present invention and be not limited to power MOSFET, IGBT, p-i-n diode etc., also can be applicable to improve the manufacture method of the related all semiconductor devices of the characteristic of bipolar action.
Label declaration
10 semiconductor wafers
11 surfaces
12 back sides
13 first exposure doses distribute
14 second exposure doses distribute
15 total radiation doses distribute
16 surface elements
The reversion of 20 housings
31 first electron raies irradiate
32 second electron raies irradiate
41 N-shaped drift layers
42 N-shaped drain electrode layers
43 N-shaped the first post layers
44 p-type the second post layers
45 gate insulating films
46 gate electrodes
47 interlayer dielectrics
48 p-type base layers
49 N-shaped source layers
50 source electrodes
51 grid defect
52 grind
53 drain electrodes
54 N-shaped contact layers
55 pn structures side by side
56 semiconductor substrates
60 surpass junction type MOSFET
100 wafer stacking bodies
Claims (18)
1. a manufacturing method for semiconductor device, the interarea of the wafer stacking body forming from stacked more than two semiconductor substrate irradiates electron ray, it is characterized in that, and this manufacturing method for semiconductor device has following operation:
Irradiate the first irradiation process of electron ray from an interarea of described wafer stacking body; And
With the acceleration energy identical with acceleration energy in the irradiation of described electron ray, irradiate the second irradiation process of electron ray from another interarea of described wafer stacking body.
2. manufacturing method for semiconductor device as claimed in claim 1, is characterized in that,
The exposure dose of described the second irradiation process is identical with the exposure dose of described the first irradiation process.
3. manufacturing method for semiconductor device as claimed in claim 1 or 2, is characterized in that,
The number of times of described the first irradiation process is identical with the number of times of described the second irradiation process.
4. manufacturing method for semiconductor device as claimed in claim 1, is characterized in that,
The exposure dose of described the second irradiation process is different from the exposure dose of described the first irradiation process.
5. manufacturing method for semiconductor device as claimed in claim 1 or 2, is characterized in that,
The exposure dose of an irradiation process among described the first and second irradiation process is more than 1% and less than 100% value of exposure dose of another irradiation process among described the first and second irradiation process.
6. the manufacturing method for semiconductor device as described in any one in claim 1 to 5, is characterized in that,
Using described the first irradiation process and described the second irradiation process as a pair of, this pair of operation is repeated repeatedly.
7. the manufacturing method for semiconductor device as described in any one in claim 1 to 6, is characterized in that,
Semiconductor substrate adjacent in described wafer stacking body is carried out stacked, to make between the first interarea separately or between the second interarea toward each other.
8. the manufacturing method for semiconductor device as described in any one in claim 1 to 7, is characterized in that,
The gross thickness of the semiconductor-based plate thickness in described wafer stacking body is thinner for the range of described semiconductor substrate than described electron ray.
9. manufacturing method for semiconductor device as claimed in claim 8, is characterized in that,
The gross thickness of the semiconductor-based plate thickness in described wafer stacking body is thinner for the half of the range of described semiconductor substrate than described electron ray.
10. the manufacturing method for semiconductor device as described in any one in claim 1 to 9, is characterized in that,
Acceleration energy in described the first irradiation process is the acceleration energy that the CONCENTRATION DISTRIBUTION that imports to two crystal defects in the above semiconductor substrate by described the first irradiation process is increased towards another interarea from an interarea of described wafer stacking body.
11. manufacturing method for semiconductor device as described in any one in claim 1 to 10, is characterized in that, comprise following operation:
Irradiate electron ray to exposure dose monitor in advance, to obtain the operation of obtaining of exposure dose data from an interarea of described wafer stacking body to multiple semiconductor substrates of another interarea; And
Obtain according to this described exposure dose data that operation obtains, the required exposure to the identical electron ray of the acceleration energy when exposing to described exposure dose monitor and irradiate the calculation process that number of times calculates,
Carry out described the first irradiation process and described the second irradiation process based on this required exposure and irradiation number of times thereof.
12. manufacturing method for semiconductor device as claimed in claim 11, is characterized in that,
Described obtaining in operation, is made as x by the exposure dose of the semiconductor substrate nearest electronic radial source from irradiating described electron ray in the semiconductor substrate in described wafer stacking body,
Described obtaining in operation, is made as y by the exposure dose of the semiconductor substrate farthest of the electronic radial source from the described electron ray of irradiation in the semiconductor substrate in described wafer stacking body,
In described calculation process, minimum required exposure dose required semiconductor substrate is made as to D, makes the total electron ray irradiation number of times of described the first irradiation process and the second irradiation process become 2D/ (x+y).
13. manufacturing method for semiconductor device as described in any one in claim 1 to 12, is characterized in that,
After described the second irradiation process, also comprise that the electron ray of heat-treating irradiates after-baking operation.
14. manufacturing method for semiconductor device as claimed in claim 13, is characterized in that,
In the atmosphere of described electron ray irradiation after-baking operation, comprise hydrogen.
15. manufacturing method for semiconductor device as described in claim 13 or 14, is characterized in that,
Before described electron ray irradiates postprocessing working procedures, also comprise the operation that forms surface electrode.
16. manufacturing method for semiconductor device as described in claim 13 or 14, is characterized in that,
After described electron ray irradiates postprocessing working procedures, also comprise the operation that forms surface electrode.
17. manufacturing method for semiconductor device as described in claim 15 or 16, is characterized in that,
Described surface electrode comprises barrier metal.
18. 1 kinds of semiconductor devices, is characterized in that, this semiconductor device is formed by the manufacture method manufacture described in any one in claim 1 to 17.
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| WO2016028944A1 (en) | 2014-08-19 | 2016-02-25 | Vishay-Siliconix | Super-junction metal oxide semiconductor field effect transistor |
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| RU2606200C1 (en) * | 2015-09-29 | 2017-01-10 | Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Томский политехнический университет" | Diagnostic technique for electric microheterogeneitiesin semiconductor heterostructures, based on ingan/gan |
| DE102015119648B4 (en) * | 2015-11-13 | 2022-11-10 | Infineon Technologies Ag | METHOD OF MAKING A SEMICONDUCTOR DEVICE |
| JP6690198B2 (en) * | 2015-11-16 | 2020-04-28 | 富士電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
| WO2018056233A1 (en) * | 2016-09-20 | 2018-03-29 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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