JPH0348462A - Insulated gate bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress or control the variation of a threshold voltage and effectively prevent the occurrence of latching up by making the number of fixed positive charges in an insulating film balanced with or especially larger than the number of levels at the boundary between the insulating film and first semiconductor area. CONSTITUTION:A voltage is applied across the emitter electrode 7 and gate electrode 6 of an IGBT from a power source 42 so that the gate electrode 6 can become negative. When irradiation is performed as usual with an electron beam which is a kind of ionizing radiation under such condition, electron-positive hole pairs produced in an gate insulating film 5 move along each electric force line and the recombination coefficient drops. Therefore, the voltage of the power source 42 is optimized so that the number of fixed positive charges in the gate insulating film 5 can be balanced with the acceptor type boundary levels at the boundary between the film 5 and a P well area 3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate bipolar transistor (Insulated gate bipolar transistor).
Sulated Gate Blpolar Tran
The present invention relates to IGBTs (hereinafter referred to as IGBTs), and particularly relates to prevention of parasitic silicon risk latch-up, control of threshold voltage changes associated with lifetime control, and improvement of the trade-off relationship between turn-off time and on-resistance.

[Conventional technology]

Generally, an IGBT' device consists of a large number of lGBT elements (
It has a structure in which IGBT cells (hereinafter referred to as IGBT cells) are connected in parallel. Figure 17 shows the conventional n-channel type! 18 is a sectional view showing the structure of a GBT cell, and FIG. 18 is a circuit diagram showing its equivalent circuit.

In FIG. 17, 1 is a P+ collector layer made of a P+ semiconductor substrate, on one main surface of which an N'' epitaxial layer 2A is formed, and on the N+ epitaxial layer 2A, an N'' epitaxial layer 2B is formed. In addition, N
The purpose of forming the +ebitaxial layer 2A is to maintain a predetermined breakdown voltage of the IGBT. In a part of the surface of the N epitaxial layer 2B, a P-well region 3 is formed by selectively diffusing P-type impurities, and in a part of the surface of this P-well region 3, a high concentration N
N+ emitter region 4 is formed by selectively diffusing type impurities. A gate insulating film 5 is formed on the surface of the P well region 3 sandwiched between the surface of the N epitaxial layer 2B and the surface of the N+ emitter region 4, and this gate insulating film 5 is integrated between adjacent IGBT cells. It is also formed on the surface of the N-bitaxial layer 2B.

Gate insulation! A gate electrode 6 made of polysilicon, for example, is formed on the li5, and a P base region 3 and an N
An emitter electrode 7 made of metal such as aluminum is formed so as to be electrically connected to both of the + emitter regions 4 . Note that the gate electrode 6 and the emitter electrode 7 are connected to an insulating film 8.
By forming a multi-layer structure with , all IGBT cells are electrically connected to each other in common. A metal collector electrode 9 is integrally formed on the back surface of the P collector layer 1 for all IGBT cells.

Near the surface of the P well region 3 sandwiched between the N-evitaxial layer 2B and the N-type vine region 4 is an n-channel MOS.
The structure is such that the gate electrode 6 is connected through the gate terminal G.
By applying a positive voltage to
Electrons are transferred from N+ emitter region 4 to N epitaxial layer 2
The B and N+ epitaxial layers 2AC and below are collectively referred to as "N base layer 2". ). !
represents the electron current flowing in this way.

e On the other hand, holes, which are minority carriers, are injected from the P collector layer 1 into the N base layer 2, a part of which recombines with the electrons and disappears, and the rest is formed as a hole current 5 in the P well region 2. flows. In this way, the IGBT basically operates in a bibolar manner, and the conductivity of the N epitaxial layer 2B increases due to the effect of conductivity modulation, resulting in a lower on-state voltage than that of the conventional MOS transistor. It has the advantage of realizing a large current capacity.

However, on the other hand, there is a hole current at turn-off! Since h decreases slowly over time, it is difficult to increase the operating frequency. Therefore, crystal defects are formed in the N base layer 2 by irradiation with an electron beam 40, and the crystal defects are made to function as recombination centers for holes during turn-off, thereby performing so-called lifetime control to increase the operating frequency. At this time, a phenomenon is observed in which the electron beam 40 passes through the gate insulating film 5, thereby forming positive fixed charges in the insulating film 5, thereby lowering the threshold voltage vth. The degree of this decrease increases as the light 1[ increases. Therefore, in order to set the threshold voltage vth after irradiation to a desired value, it is necessary to design the device by estimating the decrease due to electron beam irradiation in advance.

On the other hand, as is clear from the equivalent circuit in Fig. 18, IGB
A parasitic PNPN thyristor structure exists in the T cell.

The parasitic thyristor is an NPN transistor 1 consisting of an N base layer 2, a P well region 3, and an N emitter region 4.
0, and a PNP transistor 1 consisting of a P+ collector layer 1, an N base layer 2, and a P well region 3,
Both transistors 10, 11 are in operation, and their respective current amplification factors α . When the sum of α2 becomes 1, the parasitic i thyristor becomes conductive and latch-up occurs.

Structurally, the thickness of the N base layer 2, which is the base of the PNP transistor 1, is much thicker than the carrier diffusion length.
α2 has a relatively small value. Further, the NPN transistor 10 has a structure in which the emitter and base are short-circuited, making it difficult to turn on. Therefore, latch-up does not occur under normal operating conditions, and the IGBT cell has n-channel MOSFET 12 and PNP transistor 1.
It operates as one composite element. In this case PNP I
-The base current of transistor 11 is n-channel MOSFE
The main current I flowing from the collector terminal C of the IGBT is controlled by the control signal applied to the gate terminal G. It becomes possible to control the Note that, if the current flowing to the emitter terminal E is represented by {circle around (1)}, then the following relationship (IC-IE-Io+■h) (1) holds true.

However, the main current 1c of the IGBT is, for example, at the gate terminal G.
When increased due to some external cause such as noise applied to the electron current I and the hole current e, the electron current I and the hole current e increase. At this time, when the hole current 1h exceeds a certain value, the NPN transistor 10 becomes conductive due to the voltage drop across the resistor RB in the P-well region 3, and the increase in current amplification factor α1 causes α゛1+α2-1 to increase. It is filled and the parasitic Sailisk becomes conductive. In this way, the IGBT enters a latch-up state.

In this state, the main current 1c of the IGBT can no longer be controlled by the control signal applied to the gate terminal G.
Excessive main current I. will flow an unlimited number of times. In order to prevent latch-up, the impurity concentration in the P well region 3 should be increased to lower the resistance, and the ratio of the hole current 1h flowing directly under the N+ emitter suppressing region 4 to the emitter electrode 7 should be reduced. It is necessary.

FIG. 19 is a cross-sectional view showing an example of an IGBT cell structure conventionally employed to prevent latch-up. In this example, a P+ region 13 formed by diffusing F-type impurities of the same conductivity type at a high concentration is provided in the center of a P-well region 3 of an IGBT cell having a rectangular planar shape. As a result, the resistance of the P-well region 3 is lowered, and the ratio of the Hall current 1h flowing through the central part of the P-well region 3 is made relatively larger than the ratio of the Hall current I5 flowing directly under the N+ emitter region 4. transistor 1
This is intended to suppress the transition to the 0 conduction state.

FIG. 20 is an illustrative perspective cross-sectional view showing another example of an IGBT cell structure conventionally employed to prevent latch-up. In this example, the P well region 3 is formed in a stripe shape, and the N+ emitter region 4 is formed in a pattern in which a portion is removed.

As a result, the portion of the P well region 3 from which the N+ emitter region 4 has been removed is bypassed by the hole current h? Road and N
+The ratio of the hole current 1h flowing directly under the emitter region 4 is lowered. A P+ region 13 similar to that shown in FIG. 19 is also provided.

[Problem to be solved by the invention]

By the way, when adopting the structure shown in FIG. 19 above, the depth of the P well region 3 must be made deep, especially in a high voltage IGBT device, so the P+ region 13 with a high impurity concentration must also be made deep. need to be formed. However, since the P+ region 13 is formed by diffusion from the surface, it is inevitable that the impurity concentration distribution becomes lower as the depth increases. cannot be lowered. Also P “
Although it is desirable to form the region 13 in the entire area directly under the N+ emitter region 4, it must be avoided to extend to the channel region directly under the gate electrode 6 since this will change the threshold voltage of the MOSFET 12. Therefore, considering various errors during formation, it is possible to form the P+ region 13 only up to quite a distance in front of the channel region, and the resistance value of the lateral resistance RB2 near the channel can be sufficiently reduced. I can't. From the above, the 19th
The problem with the structure shown in the figure is that it is often insufficient as a countermeasure against latch-up.

On the other hand, according to the structure shown in FIG. 20, it is inevitable that the number of channels will decrease as a result of partially removing the N+ emitter region 4. A decrease in the number of channels is disadvantageous for increasing the current capacity.

In addition, since the planar shape of the IGBT cell is striped, when creating an IGBT device with a large current capacity by connecting many IGBT cells in parallel, it is necessary to increase the density of the cell arrangement compared to the case of rectangular IGBT cells. The problem is that it is inhibited.

Further, as shown in FIG. 17, when lifetime control is performed so that sufficient crystal defects are generated in the N base layer 2 by irradiation with the electron beam 40, the resistance value of the N base layer 2 increases as the crystal defects occur. inevitably increases, and the on-resistance of the IGBT increases. In other words, there is a trade-off relationship between the on-resistance and turn-off time of the IGBT, and there is a problem that this trade-off relationship cannot be said to be optimal at present.

Furthermore, as described above, from the irradiation C of the electron beam 40, I
Since the threshold voltage Vth of the GBT decreases, it is necessary to estimate the decrease and design the device so that the threshold voltage V after irradiation with the electron beam 40 has the desired value, which takes time and effort. Problem points: Yes.

This invention was made in order to solve the above-mentioned problems, and it is possible to suppress or control fluctuations in threshold voltage before and after irradiation with ionizing radiation such as an electron beam, and to prevent the occurrence of latch knob. The objective is to obtain an insulated gate bipolar transistor with a structure suitable for increasing the current capacity and increasing the density of κ cells by optimizing the trade-off relationship between on-resistance and turn-off time while effectively preventing .

[Means to solve the problem]

An insulated gate bipolar transistor according to claim 1 of the present invention includes a first insulated gate bipolar transistor having a first main surface and a second main surface.
a first semiconductor layer of a conductivity type, a second semiconductor layer of a second conductivity type formed on the first main surface of the first semiconductor layer, and a surface of the second semiconductor layer. a first semiconductor region of a first conductivity type selectively formed on the surface of the first semiconductor region; and a second semiconductor region of a second conductivity type selectively formed on the surface of the first semiconductor region.
an insulating film formed on the surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region, and an insulating film formed on the insulating film. a first main electrode formed over the first and second semiconductor regions, and a second main electrode formed on the second main surface of the first semiconductor layer. with respect to the number of positive fixed charges in the insulating film and the number of levels at the interface between the insulating film and the first semiconductor region, whether the former exists in balance with the latter; Or, it is constructed so that there are far more of the former than the latter.

The insulated gate bipolar transistor according to claim 2 further includes: a first semiconductor layer of a first conductivity type having first and second main surfaces; a second semiconductor layer of a second conductivity type formed thereon; a first semiconductor region of a first conductivity type selectively formed on a surface of the second semiconductor layer; a second semiconductor region of a second conductivity type selectively formed on a surface of the semiconductor region; a surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; an insulating film formed on the insulating film, an electrode formed on the insulating film, a first main electrode formed over the first and second semiconductor regions, and an insulating film formed on the insulating film; a second main electrode formed on the second main surface of the layer, the second semiconductor layer is formed on the first main surface of the first semiconductor layer, and the second main electrode is formed on the first main surface of the first semiconductor layer, a third semiconductor layer of a second conductivity type having a relatively high impurity concentration, and a second semiconductor layer having a relatively low impurity concentration and having no crystal defects, which is formed on the third semiconductor layer and having a relatively high impurity concentration.
The fourth semiconductor layer has a conductivity type of .

On the other hand, a method for manufacturing an insulated gate bipolar transistor according to a third aspect of the present invention includes the steps of: preparing a first semiconductor layer of a first conductivity type having first and second main surfaces; a second semiconductor layer on the first main surface of the first semiconductor layer;
a step of forming a second semiconductor layer of a conductivity type;
selectively forming a first semiconductor region of a first conductivity type on a surface of a semiconductor layer; and selectively forming a second semiconductor region of a second conductivity type on a surface of the first semiconductor region. forming an insulating film on the surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; and forming a control electrode on the insulating film. forming a first main electrode over the first and second semiconductor regions; and forming a second main electrode on the second main surface of the first semiconductor layer. and a step of irradiating ionizing radiation from above the control electrode while applying a predetermined voltage between the control electrode and the first main electrode.

Further, the method for manufacturing an insulated gate bipolar transistor according to claim 4 provides a first
a step of preparing a first semiconductor layer of a conductivity type;
forming a second semiconductor layer of a second conductivity type on the first main surface of the semiconductor layer; and forming a first semiconductor region of the first conductivity type on the surface of the second semiconductor layer. selectively forming a second semiconductor region of a second conductivity type on a surface of the first semiconductor region;
forming an insulating film on the surface of the first semiconductor region sandwiched between the semiconductor layer and the second semiconductor region; forming a control electrode on the insulating film; forming a first main electrode over the second semiconductor region; forming a second main electrode over the second main surface of the first semiconductor layer; irradiating first ionizing radiation from above the control electrode with a predetermined voltage applied between the first main electrodes so that the range is near the insulating film; and From the main surface where is formed, the range of the second 71i release η·1 line is within the second semiconductor layer! ! The process includes a process of felling the trees.

Furthermore, the method for manufacturing an insulated gate bipolar transistor according to claim 5 further includes a step of preparing a first semiconductor layer of a first conductivity type having first and second main surfaces; on the first main surface of the second conductivity type.
forming a semiconductor layer of a second conductivity type having a relatively high impurity concentration on the first main surface of the first semiconductor layer. The fourth semiconductor layer includes the steps of forming a third semiconductor layer, and forming a fourth semiconductor layer of a second conductivity type with a relatively low impurity concentration on the third semiconductor layer. a step of selectively forming a first semiconductor region of a first conductivity type on a surface of said first semiconductor region; and a step of selectively forming a second semiconductor region of a second conductivity type on a surface of said first semiconductor region. and the first semiconductor region sandwiched between the fourth semiconductor layer and the second semiconductor region.
forming an insulating film on the surface of the semiconductor region; forming a control electrode on the insulating film; and forming a first main electrode over the first and second semiconductor regions. and forming a second main electrode on the second main surface of the first semiconductor layer, and ionization in which the range in which generated crystal defects are distributed is smaller than the thickness of the third semiconductor layer. The method further includes the step of irradiating radiation from above the main surface on which the second main electrode is formed so that the range is near the center of the third semiconductor layer.

[Effect]

In the insulated gate bipolar transistor according to claim 1, with respect to the number of positive fixed charges in the insulating film and the number of levels at the interface between the insulating film and the first semiconductor region, the former is in balance with the latter. Either there are many, or the former are far more numerous than the latter. When the former exists in balance with the latter, the effects of both cancel each other out, so that the threshold voltage vth does not change. On the other hand, when the former exists much more than the latter, the threshold voltage vth decreases due to the influence of the former. At this time, if the first semiconductor region is formed with a high concentration in order to make it more difficult for a certain parasitic transistor to operate than the second semiconductor region, the first semiconductor region, and the second semiconductor layer, this will lower the threshold voltage. V
th increases. If this increase and the decrease are exactly offset, the threshold voltage vth remains unchanged. Of the third semiconductor layer with a high impurity concentration and the fourth semiconductor layer with a relatively low impurity concentration, crystal defects are provided only in the third semiconductor layer. It does not occur in the semiconductor layer of

On the other hand, in the method for manufacturing an insulated gate bipolar transistor according to the third aspect, ionizing radiation is irradiated from above the control electrode while a predetermined voltage is applied between the control electrode and the first main electrode. At this time, the number of positive fixed charges in the insulating film and the number of positive fixed charges in the insulating film and the first
Regarding the number of levels at the interface with the semiconductor region, the former can be set to exist in balance with the latter, or the former can be set to exist much more than the latter. Thereby, as in the description related to the insulated gate bipolar transistor according to the first aspect, it is possible to prevent the threshold voltage vth from changing.

In the method for manufacturing an insulated gate bipolar transistor according to claim 4, the first ionization is performed so that the range is near the insulating film while a predetermined voltage is applied between the control electrode and the first main electrode. Radiation is applied. At this time, depending on the voltage application situation, the number of positive fixed charges in the insulating film and the number of charges at the interface between the insulating film and the first semiconductor region are such that the former exists in balance with the latter. Alternatively, the former can be set to exist much more often than the latter. Thereby, as in the description related to the insulated gate bipolar transistor according to the first aspect, it is possible to prevent the threshold voltage vth from changing. Moreover, since the second semiconductor layer is hardly irradiated with the first ionizing radiation, lifetime control is not performed by the first ionizing radiation. On the other hand, second ionizing radiation is irradiated from above the main surface of the second main electrode so that the range is within the second semiconductor layer. At this time, lifetime control is performed by providing crystal defects in the second semiconductor layer.

Furthermore, since the second ionizing radiation does not irradiate the vicinity of the insulating film, the threshold voltage Vth does not change due to the second ionizing radiation.

Furthermore, in the method for manufacturing an insulated gate bipolar transistor according to claim 5, the second main electrode is formed to emit ionizing radiation in which the range in which the generated crystal defects are distributed is smaller than the thickness of the third semiconductor layer. In order to irradiate from above the main surface of the third semiconductor layer so that the range is near the center of the third semiconductor layer,
The third semiconductor layer, which has a relatively high impurity concentration, constitutes the second semiconductor layer.
Of the semiconductor layer and the fourth semiconductor layer having a relatively low impurity concentration, crystal defects are provided only in the third semiconductor layer. Therefore, the fourth semiconductor layer does not suffer from any harmful effects caused by the provision of crystal defects.

〔Example〕

FIG. 1 is a sectional view showing a first embodiment of an IGBT according to the present invention. In FIG. 1, 1 is a P+ collector layer made of a P+ semiconductor substrate, and on the other hand, N is on the main surface.
+Ebitaxial layer 2A is formed, and further N+
An N epitaxial layer 2B is formed on the epitaxial layer 2A. The N+ epitaxial layer 2A and the N-evitaxial layer 2B form the N base layer of the IGBT (hereinafter referred to as the N+ epitaxial layer 2A).
and the N epitaxial layer 2B are collectively referred to as the "N base layer 2." ). A P-well region 3 is formed in a part of the surface of this N-evitaxial layer 2B by selectively diffusing P-type impurities, and a P-well region 3 is further formed in a part of the surface of this P-well region 3. An N+ emitter region 4 is formed by selectively diffusing highly concentrated N type impurities. A gate insulating film 5 is formed on the surface of the P well region 3 sandwiched between the surface of the N epitaxial layer 2B and the surface of the N+ emitter region 4.
are also formed on the surface of the N epitaxial layer 2B so as to be integrated between adjacent IGBT cells. A gate electrode 6 made of polysilicon, for example, is formed on the gate insulating film 5, and an emitter electrode 7 made of a metal such as aluminum is electrically connected to both the P base region 3 and the N+ emitter region 4. It is formed. Note that the gate electrode 6 and the emitter electrode 7 have a multilayer structure with an insulating film 8 interposed therebetween, so that they are electrically connected in common to all IGBT cells. P
A metal collector electrode 9 is provided on the back surface of the collector layer 1.
It is formed integrally with the GBT cell. That is, the IGBT according to this embodiment is different from the conventional IGBT shown in FIG.
It has the same structure as the conventional IGBT, and its basic operation is also the same as that of the conventional IGBT.

A voltage is applied by a power source 42 between the emitter electrode 7 and the gate electrode 6 of the IGBT having such a structure so that the gate electrode 6 becomes negative. In this state, when irradiation with an electron beam 40, which is a type of ionizing radiation, is performed as before, each electron-hole pair excavated in the gate insulating film 5 moves along the lines of electric force, and the recombination rate decreases. do. Therefore, the gate insulating film 5
Although the positive fixed charges inside increase, the electrons that have similarly moved along the lines of electric force form an acceptor type interface level at the interface between the gate insulating film 5 and the P-well region 3. Since the positive fixed charge and the acceptor type interface state cancel each other out, if the voltage from the power supply 42 is optimized so that both are balanced, the threshold voltage Vth can be reduced before and after irradiation with the electron beam 40. can be suppressed. Therefore, as in the past, the threshold voltage by irradiation with the electron beam 40 is determined at the element design stage.
There is no need to anticipate the decrease in th in advance, and lifetime control with higher controllability can be realized.

FIG. 2 is a sectional view showing a second embodiment of the IGBT according to the present invention. In Figure 2, the basic element horizontal structure is
It is the same as FIG. 1 except for the P-well region 3. In other words, the P well region 3 in FIG. 2 is composed of an N+ emitter region 4, a P base region 3, and an N base layer 2, so that the internal resistances R and RB2 are reduced to such an extent that they do not affect the operation of the parasitic silicon risk. Parasitic NPN } is formed at a sufficiently high concentration so as to disable the operation of the transistor. Therefore, the concentration of the P-well region 3 directly under the gate insulating film 5 also increases, so that the threshold voltage Vth increases.

A voltage is applied by a power source 42 between the emitter electrode 7 and the gate electrode 6 of the IGBT having such a structure so that the gate i-pole 6 becomes positive. In this state, when irradiation with an electron beam 40, which is a type of ionizing radiation, is performed as before, each electron-hole pair generated in the gate insulating film 5 moves along the lines of electric force, and the recombination rate decreases. do. Therefore, although the fixed charge in the gate insulating film 5 increases, electrons are quickly absorbed into the gate electrode 6, and as in the first embodiment, an acceptor type is formed at the interface between the gate insulating film 5 and the P-well region 3. Does not form interface states. The increase in positive fixed charge is the threshold voltage v
Since this leads to a decrease in th, an increase in threshold voltage vth due to an increase in the concentration of P well region 3 is offset. Since the recombination rate of electrons and holes can be controlled by the electric field strength in the gate insulating film 5, by optimizing the voltage applied by the power supply 42, the recombination rate of electrons and holes can be controlled. A desired threshold voltage Vth can be obtained after 1140 irradiations. Furthermore, since the electron beam 40 also performs lifetime control in the N base layer 2, which is its original purpose, lifetime control and vth control can be performed simultaneously in this step.

FIG. 3 is a sectional view showing a third embodiment of the IGBT according to the present invention. - In FIG. 3, the basic element structure is the same as in FIG. 1 except for the P-well region 3. Third
The P-well region 3 shown in the figure is formed with a sufficiently high concentration as in the embodiment shown in FIG. 2 so that the internal resistances R 1 and RB2 affect the operation of the parasitic thyristor and are reduced to an unprecedented level. For this reason, the concentration of the P-well covering region 3 directly under the gate insulating film also increases, and as a result,
Threshold voltage vth increases.

In this embodiment, a mask 36 is formed on the emitter electrode 7, and a low-energy light ion beam 41a, which is a type of ionizing radiation beam whose range is near the gate insulating film 5, is transmitted through the mask 36. , selectively irradiates only the gate electrode 6 portion. For example, protons (hydrogen ions H+) may be used as the light ion beam 41a. During irradiation, a voltage is applied between the emitter electrode 7 and the gate electrode 6 by the power source 42 so that the gate electrode 6 becomes positive. The low-energy light ion beam 41a generates electron-hole pairs in the gate insulating film 5, but each of these moves along the lines of electric force, and the recombination rate decreases. Therefore, although the positive fixed charge in the gate insulating film 5 increases, the electrons are quickly absorbed into the gate electrode 6, and no acceptor type physical level is formed at the interface between the gate insulating film 5 and the P-well region 3. . Since an increase in positive fixed charge leads to a decrease in threshold voltage Vth, P
The increase in the threshold voltage th due to the increase in concentration in the well region 3 is canceled out. Since the recrystallization rate of electrons and holes can be controlled by the electric field strength in the gate insulating film 5, by optimizing the voltage applied by the power supply 42, the desired rate of recrystallization can be achieved after irradiation with the low-energy light ion beam 41a. threshold voltage v
th can be obtained.

The range of the low energy light ion beam 41a is gate insulated s5
Strictly in position! P well area 3 by controlling IJ
Ideally, it would not affect the P-well region 3 and the N-base layer 2, but it is thought to affect the P-well region 3 and near the very surface of the N-base layer 2 due to range fluctuations. However, the amount of ion irradiation required to generate enough electron-hole pairs to obtain the above-mentioned effect in the gate insulating film 5 is significantly higher than the amount of ion irradiation when performing normal lifetime control. Since it is small, its effect can be ignored.

Thereafter, 4 lb of high-energy light ion beam having a range into the N base layer 2 is irradiated from the collector electrode 9 side to perform precise lifetime control.

Lifetime control using this method has a more improved on-voltage (collector-emitter saturation voltage) - turn-off time t trade-off relationship CES than the above-mentioned lifetime control using an electron beam.
of'(' relation can be realized. In other words, according to this embodiment, it is possible to manufacture an IGBT in which latch-up prevention and an improved vCCS "off" trade-off relationship are realized. .

Note that by setting the concentration of the P well region 3 to the level of the first embodiment, applying a voltage so that the gate electrode 6 becomes negative, and performing irradiation with the low energy light ion beam 41a, the concentration of the first embodiment can be improved. It is also possible to suppress the decrease in the threshold voltage vth according to the stated principle.

FIG. 4A to FIG. 4D are l according to the above-mentioned first to third embodiments.
FIG. 3 is a cross-sectional view showing the GBT manufacturing procedure. Note that the P-well region 3 in this case includes a first P-well region 3a with a relatively low impurity concentration and a shallow depth, and a shallow depth of the first P-well region 3a, similar to the conventional IGBT shown in FIG. It consists of a second P well region 3b formed in the center and having a relatively high impurity concentration and a deep depth.

First, as shown in FIG. 4A, an N+ epitaxial layer 2A having a thickness of about 10 μm is epitaxially grown on the first main surface of a P+ collector layer 1 made of a P+ silicon substrate. Then, on this N epitaxial layer 2A, 50 to 1
A N 2 epitaxial layer 2B having a thickness of several 00+ μm is epitaxially grown. For example, a silicon oxide film is formed on this N 2 epitaxial layer 2 and patterned to form a mask 33. Then, by selectively ion-implanting P-type impurities such as boron into the N epitaxial layer 2A through this mask 33 and further diffusing them, the surface concentration is increased to 5×10l6 to 1×10l9clT+.
A second (7) P well 'iiJ'i region 3b of about -3 is formed.

Next, as shown in FIG. 4B, mask 33 is removed and another mask 34 is formed. Then, by selectively ion-implanting P-type impurities such as boron into the N epitaxial layer 2B through this mask 34 and further diffusing them, a second
The first well region 3b has a lower concentration and a shallower depth than the P well region 3b.
A P well region 3a is formed. In this way, a P-well region 3 is formed in which a second P-well region 3b is provided in the center of the first P-well head region 3a.

Next, as shown in FIG. 4C, the mask 34 is removed and an oxide film and a polysilicon film are formed on the entire surface instead, and these are patterned to form a gate insulating film 5, a gate electrode 6, and a polysilicon layer 6a. form.

Next, by selectively diffusing an N type impurity such as phosphorus into the P well region 3 using the gate electrode 6 and the polysilicon layer 6a as a mask, the N emitter region 4 is formed in a self-aligned manner.

Next, as shown in FIG. 4D, after removing the polysilicon layer 6a, an insulating film 8 is formed over the entire surface and patterned. Then, by forming and patterning a metal layer over the entire surface, an emitter electrode 7 electrically connected to the N+ emitter region 4 and a gate extraction portion 37 electrically connected to the gate electrode 6 are formed. After that, according to the procedure explained in connection with FIGS. 1 to 3, the electron beam 40 or the low energy light ion beam 41a, the high energy light ion beam 41
Perform irradiation according to b.

Next, a fourth example, which is a modification of the third example, will be described. FIGS. 5A and 5B are cross-sectional views showing a method of manufacturing an IGBT according to the fourth embodiment.

First, as shown in FIG. 5A, a mask 35 is formed on one main surface of the N-substrate 52, and high-concentration gas is diffused through this mask 35, so that the surface concentration is 102°c111-3.
A P+ collector region 1a of about 100% is formed. Next, the 5th B
As shown in the figure, after removing the mask 35, another mask 36 is formed and high concentration gas is diffused to form the N collector region 1b. The subsequent steps are performed in the same manner as the steps shown in FIGS. 4A to 4D (however,
The N-substrate 52 is replaced by the N base layer 2. ).

FIG. 6 shows an IGBT manufactured in this manner. The structure of the IGBT shown in the same figure and the conventional IGBT shown in FIG.
The difference from the structure of BT is that part of the collector region is made into an N+ layer 1b, and the N base layer 2 is replaced with an N- substrate 52. This N+ layer 1b is an N-substrate base layer 52.
It is connected to the P+ collector region 1a on the collector surface by the metal κ wire 9, and has a structure in which the N-substrate base layer 52 and the P+ collector region 1a are short-circuited. In this structure, the collector current! . Due to the effect that the proportion of electron current I in the electron current I increases, or e decreases the hole injection efficiency from the collector side, the conventional buffer layer (N.
．． +Equivalent to the epitaxial layer 2A) optimization and lifetime control. This has the advantage that high-speed turn-off can be achieved without using such a method.

For this so-called short-collector IGBT, this fourth
Furthermore, in order to effectively prevent latch-up, the P-well region 3 is formed with a sufficiently high concentration so that the internal resistances R and R82 are reduced to a level that does not affect the operation of the parasitic thyristor. There is. For this reason, gate insulation ll! P well area 3 directly below 5
By increasing the concentration of , the threshold voltage Vth increases. Similarly to the third embodiment, a mask 36 is formed on the emitter electrode 7, and a low energy light ion beam 41a whose range is near the gate insulating film 5 is directed through the mask 36 to the gate electrode 7. Selectively irradiate only the part 6. During irradiation, as in the third embodiment, the emitter electrode 7
A voltage is applied between the gate electrode 6 and the gate electrode 6 by a power source 42 so that the gate electrode 6 becomes positive. By optimizing the voltage applied by this power source 42, as described above in connection with the third embodiment, the low energy light ion beam 4
After the irradiation of 1a, the increase in the threshold voltage vth due to the concentration increase in the P well region 3 is offset, and the desired threshold voltage v
th can be obtained. Note that, as described above, the influence of fluctuations in the range of the low-energy light ion beam 41a can be ignored.

According to this fourth embodiment, with the collector short-circuited structure, V
-t } The trade-off relationship is optimized and CIES
of'r effectively prevents latch-up while maintaining high integration, and lowers the threshold voltage Vth by low-energy light ion beam irradiation.
An optimized IGBT can also be realized.

FIG. 7 is a sectional view showing a fifth embodiment of the IGBT according to the present invention. In FIG. 7, the basic element structure is the same as in FIG.

FIG. 8 is a graph showing an example of the concentration profile of the IGBT shown in FIG. As shown in the figure, the thickness of the P well region 3 is 10.6 μm SN epitaxial layer 2B.
The thickness of the N+ epitaxial layer 2A is 98.9 μm, and the thickness of the N+ epitaxial layer 2A is 13.5 μm.

From the collector electrode 9 side of the tGBT having such a structure,
By aiming the light ion beam 50 so that its range is located near the center of the N+ epitaxial layer 2A, crystal defects are generated only in the N+ epitaxial layer 2A, and lifetime control is performed precisely. The advantages and various desirable conditions of this embodiment are discussed in detail below.

In the embodiment shown in FIG. 7, the light ion beam 50 is, for example, 21i1! Helium ions (H e 2'') of i may be used. FIG. 9 is an explanatory diagram illustrating a step of irradiating helium ions 51 into the N + epitaxial layer 2A of FIG. 7. For convenience, N in Figure 7
Illustrations of the P well region 3, gate electrode 5, etc. formed in or on the epitaxial layer 2B are omitted. Further, the steps for manufacturing the IGBT having the structure shown in FIG. 7 are as shown in FIGS. 4A to 4D.

As shown in FIG. 9, the IGBT 60 shown in FIG.
60 is fixed in the recess, and the inside of the recess is fixed with 10-3~
1 By maintaining a vacuum of about 0-'Torr, the IGB
T60 is in a vacuum insulated state. In addition, aluminum foil 62
also serves as an energy absorber when irradiating helium ions 51 into the IGBT 60.

With the helium ion 51 installed in this way, N
+Irradiate so that the range is located near the center of the epitaxial layer 2A.

FIG. 10 is a graph showing the measurement results of the acceleration energy of hydrogen ions and helium ions (H+) and the range in silicon. Note that the thickness of the aluminum foil 62 in FIG. 9 at the time of this measurement was 20 μm. General IGBT
In 60, the thickness of the P+ collector layer 1 is 270 μm,
Since the thickness of the N epitaxial layer 2A is about 10 μm, in order to obtain a range of 275 μm near the center of the N+ epitaxial layer 2A, an acceleration of 2 5 M e V is required as shown in FIG. All you have to do is irradiate it with energetic helium ions. This is a sufficiently practical acceleration energy value. On the other hand, hydrogen ions require less acceleration energy than helium ions, as is clear from Figure 10, but as will be clear from the following explanation, their use in this example is limited. Become. Although not shown in FIG. 10, ions 1 that are heavier than helium ions, such as lithium ions (L 2 ), require greater acceleration energy than helium ions as they become heavier. If the acceleration energy is 1 or too large, there will be restrictions from a practical standpoint.

FIG. 11 is a graph showing the crystal defect distribution, which is the range in which crystal defects generated by ion irradiation are distributed. As shown in the figure, crystal defects are caused by the range D of irradiated ions.
It becomes a local distribution with a peak near . In other words, when ion irradiation is performed, the width shown in the figure (hereinafter referred to as "
Most of the crystal defects (mainly vacancies) are present in W (referred to as the half width of the defect distribution peak).

FIG. 12 is a graph showing the relationship between the average range D of hydrogen ions and helium ions in silicon and the half width W of the defect distribution peak. As mentioned above, the general IGB
At T60, the thickness of P+ collector layer 1 is approximately 270 μmsN
+The thickness of the epitaxial layer 2A is approximately 10 μm. According to Figure 12, the half width W of the defect distribution peak caused by ions implanted into silicon at a range of approximately 275 μm is approximately 16 μm for hydrogen ions and approximately 9 μm for helium ions.
m. Therefore, in order to generate crystal defects only in the N+ epitaxial layer 2A having a thickness of about 10 μm, it is necessary to implant helium ions instead of hydrogen ions. N
+When the epitaxial layer 2A is thick, hydrogen ions can be used.

Although not shown in FIG. 12, ions heavier than helium ions can be used in place of helium ions because the defect distribution peak half width W is smaller than that of helium ions.

Table 1 shows irradiation with helium ions while varying the irradiation amount.
After that, annealing properties [temperature 300°C, atmosphere N,
6 hours], the turn-off time is 1.2 when the range position is set near the center of the N epitaxial layer 2A and when it is annealed within the N epitaxial layer 2B. CB showing the measurement results of (μSoff' ec) and on-resistance V (V)
This is the S table. Further, FIG. 13 is a graph showing the trade-off relationship between turn-off time and on-resistance in both cases based on Table 1. In the figure, the curve with the symbol N+ is the trade-off relationship between turn-off time and on-resistance when helium ions are implanted near the center of the N+ epitaxial layer 2A, and the curve with the symbol N is the trade-off relationship between the turn-off time and on-resistance when helium ions are implanted near the center of the N+ epitaxial layer 2A. Turn-off when helium ions are implanted into the N-evitaxial layer 2B As shown in Table 13, it is better to implant helium ions into the N-evitaxial layer 2A.
It can be seen that the trade-off relationship between turn-off time and on-resistance is improved compared to implanting helium ions into B. The reason for this is presumed to be as follows. That is, the eighth
As shown in the figure, the concentration of N+ epitaxial layer 2A is N
The concentration is sufficiently higher than that of the single epitaxial layer 2B. In other words, the resistance value of the N+ epitaxial layer 2A is sufficiently lower than the resistance value of the N- epitaxial layer 2B, and the increase in resistance due to the generation of crystal defects can be ignored. Therefore, when the IGBT is turned on, the N
The degree of inhibition of the conductivity modulation occurring in B can be reduced compared to when crystal defects are directly generated in the same layer 2B.

In addition, since electrons flowing from the N base layer 2 to the P+ collector layer 1 at the initial stage of turn-off tend to cause holes to be injected from the P+ collector layer 1 to the N base layer 2, these holes can be captured quickly. In order to achieve this, it is convenient to generate crystal defects in a concentrated manner in the N+ epitaxial layer 2A, which is located closest to the P collector layer 1 in terms of position. Note that the same applies to implantation of ions other than helium ions, such as hydrogen ions and lithium ions.

Table 2 shows the results of 2 An IGBT having an N+ epitaxial layer 2A with a thickness of 10 μm and an N+ epitaxial layer 2A with a thickness of 20 μm.
3 is a table showing measurement results of turn-off time and on-resistance of each IGBT having the following characteristics. Further, FIG. 14 is a graph showing the trade-off relationship between the turn-off time and on-resistance based on Table 2. In addition, in the same figure, the curve 1l10 is the IGBT having the N+ epitaxial layer 2A with a thickness of 10 μm, and the curve 220 is the second table of the measurement results of the IGBT having the N+ epitaxial layer 2A with the thickness of 20 μm.As shown in the same figure, Similarly, even if helium ions are implanted into the N+ epitaxial layer 2A, a 10 μm thick N
The IGBT with the epitaxial layer 2A is better than the IGBT with the N+ epitaxial layer 2A with a thickness of 20 μm.
The trade-off relationship between turn-off time and on-resistance has been improved.

The thicker the N epitaxial layer 2A is, the more P4
This is because the hole injection efficiency from the collector layer 1 is reduced and the thickness of the layer 2A already affects the on-voltage of the IGBT before ion irradiation.

That is, in order to increase the hole injection efficiency, it is desirable that the thickness of the N + epitaxial layer 2A be thin, but on the other hand, in order to maintain the withstand voltage, crystal defects are locally generated in the same layer 2A due to ion irradiation. It is necessary to ensure a sufficient thickness for this purpose, and it is necessary to determine the thickness of the N+ epitaxial layer 2A by taking these conditions into consideration.

Tables 3A to 3D show that an IGBT having an N+ epitaxial layer 2A with a thickness of 20 μm is subjected to electron beam, hydrogen ion,
After forming crystal defects in the N+ epitaxial layer 2A by irradiating helium ions (when irradiating hydrogen ions and helium ions, the range is set near the center of the N+ epitaxial layer 2A), annealing conditions [temperature 300°C. Atmosphere N,
This is a table showing the measurement results of the turn-off time and on-resistance when annealing was performed for 2 hours (6 hours only when irradiated with helium ions), of which Table 3A shows no irradiation, Table 3B shows when irradiated with an electron beam, Table 3C is a table showing the measurement results when irradiated with hydrogen ions, and Table 3D is a table showing the measurement results when irradiated with helium ions. Based on these Tables 3A to 3D, the trade-off relationship between on-resistance and turn-off time is graphed in FIG. 15. As shown in Table 3A and Table 3D in FIG. It can be seen that the trade-off relationship between the on-resistance and turn-off time of the IGBT is favorable in the order of hydrogen ion irradiation and electron beam irradiation. In the case of electron beam irradiation, the crystal defects formed are l G
Since it covers the entire BT, a very good trade-off relationship cannot be obtained. The reason why helium ion irradiation has a better trade-off relationship than hydrogen ion irradiation is that the crystal defect distribution (
This is presumed to be due to the difference in the defect distribution peak (proportional to the half width W). That is, in an IGBT irradiated with hydrogen ions having a relatively wide crystal defect distribution, some crystal defects occur not only in the N 2 epitaxial layer 2A but also in the N 2 epitaxial layer 2B. In contrast, in an IGBT irradiated with helium ions with a relatively narrow crystal defect distribution, crystal defects are definitely present in the N+ epitaxial layer 2.
Occurs only in A. As a result, IG that emitted hydrogen ions into the fish
It is presumed that the trade-off relationship between on-resistance and turn-off time of the BT has deteriorated compared to the IGBT that has been irradiated with helium ions. As a result, although not shown in FIG. 15, ions such as lithium ions, which are heavier than helium ions and have a narrow crystal defect distribution, are thought to exhibit the same effect as helium ions.

Table 4 shows two IGBs whose defect distribution peak half width W was changed due to different device thicknesses (as a result, the distance to the center of the N1 epitaxial layer 2A was different).
N+ epitaxial layer 2 with a thickness of 10 μm for each T
3 is a table showing measurement results of turn-off time and on-resistance when helium ions were irradiated multiple times with different doses during A.

All annealing was performed under N2 atmosphere at 30,0"C,5
It was done under the time constraints.

Figure 16 is based on Table 4, and shows the trade-off between evening-off time and on-resistance. When helium ions are implanted into the N+ epitaxial layer 2A formed in each, the half width W of the defect distribution peak differs (8.8 μm as shown in Table 4), as is clear from FIG. and 3.5 μm), a difference occurs in each crystal defect distribution. However, as shown in FIG. 16, the trade-off relationship between turn-off time and on-resistance is almost the same in both cases. This seems to be due to crystal defects occurring only in the N 2 epitaxial layer 2A in either case. In other words, if crystal defects can be formed only in the N+ epitaxial layer 2A, there will be no change in the trade-off relationship between turn-off time and on-resistance, regardless of the device thickness.

The results of the above considerations can be summarized as follows.

(1) The use of heavy ions is subject to practical limitations in terms of acceleration energy. (Figure 10) (2) The heavier the ion, the narrower the crystal defect distribution. (FIG. 12) (3) The degree of improvement in the trade-off relationship between turn-off time and on-resistance is greater when the light ion beam 50 is implanted into the N+ epitaxial layer 2A than into the N+ epitaxial layer 2B. (Figure 13) (4) N+ epitaxial layer 2A
As the thickness increases, the degree of improvement in the trade-off relationship described above decreases. (FIG. 14) (5) The above trade-off relationship is best improved when crystal defects are generated only in the N+ epitaxial layer 2A. (FIG. 15) (6) N Even if the crystal defect distribution in the epitaxial layer 2A becomes narrower, the degree of improvement in the above trade-off relationship remains the same. (Fig. 16) In a general IGBT having a P+ collector layer 1 with a thickness of about 270 μm and an N+ epitaxial layer 2A with a thickness of about 10 μm, the above (2),
Considering (3), (4), (5), and (Fi), it is possible to implant helium ions and heavier ions so that their range is located near the center of the N+ epitaxial layer 2A. is desirable. However, for ions heavier than helium ions, the above restriction (1) must be taken into consideration. When the N+ epitaxial layer 2A is considerably thick, hydrogen ions can also be used. However, in this case, the drawback (4) above occurs.

Further, the IGBT of this fifth embodiment has a gate insulating film 5
Since the device is manufactured without ever being irradiated with ionizing radiation, there is no change in the threshold voltage before and after lifetime control, as in the third embodiment.

Furthermore, if the helium ion irradiation according to the fifth embodiment is applied to the irradiation with the 4 lb high-energy light ion beam of the third embodiment, the controllability of the lifetime control in the third embodiment is further improved. Improved.

〔Effect of the invention〕

As explained above, according to the IGBT according to claim 1, regarding the number of positive fixed charges in the insulating film and the number of levels at the interface between the insulating film and the first semiconductor region, the former is The former is present in balance with the latter, or the former is present significantly more than the latter, while claim 3
According to the IGBT manufacturing method described, the ga limiting voltage and the first
By irradiating ionizing radiation from above the control electrode with a predetermined voltage applied between the main electrodes, the number of positive fixed charges in the insulating film and at the interface between the insulating film and the first semiconductor region are Regarding the number of levels, it is possible to set the former to be in balance with the latter, or to have a much larger number of the former than the latter, so it is possible to An insulated gate bipolar transistor that can suppress fluctuations in threshold voltage before and after irradiation, effectively prevent latch-up, and has a structure suitable for large current capacity and high density cell arrangement. It has the effect of being able to obtain

Furthermore, according to the IGBT manufacturing method according to claim 4,
The threshold m voltage vth is increased by the step of irradiating the first ionizing radiation.
Since the lifetime can be controlled independently by the step of illuminating the second ionizing radiation q.1 line,
In addition to the effects described above, accurate setting of the threshold f7M voltage and lifetime control with good controllability can be performed.

On the other hand, according to the IGBT according to the second aspect, of the third semiconductor layer having a relatively high impurity concentration and the fourth semiconductor layer having a relatively low impurity concentration that constitute the second semiconductor layer, the third semiconductor layer constitutes the second semiconductor layer. Since crystal defects are provided only in this layer, the adverse effects of providing crystal defects do not occur in the fourth semiconductor layer, which has the effect of optimizing the trade-off relationship between turn-off time and on-resistance. be.

Further, according to the method for manufacturing an IGBT according to claim 5,
Ionizing radiation is applied from above the main surface where the second main electrode is formed to a range near the center of the third semiconductor layer, where the distribution range of generated crystal defects is smaller than the thickness of the third semiconductor layer. Because of the irradiation, crystal defects are generated only in the third semiconductor layer of the third semiconductor layer with a relatively high impurity concentration and the fourth semiconductor layer with a relatively low impurity concentration that constitute the second semiconductor layer. will be established. Therefore, the disadvantages caused by the provision of crystal defects do not occur in the fourth semiconductor layer, which has the effect of optimizing the trade-off relationship between turn-off time and on-resistance. In addition, since the IGET can be manufactured without irradiating the vicinity of the insulating film with ionizing radiation, 71! There is no possibility that the threshold voltage will change before and after irradiation with radiation.

[Brief explanation of drawings]

1 to 3 are cross-sectional views showing first to third embodiments of IGBTs according to the present invention, and FIGS. 4A to 4D are methods for manufacturing IGBTs according to these first to third embodiments. FIG. 5A and FIG. 5B are cross-sectional views showing the fourth embodiment of the present invention.
Cross-sectional view showing the method for manufacturing the IGBT according to the embodiment, No. 6
The figure is a sectional view showing the structure of an IGBT according to the fourth embodiment, FIG. 7 is a sectional view showing the fifth embodiment of the IGBT according to the present invention, and FIG. 8 is a sectional view showing the structure of the IGBT according to the fifth embodiment. IGB
Cross-sectional views illustrating a part of the manufacturing method of T, FIGS. 9 to 16
The figure is a graph showing the effect of the IGBT according to the fifth embodiment, and FIG. 17 is a cross-sectional view showing the structure of the conventional IGBT.
FIG. 18 is a circuit diagram showing the equivalent circuit, and FIGS. 19 and 20 are respectively conventional I
FIG. 2 is a cross-sectional view and an illustrated perspective cross-sectional view showing the structure of a GBT. In the figure, 1 is a P+ collector layer, 2A is an N+ epitaxial layer, 2B is an N-epitaxial layer, 3 is a P well region, 4 is an N+ emitter region, 5 is a gate insulating film, 6 is a gate electrode, and 7 is an emitter. 8 is an insulating film, 9 is a collector electrode, 36 is a mask, 40 is an electron beam, 41a is a low energy light ion beam, 4lb is a high energy light ion beam, 42 is a power source, and 51 is a helium ion. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (5)

[Claims] (1) a first semiconductor layer of a first conductivity type having first and second main surfaces; and a first semiconductor layer of a second conductivity type formed on the first main surface of the first semiconductor layer. a second semiconductor layer; a first semiconductor region of a first conductivity type selectively formed on a surface of the second semiconductor layer; and a first semiconductor region selectively formed on a surface of the first semiconductor region. Second
a second semiconductor region of a conductivity type; an insulating film formed on a surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; a control electrode formed on the second main surface of the first semiconductor layer; a first main electrode formed on the first and second semiconductor regions; and a first main electrode formed on the second main surface of the first semiconductor layer. 2 main electrodes, with respect to the number of positive fixed charges in the insulating film and the number of levels at the interface between the insulating film and the first semiconductor region, the former exists in balance with the latter. Or, an insulated gate bipolar transistor characterized by the fact that the former is much more present than the latter. (2) a first conductivity type first semiconductor layer having first and second principal surfaces; and a second conductivity type formed on the first principal surface of the first semiconductor layer. a second semiconductor layer, a first semiconductor region of a first conductivity type selectively formed on a surface of the second semiconductor layer, and a first semiconductor region selectively formed on a surface of the first semiconductor region. second
a second semiconductor region of a conductivity type; an insulating film formed on a surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; a control electrode formed on the second main surface of the first semiconductor layer; a first main electrode formed on the first and second semiconductor regions; and a first main electrode formed on the second main surface of the first semiconductor layer. 2 main electrodes, and the second semiconductor layer has the first main electrode of the first semiconductor layer.
a third semiconductor layer of a second conductivity type with relatively high impurity concentration and having crystal defects, formed on the main surface of the third semiconductor layer, and a relatively high impurity concentration semiconductor layer formed on the third semiconductor layer and having relatively high impurity concentration; An insulated gate bipolar transistor comprising a fourth semiconductor layer of a second conductivity type with a low impurity concentration. (3) preparing a first semiconductor layer of a first conductivity type having first and second main surfaces; and a step of preparing a first semiconductor layer of a first conductivity type having first and second main surfaces; selectively forming a first semiconductor region of a first conductivity type on a surface of the second semiconductor layer; and forming a first semiconductor region of a first conductivity type on a surface of the first semiconductor region. selectively forming a second semiconductor region of a second conductivity type;
forming an insulating film on the surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; forming a control electrode on the insulating film; forming a first main electrode over the first and second semiconductor regions; forming a second main electrode on the second main surface of the first semiconductor layer; A method for manufacturing an insulated gate bipolar transistor, comprising the step of irradiating ionizing radiation from above the control electrode while applying a predetermined voltage between the control electrode and the first main electrode. (4) preparing a first semiconductor layer of a first conductivity type having first and second main surfaces; and forming a second conductivity type semiconductor layer on the first main surface of the first semiconductor layer. selectively forming a first semiconductor region of a first conductivity type on a surface of the second semiconductor layer; and forming a first semiconductor region of a first conductivity type on a surface of the first semiconductor region. selectively forming a second semiconductor region of a second conductivity type;
forming an insulating film on the surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; forming a control electrode on the insulating film; forming a first main electrode over the first and second semiconductor regions; forming a second main electrode on the second main surface of the first semiconductor layer; irradiating a first ionizing radiation from above the control electrode with a predetermined voltage applied between the control electrode and the first main electrode so that the range is near the insulating film; irradiating second ionizing radiation from above the main surface on which the main electrode is formed such that the range is within the second semiconductor layer. (5) preparing a first semiconductor layer of a first conductivity type having first and second main surfaces; and forming a second conductivity type semiconductor layer on the first main surface of the first semiconductor layer. forming a second semiconductor layer having a relatively high impurity concentration on the first main surface of the first semiconductor layer. the step of forming a third semiconductor layer of a conductivity type; and the step of forming a fourth semiconductor layer of a second conductivity type with a relatively low impurity concentration on the third semiconductor layer; selectively forming a first semiconductor region of a first conductivity type on the surface of the semiconductor layer of No. 4; and selectively forming a second semiconductor region of a second conductivity type on the surface of the first semiconductor region. forming an insulating film on the surface of the first semiconductor region sandwiched between the fourth semiconductor layer and the second semiconductor region; and forming a control electrode on the insulating film. forming a first main electrode over the first and second semiconductor regions; and forming a second main electrode on the second main surface of the first semiconductor layer. a step of applying ionizing radiation to a range in which crystal defects are distributed in a range smaller than the thickness of the third semiconductor layer from above the main surface on which the second main electrode is formed; 3. A method for manufacturing an insulated gate bipolar transistor, further comprising the step of irradiating near the center of the semiconductor layer.