CN104064610B - 以微纳米结构硅为光敏层的正照式Si‑PIN光电探测器及其制备方法 - Google Patents
以微纳米结构硅为光敏层的正照式Si‑PIN光电探测器及其制备方法 Download PDFInfo
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Abstract
本发明公开了一种以微纳米结构硅为光敏层的正照式Si‑PIN光电探测器及其制备方法，以微纳米结构硅为光敏层的正照式Si‑PIN光电探测器包括I型衬底、位于I型衬底下方的N区、位于I型衬底中央上方的微纳米结构层P区、位于I型衬底两侧上方的P+区、位于I型衬底上表面的上端电极及位于N区下表面的下端电极。本发明以微纳米结构硅为光敏层的正照式Si‑PIN光电探测器比传统Si光电探测器具有更高的响应度，同时还能实现对近红外光的探测，其制备工艺简单，且可与传统硅半导体工艺兼容。
Description
技术领域
本发明属于光电探测技术领域，涉及光电探测器件结构，具体涉及一种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器及其制备方法。
背景技术
光电探测器作为光纤通讯系统、红外成像系统、激光报警系统和激光测距系统等的重要组成部分，在民用方面有广泛的应用。目前，广泛使用的光电探测器主要有Si基光电探测器和InGaAs近红外光电探测器。其中，Si-PIN光电探测器响应速度快、灵敏度高，且Si材料易于提纯、易掺杂、资源丰富、成本低、易于大规模集成和相关技术成熟等，因而被广泛使用。但是，由于Si材料的禁带宽度较大（1.12 eV），因而Si基光探测器的主要探测范围为400 nm～1000 nm，无法达到在较低偏置下探测大于1100 nm的光波信号的目的。因此，当需要探测大于1000 nm的近红外光信号时，常用InGaAs光电探测器代替。但是，InGaAs半导体材料存在价格昂贵、热机械性能较差、晶体质量较差且不易与现有硅微电子工艺兼容等缺点。
微纳米结构硅是一种通过反应离子刻蚀、化学刻蚀及纳米压印刻蚀等方法制备的表面硅材料，该材料具有微纳米尺度的精细微结构和大面积均匀性。目前，纳米压印刻蚀这一新型的微纳米加工技术正受到国内外的重视，其基本原理是将事先制作好的微纳米结构模版通过专用压机，作用于一层薄的聚合物压印胶上，这层具有良好流变性的压印胶可通过热作用或紫外光固化，经良好的脱模后在压印胶上形成与模版1:1大小的图案，从而替代传统的“光刻”工艺。该工艺通过压印胶的模压变形与固化来实现图像的转移，图像最小尺度极限主要依赖于模板的加工精度，而后者可借助最新的微纳米刻蚀技术，实现纳米量级的加工，突破了传统光刻的工艺极限，降低了对特殊曝光束源、高精度聚焦系统、极短波长透镜系统以及抗蚀剂分辨率受光波场效应的限制和要求，具有工艺重复性好、生产效率高和图形转移精度高等优点，适合产业化批量生产。
微纳米结构硅对可见光及近红外光有很好的减反性和增吸性，光谱吸收率可达到90%以上。微纳米结构的存在将产生散射效应，使微纳米硅的直接带隙宽度与间接带隙宽度之间的差异减少，可使硅材料的能带结构由间接带隙向准直接带隙转变，因而吸收起始波长可以实现红移。基于纳米压印刻蚀工艺得到的新型Si-PIN光电探测器，不仅能提高对可见光及近红外光的吸收率，还能使光响应波段扩展到近红外波段范围，使响应度更高。此外，纳米压印刻蚀工艺简单且可与传统硅微电子工艺兼容。因此，这种新型Si-PIN光电探测器在大规模市场化方面优势明显。
发明内容
本发明基于上述微纳米压印刻蚀工艺，提供一种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器及其制备方法。
本发明技术方案为：
以微纳米结构硅为光敏层的正照式Si-PIN光电探测器，包括I型衬底、位于I型衬底下方的N区、位于I型衬底中央上方的微纳米结构层P区、位于I型衬底两侧上方的P+区、位于I型衬底上表面的上端电极及位于N区下表面的下端电极，其特征为：
（1）所述微纳米结构硅层P区为探测器光敏面；
（2）所述微纳米结构硅层P区尺寸为：柱/孔直径50～90 nm、高度300～500 nm、周期100～200 nm；
（3）所述P+区形成保护环。
作为优选，所述微纳米结构硅层P区是通过硼重扩散或离子注入掺杂和经过纳米压印刻蚀工艺得到的，其呈三维空间阵列分布。
作为优选，所述微纳米结构硅层P区呈阵列化排布。
作为优选，所述P+区是通过硼重扩散或离子注入掺杂方法制备得到的，其掺杂浓度范围为1×1018 ion/cm3～5×1019 ion/cm3。
作为优选，所述上端电极和下端电极为铝薄膜层或金薄膜层或铬/金薄膜层，电极厚度为50 nm～150 nm。
以微纳米结构硅为光敏层的正照式Si-PIN光电探测器的制备方法，包括以下步骤：
（1）：在本征I型衬底表面氧化生长SiO2膜层；
（2）：在SiO2膜层表面四周光刻出环形N型区的图形；
（3）：在SiO2膜层表面光刻出微纳米结构硅层P区的图形，然后进行硼扩散或离子注入掺杂形成微纳米结构硅层P区，在微纳米结构硅层P区上方通过纳米压印刻蚀技术加工出微纳米结构；
（4）：在SiO2膜层表面光刻出P+区的图形，然后进行硼重扩散或离子注入掺杂形成P+区；
（5）：制备电极。
上述的以微纳米结构硅为光敏层的正照式Si-PIN光电探测器的制备方法中：
所述N区为磷扩散或离子注入掺杂N型区，结深为1.5 μm ～3. 5 μm，掺杂浓度范围为4×1015 ion/cm3 ～ 2×1017 ion /cm3。
所述P型区为硼扩散或离子注入掺杂P型区，结深为0.5 μm ～ 3.0 μm，掺杂浓度范围为4×1015 ion/cm3 ～ 2×1017 ion /cm3。
所述微纳米结构硅层是通过对硼扩散或离子注入掺杂P区进行纳米压印刻蚀得到的呈三维空间阵列分布的层状微结构。微纳米结构硅呈阵列化排布，其典型尺寸为：硅微纳米柱或微纳米孔直径50～90 nm、高度（或深度）300～500 nm、周期100～200 nm。
所述P+区是通过硼重扩散或离子注入掺杂方法制备得到的，结深为0.5 μm ～3.5 μm，掺杂浓度范围为1×1018 ion/cm3～5×1019 ion/cm3。
上端电极和下端电极为铝薄膜层或金薄膜层或铬/金薄膜层，电极厚度为50 nm～150 nm。
本发明的基本工作原理是：被探测物质所激发出的光辐射或各种反射激光被新型Si-PIN光电探测器的光敏面所吸收，产生光生载流子，这些自由电荷在外电场作用下分别向两极漂移，从而产生光电压或者光电流。
本发明的有益效果是：将纳米压印刻蚀技术制备的微纳米结构硅与传统Si-PIN光电探测器相结合的一种新型Si-PIN光电探测器结构。由于微纳米结构硅具有宽光谱吸收和低反射率高吸收率等特征，以及探测器独特的环形P+区也叫保护环区的存在，使得这种新型Si-PIN光电探测器具有近红外光谱延伸的特征以及较高的响应度，特别能在700 nm～1200 nm波长范围内提高器件的响应度和量子效率。
按照本发明所述的以微纳米结构硅为光敏层的正照式Si-PIN光电探测器其所用的基本材料为硅，易于与现有硅微电子标准工艺兼容，且制备过程简单，成本低。并且，由于光敏面是具有微纳米尺度的表面结构，使得该器件具有较高的响应度和近红外光谱响应的特征。而且，采用纳米压印刻蚀技术加工得到的微纳米结构硅具有良好的分布均匀性与周期重复性，在大规模生产方面具有很大优势。
附图说明
图1是本发明的剖面结构示意图。
图2是本发明的仰视平面结构示意图。
其中各附图标记的含义为：
1- I型衬底，2- N区，3- 微纳米结构硅层P区，4- P+区，5-上端电极，6-下端电极。
具体实施方式
下面结合附图1-2和具体实施例对本发明一种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器及其制备方法作进一步的说明。
实施例1
本发明一种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器的结构如图1所示，包括I型衬底1、N区2、微纳米结构硅层P区3、P+区4、上金属电极5及下金属电极6，I型衬底1可采用高阻Si单晶片；N区2可采用磷扩散或离子注入掺杂；微纳米结构硅层P区3可采用硼扩散或离子注入掺杂，在其上进行纳米压印刻蚀；P+区4可采用硼重扩散或离子注入掺杂；上端电极5可采用P型欧姆接触；下端电极6可采用N型欧姆接触；这样制作的新型Si-PIN光电探测器具有微纳米结构硅层和保护环，从而具有高响应度和近红外宽光谱响应的特性。
本发明一种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器的制备方法的具体工艺过程为：
1. 预备表面清洁、干燥的高阻（电阻率为1000 Ω•cm～2000 Ω•cm）、晶向为<111>的硅单晶片衬底材料；
2.将硅单晶片研磨抛光至厚度为350μm，并在衬底正面氧化生长SiO2膜层，膜层厚度为300 nm～400 nm，生长温度为1000℃；
3. 光刻SiO2膜层形成P+区4保护环硼掺杂窗口，在1000℃～1100℃下进行硼重扩散或离子注入掺杂形成P+区4，结深为1.0 μm ～ 3.5 μm；
4. 光刻SiO2膜层形成微纳米结构硅层P区3硼掺杂窗口，在1000℃下进行硼扩散或离子注入掺杂形成微纳米结构硅层P区，结深为0.2 μm ～ 3.0 μm；
5. 对衬底正面涂正胶，并减薄、研磨、抛光衬底背面，使衬底厚度为100 μm ～200μm，并进行磷扩散或离子注入掺杂形成N区2，结深约为3μm～ 4μm，接着去除正面正胶；
6. 依次利用丙酮、乙醇对磷重扩散或离子注入掺杂后的硅衬底进行清洗并烘干；
7. 采用纳米压印刻蚀工艺对形成微纳米结构硅层P区3的上表面进行处理；
8. 在P+区4表面刻蚀电极窗口，并在正面和背面依次沉积上端电极5和下电极6。
其中，在微纳米结构硅层P区3的制备中，微纳米结构硅呈阵列化排布，其尺寸为：硅微纳米柱或微纳米孔直径50～90 nm、高度（或深度）300～500 nm、周期100～200 nm。
其中，金属电极可选材料有铝、金、铬/金；金属沉积方法可为LPCVD、MOCVD、磁控溅射等；金属电极厚度为50 nm～150 nm。
该种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器的响应波长范围为400nm～1200 nm，响应度范围为0.5 A/W～10 A/W。
以上仅是本发明一种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器及其制备方法众多具体应用范围中的代表性实施例，对本发明一种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器及其制备方法的保护范围不构成任何限制，凡采用变换或是等效替换而形成的技术方案，均落在本发明权利保护范围之内。
Claims (1)
1.一种以微纳米结构硅为光敏层的正照式Si-PIN光电探测器，包括I型衬底（1）、位于I型衬底(1)下方的N区（2）、位于I型衬底(1)中央上方的微纳米结构层P区（3）、位于I型衬底(1)两侧上方的P+区（4）、位于I型衬底(1)上表面的上端电极（5）及位于N区（2）下表面的下端电极（6），其特征在于：
（1）、所述微纳米结构硅层P区（3）为探测器光敏面；
（2）、所述微纳米结构硅层P区（3）尺寸为：柱/孔直径50～90 nm、高度300～500 nm、周期100～200 nm；
（3）、所述P+区（4）形成保护环；
所述微纳米结构硅层P区（3）是通过硼重扩散或离子注入掺杂和经过纳米压印刻蚀工艺得到的，其呈三维空间阵列分布；所述P+区（4）是通过硼重扩散或离子注入掺杂方法制备得到的，其掺杂浓度范围为1×1018 ion/cm3～5×1019 ion/cm3；所述上端电极（5）和下端电极（6）为铝薄膜层或金薄膜层或铬/金薄膜层，电极厚度为50 nm～150 nm；
所述以微纳米结构硅为光敏层的正照式Si-PIN光电探测器的制备方法的具体工艺过程为：
（1）、 预备表面清洁、干燥的高阻，电阻率为1000 Ω•cm～2000 Ω•cm、晶向为<111>的硅单晶片衬底材料；
（2）、将硅单晶片研磨抛光至厚度为350μm，并在衬底正面氧化生长SiO2膜层，膜层厚度为300 nm～400 nm，生长温度为1000℃；
（3）、 光刻SiO2膜层形成P+区（4）保护环硼掺杂窗口，在1000℃～1100℃下进行硼重扩散或离子注入掺杂形成P+区（4），结深为1.0 μm ～ 3.5 μm；
(4) 、光刻SiO2膜层形成微纳米结构硅层P区（3）硼掺杂窗口，在1000℃下进行硼扩散或离子注入掺杂形成微纳米结构硅层P区，结深为0.2 μm ～ 3.0 μm；
(5)、对衬底正面涂正胶，并减薄、研磨、抛光衬底背面，使衬底厚度为100 μm ～ 200μm，并进行磷扩散或离子注入掺杂形成N区（2），结深约为3μm～ 4μm，接着去除正面正胶；
（6）、依次利用丙酮、乙醇对磷重扩散或离子注入掺杂后的硅衬底进行清洗并烘干；
（7）、采用纳米压印刻蚀工艺对形成微纳米结构硅层P区（3）的上表面进行处理；
（8）、在P+区（4）表面刻蚀电极窗口，并在正面和背面依次沉积上端电极（5）和下端电极（6）。
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