CN104062573A - Hot carrier injection test circuit and method thereof - Google Patents
Hot carrier injection test circuit and method thereof Download PDFInfo
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- CN104062573A CN104062573A CN201310093705.8A CN201310093705A CN104062573A CN 104062573 A CN104062573 A CN 104062573A CN 201310093705 A CN201310093705 A CN 201310093705A CN 104062573 A CN104062573 A CN 104062573A
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Abstract
The invention provides a hot carrier injection test circuit and a method thereof. The hot carrier injection test circuit comprises at least three successively connected test units. The number of the test units is an odd number. Each test unit comprises the components of: a diode, a PMOS tube and a NMOS tube. According to the hot carrier injection test circuit and the method provided by the technical solution of the invention, a plurality of NMOS tube samples are simultaneously adopted for testing, not only is testing time reduced, but also testing difference caused by different NMOS tube samples is reduced. Furthermore accuracy for evaluating injection service life of the hot carrier of the NMOS tube is improved.
Description
Technical field
The present invention relates to integrated circuit fields, particularly a kind of hot carrier injection into test circuit and method.
Background technology
It is the key factor that affects semiconductor MOS pipe performance that hot carrier is injected (HCI, Hot Carrier Injection) always, and it directly causes the degeneration of metal-oxide-semiconductor performance, and therefore, hot carrier is injected into an important indicator for metal-oxide-semiconductor reliability testing.The hot carrier injection into test of metal-oxide-semiconductor is according to (the JEDEC of joint electron device engineering council, Joint Electron Device Engineering Council) standard, while applying identical stress voltage, record the degeneration amplitude of the metal-oxide-semiconductor performance index of testing under different time, calculate the life-span of its hot carrier injection into test under normal working voltage or 1.1 times of operating voltage according to the degeneration amplitude of metal-oxide-semiconductor performance index and life model.
Fig. 1 is the circuit structure of traditional NMOS pipe hot carrier injection into test and the sequential schematic diagram that applies test voltage.With reference to figure 1, NMOS pipe N11 is the selected sample of testing, and its substrate and source electrode are all connected to ground.Before testing, under NMOS pipe N11 is in running order, the voltage at NMOS pipe N11 grid and drain electrode two ends is operating voltage (operating voltage) Vop.When test, during the t1 moment to t2 moment, the grid to NMOS pipe N11 and drain electrode stress application voltage (stressvoltage) Vstress simultaneously; During the t2 moment to t3 moment, the voltage that the grid to NMOS pipe N11 and drain electrode apply becomes operating voltage Vop from stress voltage Vstress, during this period, detects the drain saturation current of NMOS pipe N11; Between the t3 moment to t4 moment, the grid to NMOS pipe N11 and drain electrode stress application voltage Vstress again.Repeat above-mentioned test process, the cumulative time of stress application voltage Vstress constantly increases, the NMOS pipe N11 drain saturation current detecting also changes thereupon, by calculating the time dependent relation of drain saturation current attenuation amplitude that can obtain NMOS pipe N11.
Fig. 2 adopts the test of test circuit shown in Fig. 1 NMOS pipe drain saturation current attenuation results schematic diagram.With reference to figure 2, transverse axis represents the test duration (s), it is the cumulative time of stress application voltage, the longitudinal axis represents NMOS pipe drain saturation current attenuation amplitude (%), three suite lines in figure are to test the drain current attenuation amplitude under three DC stress voltages (1.4V, 1.5V and 1.6V) and discrete point corresponding to drain saturation current attenuation amplitude carried out to matching according to classic method to obtain, and every suite line comprises tests to two NMOS pipe samples two curves that obtain.The curve obtaining according to test, can calculate the life-span of NMOS pipe under normal working voltage.Conventionally be 10% as failure criteria using metal-oxide-semiconductor drain saturation current attenuation amplitude.Adopt hot carrier injection into test can predict the metal-oxide-semiconductor hot carrier injection life-span, tested metal-oxide-semiconductor is carried out to hot carrier injection until its device parameters lost efficacy, the spent time is exactly the out-of-service time of device, just can calculate metal-oxide-semiconductor hot carrier inject the life-span according to out-of-service time and life model.
But along with semiconductor fabrication process enters the deep-submicron epoch, when metal-oxide-semiconductor size scaled down, device operating voltage does not have corresponding equal proportion and reduces.In small size device, the lateral dimension of circuit is more and more less, causes channel length to reduce, and utilizes classic method to carry out hot carrier injection into test to metal-oxide-semiconductor, and the test result of different metal-oxide-semiconductor samples exists very big-difference, as shown in Figure 3.Therefore,, there is the testing differentia of different metal-oxide-semiconductor samples in traditional hot carrier injection into test method, causes in the time that assessment metal-oxide-semiconductor hot carrier is injected the life-span accuracy not high.Inject the accuracy in life-span in order to improve assessment metal-oxide-semiconductor hot carrier, can increase the quantity of test sample, the increase of test sample size certainly will will increase the test duration.Therefore, provide the appraisal procedure in the metal-oxide-semiconductor hot carrier injection life-span that a kind of test duration is short, accuracy is high just to become a problem demanding prompt solution.
More technical schemes about metal-oxide-semiconductor hot carrier injection into test can be US2011193586 with reference to publication number, denomination of invention is Alternating Current (AC) Stress Test Circuit, Methodfor Evaluating AC Stress Induced Hot Carrier Injection (HCI) Degradation, andTest Structure for HCI Degradation Evaluation(exchanges stress test circuit, exchange stress evaluation hot carrier and inject the method for degenerating and hot carrier and inject the test structure of degradation assessment) U.S. Patent application file.
Summary of the invention
What the present invention solved is that the NMOS pipe hot carrier causing because of different sample test difference in traditional hot carrier injection into test is injected the problem that life appraisal accuracy is low, the test duration is long.
For addressing the above problem, the invention provides a kind of hot carrier injection into test circuit, comprise at least three connected test cells successively, the quantity of described test cell is odd number, and each test cell comprises: a diode, a PMOS pipe and a NMOS pipe; In each test cell, the described gate pmos utmost point connects described NMOS tube grid and described diode cathode, the drain electrode of described PMOS pipe connects the drain electrode of described NMOS pipe, described PMOS pipe source electrode connects described PMOS pipe substrate as the first power end, described NMOS pipe source electrode connects described NMOS pipe substrate as second source end, and described diode anode is as control end; NMOS tube grid in first test cell is as input end, NMOS pipe drain electrode in last test cell is as output terminal, described input end connects output terminal, and the NMOS tube grid in a rear test cell connects the NMOS pipe drain electrode in previous test cell.
Optionally, the quantity of described test cell is less than 30000.
Optionally, the channel length of described PMOS pipe and NMOS pipe is equal.
Based on above-mentioned hot carrier injection into test circuit, the present invention also provides a kind of hot carrier injection into test method, comprise: carry out variation relation and obtain step, to obtain the variation relation between the threshold voltage variation amount of described NMOS pipe in the given time and cumulative time that stress voltage applies; Obtain described NMOS pipe hot carrier according to described variation relation and inject the life-span; Wherein, described variation relation acquisition step comprises: the original frequency of measuring described output terminal generation signal; During measuring described original frequency, described control end is in vacant state, and described input end is connected operating voltage with the first power end, described second source termination ground wire voltage; Repeatedly apply the extremely described control end of stress voltage that magnitude of voltage is identical; During applying described stress voltage, described input end and the first power end be in vacant state, described second source termination ground wire voltage; To after described control end, measure described output terminal and produce the stage frequency of signal at each stress application voltage; During measuring described stage frequency, described control end is in vacant state, and described input end is connected operating voltage with described the first power end, described second source termination ground wire voltage; Obtain the threshold voltage variation amount of described NMOS pipe according to the difference of each stage frequency and described original frequency, and threshold voltage variation amount and the variation relation of the cumulative time that stress voltage applies of described NMOS pipe in the given time.
Optionally, the threshold voltage variation amount that the described difference according to each stage frequency and described original frequency obtains described NMOS pipe comprises: according to Δ V
tHN=Δ f/k
nobtain the threshold voltage variation amount of described NMOS pipe, Δ V
tHNfor the threshold voltage variation amount of described NMOS pipe, Δ f is the difference of described stage frequency and described original frequency, k
nfor the parameter relevant with material and technique of described NMOS.
Optionally, described schedule time is 10000 seconds.
Optionally, describedly obtain described NMOS pipe hot carrier according to described variation relation and inject the life-span and meet joint electron device engineering council's standard.
Optionally, describedly obtain described NMOS pipe hot carrier according to described variation relation and inject the life-span and comprise: obtain fitting parameter according to described variation relation; Determine the out-of-service time of described NMOS pipe according to described variation relation and failure threshold voltage variety, the threshold voltage variation amount criterion that described failure threshold voltage variety is described NMOS tube failure; According to described out-of-service time and fitting parameter, utilize hot carrier to inject life model and calculate the described NMOS pipe hot carrier injection life-span.
Optionally, described hot carrier injection into test method also comprises: when cannot determine the out-of-service time of described NMOS pipe according to described variation relation and failure threshold voltage variety, change the magnitude of voltage of described stress voltage, repeat described variation relation and obtain step.
Optionally, described hot carrier injection into test method also comprises: change the magnitude of voltage of described stress voltage, repeat described variation relation and obtain step.
Optionally, the span of described stress voltage is 1V～10V.
Optionally, the span of described operating voltage is 0.5V～5V.
Compared with prior art, hot carrier injection into test circuit and method that technical solution of the present invention provides, multiple NMOS pipe samples are applied after DC stress voltage simultaneously, measure the oscillation frequency variable quantity of being managed the ring oscillator circuit output signal forming by NMOS pipe sample and PMOS, and according to the threshold voltage variation amount of the oscillation frequency variable quantity calculating NMOS pipe sample of ring oscillator circuit output signal, calculate NMOS pipe hot carrier according to JEDEC standard meter and inject the life-span.The hot carrier injection into test circuit and the method that provide due to the technical program, adopted multiple NMOS pipe samples to test simultaneously, both saved the test duration, reduced again the testing differentia because of the generation of different N metal-oxide-semiconductor sample, improved the accuracy in assessment NMOS pipe hot carrier injection life-span.
Brief description of the drawings
Fig. 1 is the circuit structure of traditional NMOS pipe hot carrier injection into test and the sequential schematic diagram that applies test voltage;
Fig. 2 is classic method test NMOS pipe drain saturation current attenuation results schematic diagram;
Fig. 3 is classic method test small size NMOS pipe drain saturation current attenuation results schematic diagram;
Fig. 4 is the hot carrier injection into test circuit diagram of the embodiment of the present invention;
Fig. 5 is the hot carrier injection into test method flow schematic diagram of embodiment of the present invention;
Fig. 6 is that the NMOS pipe threshold voltage variety of the embodiment of the present invention and the difference of stage frequency and original frequency are related to schematic diagram;
Fig. 7 is the variation relation figure between the NMOS pipe threshold voltage variety of the embodiment of the present invention and cumulative time that stress voltage applies.
Embodiment
Just as described in the background art, calculate metal-oxide-semiconductor hot carrier and inject the life-span, need the out-of-service time by metal-oxide-semiconductor stress application voltage being obtained to metal-oxide-semiconductor.Along with the development of semiconductor fabrication process, metal-oxide-semiconductor size is more and more less, channel length reduces, utilize classic method to carry out hot carrier injection into test to metal-oxide-semiconductor, there is very large difference the metal-oxide-semiconductor out-of-service time of testing different sample acquisitions, causes assessing the accuracy in metal-oxide-semiconductor hot carrier injection life-span not high.The inventor of the technical program is through research, provide a kind of test duration short, metal-oxide-semiconductor hot carrier is injected to high hot carrier injection into test circuit and the method for assessment accuracy in life-span.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Below in conjunction with Fig. 4, the hot carrier injection into test circuit of the embodiment of the present invention is elaborated.Described hot carrier injection into test circuit comprises at least three connected test cells successively, and the quantity of described test cell is odd number, and each test cell comprises: a diode, a PMOS pipe and a NMOS pipe.
Described NMOS pipe is for carrying out the sample of hot carrier injection into test, and described PMOS pipe is used for carrying out subtest.In the present embodiment, the channel length of described PMOS pipe and described NMOS pipe is equal, and the quantity of described test cell can be less than 30000.
In each test cell, the described gate pmos utmost point connects described NMOS tube grid and described diode cathode, the drain electrode of described PMOS pipe connects the drain electrode of described NMOS pipe, described PMOS pipe source electrode connects described PMOS pipe substrate as the first power end, described NMOS pipe source electrode connects described NMOS pipe substrate as second source end, and described diode anode is as control end.
It should be noted that, the control end of each test cell can independently exist, and inputs identical control signal, can be also to input a control signal after the control end of each test cell links together, in the present embodiment, the control end of each test cell links together.
For example, the hot carrier injection into test circuit shown in Fig. 4 comprises 3 test cells that structure is identical, and first test cell 41 comprises PMOS pipe P41, NMOS pipe N41 and diode D41.The grid of described PMOS pipe P41 connects the described NMOS pipe grid of N41 and the negative electrode of described diode D41, and drain electrode connects the drain electrode of described NMOS pipe N41, and source electrode is connected with substrate as the first power end Vdd; The source electrode of described NMOS pipe N41 is connected with substrate as second source end Vs; The anode of described diode D41 is as control end A.
The grid of NMOS pipe N41 in first test cell 41 is as input end In, NMOS pipe drain electrode in last test cell is as output terminal Out, described input end In connects described output terminal Out, and the NMOS tube grid in a rear test cell connects the NMOS pipe drain electrode in previous test cell.
Based on above-mentioned hot carrier injection into test circuit, embodiment of the present invention also provides a kind of hot carrier injection into test method.With reference to figure 5, described hot carrier injection into test method comprises:
Step S1: the original frequency of measuring described output terminal generation signal; During measuring described original frequency, described control end is in vacant state, and described input end is connected operating voltage with the first power end, described second source termination ground wire voltage;
Step S2: repeatedly apply the extremely described control end of stress voltage that magnitude of voltage is identical; During applying described stress voltage, described input end and the first power end be in vacant state, described second source termination ground wire voltage;
Step S3: to after described control end, measure described output terminal and produce the stage frequency of signal at each stress application voltage; During measuring described stage frequency, described control end is in vacant state, and described input end is connected operating voltage with described the first power end, described second source termination ground wire voltage;
Step S4: obtain the threshold voltage variation amount of described NMOS pipe according to the difference of each stage frequency and described original frequency, and threshold voltage variation amount and the variation relation of the cumulative time that stress voltage applies of described NMOS pipe in the given time;
Step S5: obtain described NMOS pipe hot carrier according to described variation relation and inject the life-span.
For better embodiments of the present invention being understood, below in conjunction with accompanying drawing, hot carrier injection into test circuit and the method for technical solution of the present invention are described in detail.
First, measure the original frequency of described hot carrier injection into test circuit output end Out generation signal.During measuring described original frequency, described control end A is in vacant state, and described input end In is connected operating voltage with the first power end Vdd, described second source end Vs ground wire voltage.
Due to the one-way conduction characteristic of diode, the gate isolation of NMOS pipe in the grid of NMOS pipe and other test cell in each test cell, the hot carrier injection into test circuit that is made up of odd number test cell is actual is ring oscillator, can be tested out described hot carrier injection into test circuit output end Out and produced the original frequency of signal by oscillograph or spectrum analyzer.For convenience of description, use f
0represent described original frequency.
The span of described operating voltage is 0.5V～5V, and as a preferred embodiment, in the present embodiment, described operating voltage is 1V.
Described original frequency f
0after measurement completes, stress application voltage is to the control end A of described hot carrier injection into test circuit.Particularly, during applying described stress voltage, described input end In and described the first power end Vdd be in vacant state, described second source end Vs ground wire voltage.
Apply described stress voltage to described control end A, the stress state that the NMOS pipe in each test cell injects in hot carrier, the PMOS pipe in each test cell is in unstressed condition.
For convenience of description, use t
1represent this time to apply the lasting time of described stress voltage.The span of described stress voltage is 1V～10V, and as a preferred embodiment, in the present embodiment, described stress voltage is 1.7V.
Complete and apply after described stress voltage, measure the stage frequency of described hot carrier test circuit output terminal Out generation signal.Measure the method and the described original frequency f of measurement of described stage frequency
0method identical, do not repeat them here.For convenience of description, use f
1represent to apply t
1the described stage frequency that after the described stress voltage of time, test obtains.
In the technical program, test described original frequency f
0with described stage frequency f
1time, the diode cut-off in each test cell, described hot carrier injection into test circuit is ring oscillator, according to the frequency model Δ f=k of ring oscillator
pΔ V
tHP+ k
nΔ V
tHN+ k
lΔ L can calculate the threshold voltage variation amount of NMOS pipe in described hot carrier injection into test circuit.
In the frequency model of ring oscillator, Δ f represents the frequency variation of annular oscillator output signal; k
pand k
nthe parameter relevant with material and technique that represents respectively the pipe of PMOS in ring oscillator and NMOS pipe, is known constant; Δ V
tHPwith Δ V
tHNrepresent respectively the threshold voltage variation amount of the pipe of PMOS in ring oscillator and NMOS pipe; k
lrepresent respectively channel length coefficient and the changes in channel length amount of the pipe of PMOS in ring oscillator and NMOS pipe with Δ L.
Further, in the technical program, just the NMOS pipe in described hot carrier injection into test circuit is applied to described stress voltage, in described hot carrier injection into test circuit, the channel length of the threshold voltage of PMOS pipe and PMOS pipe and NMOS pipe does not all change, i.e. Δ V in ring oscillator frequency model
tHPl is 0 with Δ.Therefore, apply after described stress voltage and apply before described stress voltage the difference DELTA f=f of described hot carrier injection into test circuit output signal frequency
1-f
0=k
nΔ V
tHN, i.e. the threshold voltage variation amount Δ V of NMOS pipe described in described hot carrier injection into test circuit
tHN=Δ f/k
n.
Repeatedly the NMOS pipe in described hot carrier injection into test circuit is applied to the stress voltage that magnitude of voltage is identical, obtain applying the threshold voltage variation amount of described NMOS pipe under different cumulative times of described stress voltage, the described cumulative time is the cumulative time that applies described stress voltage, for example, and t
1represent to apply for the first time the duration of described stress voltage, t
2represent the front duration sum that applies described stress voltage for twice, t
3represent that first three time applies the duration sum of described stress voltage,, t
nbefore representing, apply the duration sum of described stress voltage for n time.
According to (the JEDEC of joint electron device engineering council, Joint Electron Device EngineeringCouncil) standard, the T.T. of setting the hot carrier injection into test stress application voltage of metal-oxide-semiconductor is 10000 seconds, be to be 10000 seconds the described schedule time, the time that at every turn applies described stress voltage is also according to JEDEC standard, does not repeat them here.
For representing more intuitively the threshold voltage variation amount Δ V of NMOS pipe in described hot carrier injection into test circuit
tHNthe relation changing with the frequency variation Δ f of described hot carrier injection into test circuit output signal, Fig. 6 applies the described NMOS pipe threshold voltage variety Δ V that 5 described stress voltages obtain
tHNand the graph of a relation between the frequency variation Δ f of described hot carrier injection into test circuit output signal.
With reference to figure 6, horizontal ordinate represents the frequency variation Δ f(Hz of described hot carrier injection into test circuit output signal), ordinate represents described NMOS pipe threshold voltage variety Δ V
tHN(mV).Discrete point in figure is all on straight line L, and the slope of straight line L is the parameter k relevant with material and technique of described NMOS pipe
n.
Repeatedly apply after the stress voltage that magnitude of voltage is identical, the acquisition test duration is t
1, t
2, t
3,, t
nthe threshold voltage variation amount Δ V of corresponding described NMOS pipe
tHN1, Δ V
tHN2, Δ V
tHN3,, Δ V
tHNn.
According to JEDEC standard, the hot carrier of calculating described NMOS pipe is injected the life-span and is tested under the different DC stress voltage of three magnitudes of voltage.Adopt identical test circuit and method, under two other DC stress voltage, test the threshold voltage variation amount of NMOS pipe sample, under each DC stress voltage, all test two groups of NMOS pipe samples.In the present embodiment, described two other DC stress voltage is respectively 1.55V and 1.85V.
After the variable quantity of the threshold voltage that obtains NMOS pipe under different DC stress voltage, make the threshold voltage variation amount of described NMOS pipe and apply the variation relation figure between cumulative time of described stress voltage.With reference to figure 7, horizontal ordinate represents the test duration (s), and ordinate represents the threshold voltage variation amount (mV) of NMOS pipe.Discrete point in figure is the data that represent that test obtains, and curve is according to JEDEC standard, described discrete point to be carried out to matching to obtain.Described curve has three groups, the corresponding suite line of each DC stress voltage, and every suite line comprises tests to two groups of NMOS pipe samples two curves that obtain.
It should be noted that, when metal-oxide-semiconductor is carried out to hot carrier injection into test, the DC stress voltage applying is higher than the operating voltage of metal-oxide-semiconductor, simultaneously, in the curve that also will ensure to obtain under three DC stress voltages, having horizontal ordinate on a curve at least is that the ordinate of 10000 seconds corresponding points is not less than 50mV.In the time that the variation relation between the cumulative time applying according to threshold voltage variation amount and the stress voltage of described NMOS pipe cannot be determined the out-of-service time of described NMOS pipe, in 10000 seconds, threshold voltage variation amount is all less than 50mV, cannot definite threshold voltage variety it be the cumulative time that 50mV is corresponding, change the magnitude of voltage of described stress voltage, repeated execution of steps S1～step S4.
For example, in the present embodiment, the DC stress voltage that one group of NMOS pipe sample is applied to 1.55V is tested, and the curve obtaining as shown in Figure 7.Apply on the curve that the DC stress voltage of 1.55V obtains, 10000 seconds with ordinate corresponding to interior horizontal ordinate all lower than 50mV, therefore, in the time that another group sample is tested, the voltage of choosing can be higher than 1.55V, as 1.7V, 1.85V.
Obtain the variation relation between the threshold voltage variation amount of described NMOS pipe and cumulative time that stress voltage applies, just can calculate described NMOS pipe hot carrier and inject the life-span.The concrete grammar that calculates the hot carrier injection life-span of described NMOS pipe carries out according to JEDEC standard, for avoiding repeating, is below briefly described.
The threshold voltage variation amount of described NMOS pipe and the variation relation between the cumulative time that stress voltage applies can be both fitting functions, obtain fitting parameter according to described variation relation.As previously mentioned, the curve in Fig. 7 is to carry out matching according to JEDEC standard to obtain, and can calculate described fitting parameter according to the numerical value of fitting function and discrete point coordinate.
Determine the out-of-service time of described NMOS pipe according to described variation relation and failure threshold voltage variety, the threshold voltage variation amount criterion that described failure threshold voltage variety is described NMOS tube failure.
According to JEDEC standard, NMOS pipe threshold voltage variety is reached to the threshold voltage variation amount criterion of 50mV as described NMOS tube failure, when NMOS pipe threshold voltage variety is 50mV, the corresponding test duration is the out-of-service time.Particularly, with reference to figure 7, if ordinate is that the point that 50mV is corresponding is the discrete point that test obtains just on curve, the described out-of-service time is directly determined according to the time that applies described stress voltage; If ordinate is that the point that 50mV is corresponding is not discrete point on curve, for example some O in Fig. 7, the definite straight line expression formula of two points adjacent according to an O (some P and some Q) is calculated the described out-of-service time.
Obtain after the out-of-service time and fitting parameter of described NMOS pipe, inject life model according to hot carrier and calculate the described NMOS pipe hot carrier injection life-span.Described life model can be substrate and leakage current ratio Isub/Id model, can be also that drain-source voltage accelerates Vds model, can also be substrate current Isub model, and circular carries out according to JEDEC standard, does not repeat them here.
In sum, hot carrier injection into test circuit and method that technical solution of the present invention provides, by measuring the oscillation frequency variable quantity of being managed the ring oscillator circuit output signal forming by NMOS pipe sample and PMOS, calculate the threshold voltage variation amount of NMOS pipe sample, finally can calculate NMOS pipe hot carrier and inject the life-span.Hot carrier injection into test circuit and method that the technical program provides, adopted multiple NMOS pipe samples to test simultaneously, both saved the test duration, reduced again the testing differentia because of the generation of different N metal-oxide-semiconductor sample, improved the accuracy in assessment NMOS pipe hot carrier injection life-span.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection domain of technical solution of the present invention.
Claims (12)
1. a hot carrier injection into test circuit, is characterized in that, comprising: at least three connected test cells successively, and the quantity of described test cell is odd number, each test cell comprises: a diode, a PMOS pipe and a NMOS pipe;
In each test cell, the described gate pmos utmost point connects described NMOS tube grid and described diode cathode, the drain electrode of described PMOS pipe connects the drain electrode of described NMOS pipe, described PMOS pipe source electrode connects described PMOS pipe substrate as the first power end, described NMOS pipe source electrode connects described NMOS pipe substrate as second source end, and described diode anode is as control end;
NMOS tube grid in first test cell is as input end, NMOS pipe drain electrode in last test cell is as output terminal, described input end connects output terminal, and the NMOS tube grid in a rear test cell connects the NMOS pipe drain electrode in previous test cell.
2. hot carrier injection into test circuit according to claim 1, is characterized in that, the quantity of described test cell is less than 30000.
3. hot carrier injection into test circuit according to claim 1, is characterized in that, the channel length of described PMOS pipe and NMOS pipe equates.
4. a method of testing of utilizing hot carrier injection into test circuit described in claim 1, is characterized in that, comprising:
Carry out variation relation and obtain step, to obtain the variation relation between the threshold voltage variation amount of described NMOS pipe in the given time and cumulative time that stress voltage applies;
Obtain described NMOS pipe hot carrier according to described variation relation and inject the life-span;
Wherein, described variation relation acquisition step comprises:
Measure the original frequency that described output terminal produces signal; During measuring described original frequency, described control end is in vacant state, and described input end is connected operating voltage with the first power end, described second source termination ground wire voltage;
Repeatedly apply the extremely described control end of stress voltage that magnitude of voltage is identical; During applying described stress voltage, described input end and the first power end be in vacant state, described second source termination ground wire voltage;
To after described control end, measure described output terminal and produce the stage frequency of signal at each stress application voltage; During measuring described stage frequency, described control end is in vacant state, and described input end is connected operating voltage with described the first power end, described second source termination ground wire voltage;
Obtain the threshold voltage variation amount of described NMOS pipe according to the difference of each stage frequency and described original frequency, and threshold voltage variation amount and the variation relation of the cumulative time that stress voltage applies of described NMOS pipe in the given time.
5. hot carrier injection into test method according to claim 4, is characterized in that, the threshold voltage variation amount that the described difference according to each stage frequency and described original frequency obtains described NMOS pipe comprises: according to Δ V
tHN=Δ f/k
nobtain the threshold voltage variation amount of described NMOS pipe, Δ V
tHNfor the threshold voltage variation amount of described NMOS pipe, Δ f is the difference of described stage frequency and described original frequency, k
nfor the parameter relevant with material and technique of described NMOS.
6. hot carrier injection into test method according to claim 4, is characterized in that, the described schedule time is 10000 seconds.
7. hot carrier injection into test method according to claim 4, is characterized in that, describedly obtains described NMOS pipe hot carrier according to described variation relation and injects the life-span and meet joint electron device engineering council's standard.
8. hot carrier injection into test method according to claim 7, is characterized in that, describedly obtains described NMOS pipe hot carrier according to described variation relation and injects the life-span and comprise:
Obtain fitting parameter according to described variation relation;
Determine the out-of-service time of described NMOS pipe according to described variation relation and failure threshold voltage variety, the threshold voltage variation amount criterion that described failure threshold voltage variety is described NMOS tube failure;
According to described out-of-service time and fitting parameter, utilize hot carrier to inject life model and calculate the described NMOS pipe hot carrier injection life-span.
9. hot carrier injection into test method according to claim 8, it is characterized in that, also comprise: when cannot determine the out-of-service time of described NMOS pipe according to described variation relation and failure threshold voltage variety, change the magnitude of voltage of described stress voltage, repeat described variation relation and obtain step.
10. hot carrier injection into test method according to claim 4, is characterized in that, also comprises: change the magnitude of voltage of described stress voltage, repeat described variation relation and obtain step.
11. hot carrier injection into test methods according to claim 4, is characterized in that, the span of described stress voltage is 1V～10V.
12. hot carrier injection into test methods according to claim 4, is characterized in that, the span of described operating voltage is 0.5V～5V.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040085084A1 (en) * | 2002-11-06 | 2004-05-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source |
| CN1588104A (en) * | 2004-08-19 | 2005-03-02 | 信息产业部电子第五研究所 | MOS device hot carrier injection effect measuring method |
| CN101692449A (en) * | 2009-10-13 | 2010-04-07 | 上海宏力半导体制造有限公司 | Method for parallel measurement of hot carrier injection effect |
| US20110193586A1 (en) * | 2010-02-11 | 2011-08-11 | United Microelectronics Corporation | Alternating Current (AC) Stress Test Circuit, Method for Evaluating AC Stress Induced Hot Carrier Injection (HCI) Degradation, and Test Structure for HCI Degradation Evaluation |
| CN102253324A (en) * | 2011-06-17 | 2011-11-23 | 上海集成电路研发中心有限公司 | Testing structure and testing method for hot carrier effect of MOS (Metal Oxide Semiconductor) device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040085084A1 (en) * | 2002-11-06 | 2004-05-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source |
| CN1588104A (en) * | 2004-08-19 | 2005-03-02 | 信息产业部电子第五研究所 | MOS device hot carrier injection effect measuring method |
| CN101692449A (en) * | 2009-10-13 | 2010-04-07 | 上海宏力半导体制造有限公司 | Method for parallel measurement of hot carrier injection effect |
| US20110193586A1 (en) * | 2010-02-11 | 2011-08-11 | United Microelectronics Corporation | Alternating Current (AC) Stress Test Circuit, Method for Evaluating AC Stress Induced Hot Carrier Injection (HCI) Degradation, and Test Structure for HCI Degradation Evaluation |
| CN102253324A (en) * | 2011-06-17 | 2011-11-23 | 上海集成电路研发中心有限公司 | Testing structure and testing method for hot carrier effect of MOS (Metal Oxide Semiconductor) device |
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