CN104058362B - The processing method of microelectromechanical systems - Google Patents
The processing method of microelectromechanical systems Download PDFInfo
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- CN104058362B CN104058362B CN201310092536.6A CN201310092536A CN104058362B CN 104058362 B CN104058362 B CN 104058362B CN 201310092536 A CN201310092536 A CN 201310092536A CN 104058362 B CN104058362 B CN 104058362B
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Abstract
The present invention discloses a kind of processing method of microelectromechanical systems, comprises the following steps：Substrate layer is formed on silicon chip；Photoresist pattern layer is formed on the substrate layer；Whole silicon chip is heated and ultraviolet treatment with irradiation；Carry out dry etching.The above method is due to by heating and ultraviolet irradiation so that the anti-etching ability enhancing of photoresist, be not in as in conventional art because of problem that the size of photoresist side micro mechanical structure by excessive corrosion is bigger than normal.Therefore the uniformity of hole etching size can be ensured.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of processing method of microelectromechanical systems.
Background technology
Polyimides（Polyimide, PI）For microelectromechanical systems（microelectronic mechanical
System, MEMS）, it is necessary to realize transition diagram by dry etching in technique.By plasma during dry etching
After bombardment, it may appear that photoresist sideetching is excessive, so as to the critical size for causing PI holes after PI is etched becomes greatly beyond desired value
Problem.
The method of PI holes critical size is after traditional control PI dry etchings, and size benefit is carried out when litho pattern is transferred
Repay, the purpose of the size for reducing PI holes is reached by reducing the size of litho pattern.But this method is exposed by litho pattern
Influence, cause to be had differences between different disks and different batches, the uniformity of PI holes size is poor.
The content of the invention
Based on this, it is necessary to provide a kind of method that can reduce hole etching deviation so that in same process, hole size
Uniformity is preferable.
A kind of processing method of microelectromechanical systems, comprises the following steps：Substrate layer is formed on silicon chip；In the base
Photoresist pattern layer is formed on material layer；Whole silicon chip is heated and ultraviolet treatment with irradiation；Carry out dry etching.
Wherein in one embodiment, it is described whole silicon chip is heated and the step of ultraviolet treatment with irradiation in, first
Heated, then carried out ultraviolet treatment with irradiation.
Wherein in one embodiment, the temperature of the heating is 110~130 DEG C.
Wherein in one embodiment, the temperature of the heating is 120 DEG C.
Wherein in one embodiment, the frequency of the ultraviolet is 2.45GHz.
Wherein in one embodiment, the intensity of the ultraviolet is 100~125mW/cm2.
Wherein in one embodiment, the intensity of the ultraviolet is 110mW/cm2.
Wherein in one embodiment, it is described whole silicon chip is heated and ultraviolet treatment with irradiation time for 1~
1.5 minutes.
Wherein in one embodiment, the substrate layer is made of polyimide material.
The above method, due to by heating and ultraviolet irradiation so that the anti-etching ability enhancing of photoresist, will not
Because of the size of photoresist side micro mechanical structure by excessive corrosion problem bigger than normal in appearance such as conventional art.Therefore can protect
Demonstrate,prove the uniformity of hole etching size.
Brief description of the drawings
Fig. 1 is the processing method flow chart of the microelectromechanical systems of an embodiment；
Fig. 2 is the layer structure figure before being etched after microelectron mechanical structure exposes；
Fig. 3 is the layer structure figure after microelectron mechanical structure etching.
Specific embodiment
In microelectromechanical systems（MEMS）In technique, silicon substrate MEMS technology is the micromachined work based on silicon
Skill.Traditional silicon substrate MEMS technology is divided into two major classes, i.e. Bulk micro machining and surface silicon process technology.Bulk micro machining is
Three-dimension process is carried out to body silicon, using substrate monocrystal silicon chip as mechanical structure；Surface silicon process technology is utilized and common integrated electricity
The similar plane machining means of road technique, using silicon (monocrystalline or polycrystalline) film as mechanical structure.
In silicon substrate MEMS technology, the processing technology of most critical mainly includes depth-to-width ratio big anisotropic corrosion technique, key
Conjunction technology and surface sacrificial layer technology etc..The base material that corrosion technology is placed on silicon substrate surface etches to form micro mechanical structure, at present
Conventional base material uses polyimides（Polyimide, PI）.Corrosion technology includes wet etching and dry etching.Wet etching
It is incompatible with integrated circuit technology, it is difficult to carried out with integrated circuit it is integrated, and exist be difficult to accurately to control lateral dimension precision and
The shortcomings of device size is larger.Dry plasma technology has become the main flow of micromachining technology.
As shown in figure 1, the processing method flow chart of the microelectromechanical systems for an embodiment.The method includes following step
Suddenly.
S101：Substrate layer is formed on silicon chip.With reference to Fig. 2, substrate layer 20 is formed on silicon chip 10.Wherein substrate layer 20 passes through
Dry etching can form micro mechanical structure.Substrate layer 20 uses polyimides（Polyimide, PI）.
S102：Photoresist pattern layer is formed on the substrate layer.With continued reference to Fig. 2, photoresist pattern layer 30 is in base
Coating photoresist on material layer 20, is then transferred to photoresist through steps such as overexposure, development, photoetching by the pattern of micro mechanical structure
The pattern for being formed afterwards.Photoetching agent pattern transfer technique is the common technology of field of lithography, be will not be described here.Photoresist is follow-up
It is substantially erosion-resisting in dry etch step, will not be etched away.Therefore the substrate layer in the case where photoresist is covered and is protected
It is retained, and the substrate layer not being covered by photoresist can then be etched away.It should be noted that in microelectromechanical systems processing
In technique, it is often necessary to which processing forms through hole, namely hole can be related to etch.The anti-etching ability in dry etching of photoresist,
Whether determine the size of through hole can meet predetermined requirement.In traditional etching technics, photoresist side often occurs
While being corroded, cause the problem for becoming large-sized of through hole, in such as Fig. 2, the through hole expection formed on photoresist pattern layer 30 should
It is solid line edge, but is expanded to dotted line edge because of excessive erosion in practice.Therefore, being added in traditional technological process
Step S103.
S103：Whole silicon chip is heated and ultraviolet treatment with irradiation.In this step, first heated, then entered
Row ultraviolet treatment with irradiation.By heating, the aqueous vapor of the substrate layer 20 below photoresist pattern layer 30 can discharge, especially
It is that, for the polyimides of the easy moisture absorption, the heat treatment of early stage contributes to the volatilization of the inside aqueous vapor, so follow-up ultraviolet is made
With big influence would not be produced to substrate layer 20.In addition, by heating, photoresist can uniformly be heated, and make photoetching
Glue more uniform distribution after being heated, although can so make that the size of original figure becomes is bigger, can be in follow-up ultraviolet
Make photoresist more anti-etching in processing procedure, so as to reach the purpose of more preferably protection substrate layer etch topography and critical size.Institute
The temperature of heating is stated between 110~130 DEG C, preferably 120 DEG C.Too low temperature can not be functioned as described above, too high
Temperature can influence the performance of substrate layer 20.
On the other hand, ultraviolet irradiation can strengthen the anti-etching ability of photoresist.In the present embodiment, what is used is ultraviolet
Line frequency is 2.45GHz, and intensity is 100~125mW/cm2, preferably 110mW/cm2。
The time of this step process is 1~1.5 minute.
S104：Carry out dry etching.After the step of by above-mentioned S101~S103, you can perform the step of dry etching
Suddenly.Dry etching is usually the method for using plasma bombardment.After this step, the substrate layer 20 not being covered by photoresist is carved
Eating away, so that micro mechanical structure is formed, with reference to Fig. 3.
The above method, due to by heating and ultraviolet irradiation so that the anti-etching ability enhancing of photoresist, will not
Because of the size of photoresist side micro mechanical structure by excessive corrosion problem bigger than normal in appearance such as conventional art.By test,
Change in size can be controlled in 20 rans.Therefore the uniformity of hole etching size can be ensured.
Embodiment described above only expresses several embodiments of the invention, and its description is more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Shield scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (3)
1. a kind of processing method of microelectromechanical systems, comprises the following steps：
Substrate layer is formed on silicon chip；The substrate layer is made of polyimide material；
Photoresist pattern layer is formed on the substrate layer；
Whole silicon chip is heated and ultraviolet treatment with irradiation, the time for the treatment of is 1~1.5 minute；
Carry out dry etching；
It is described whole silicon chip is heated and the step of ultraviolet treatment with irradiation in, first heated, then carry out ultraviolet
Line treatment with irradiation；The frequency of the ultraviolet is 2.45GHz；The intensity of the ultraviolet is 100~125mW/cm2；It is described to add
The temperature of heat treatment is 110~130 DEG C.
2. the processing method of microelectromechanical systems according to claim 1, it is characterised in that the temperature of the heating
Spend is 120 DEG C.
3. the processing method of microelectromechanical systems according to claim 1, it is characterised in that the intensity of the ultraviolet
It is 110mW/cm2。
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| CN104058362B true CN104058362B (en) | 2017-06-27 |
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| CN108520856A (en) * | 2018-05-18 | 2018-09-11 | 中国科学院微电子研究所 | A kind of patterning method of ito thin film |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214524B1 (en) * | 1997-10-03 | 2001-04-10 | Fusion Systems Corporation | Controlled amine poisoning for reduced shrinkage of features formed in photoresist |
| US6306780B1 (en) * | 2000-02-07 | 2001-10-23 | Agere Systems Guardian Corp. | Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation |
| CN101561629A (en) * | 2008-04-16 | 2009-10-21 | 中国科学院微电子研究所 | Method for manufacturing gradual slope of medium edge by photoresist with inverse trapezium section |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080015536A (en) * | 2006-08-16 | 2008-02-20 | 삼성전자주식회사 | System and method for manufacturing wire grid polarizer |
| CN101863447B (en) * | 2009-04-15 | 2011-10-05 | 中国科学院半导体研究所 | Method for manufacturing sloped sidewall silicon dioxide structure by adopting photoetching and dry etching |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214524B1 (en) * | 1997-10-03 | 2001-04-10 | Fusion Systems Corporation | Controlled amine poisoning for reduced shrinkage of features formed in photoresist |
| US6306780B1 (en) * | 2000-02-07 | 2001-10-23 | Agere Systems Guardian Corp. | Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation |
| CN101561629A (en) * | 2008-04-16 | 2009-10-21 | 中国科学院微电子研究所 | Method for manufacturing gradual slope of medium edge by photoresist with inverse trapezium section |
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Effective date of registration: 20170926 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |
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