CN104058362A - Processing method of microelectronic mechanical system - Google Patents
Processing method of microelectronic mechanical system Download PDFInfo
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- CN104058362A CN104058362A CN201310092536.6A CN201310092536A CN104058362A CN 104058362 A CN104058362 A CN 104058362A CN 201310092536 A CN201310092536 A CN 201310092536A CN 104058362 A CN104058362 A CN 104058362A
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- processing method
- microelectromechanical systems
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Abstract
The invention discloses a processing method of a microelectronic mechanical system, which comprises the following steps: forming a substrate layer on a silicon chip; forming a photoresist pattern layer on the substrate layer; heating the whole silicon chip and performing ultraviolet ray irradiation treatment; and then etching by a dry method. By heating treatment and the ultraviolet ray irradiation, the anti-etching capability of a photoresist is enhanced by the method, so that problem that the side edge of the photoresist is excessively corroded in the prior art and the size of a micro mechanical structure is large can be avoided. The aperture etching size can ensure consistency.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of processing method of microelectromechanical systems.
Background technology
Polyimides (polyimide, PI), in microelectromechanical systems (microelectronic mechanicalsystem, MEMS) technique, need to be realized transition diagram through dry etching.In dry etching process, after plasma bombardment, there will be photoresist sideetching excessive, thereby cause the critical size in PI hole after PI etching to become the problem that exceeds greatly desired value.
After traditional control PI dry etching, the method for PI hole critical size is, carries out dimension compensation when transfer printing litho pattern, reaches the object of the size that reduces PI hole by reducing the size of litho pattern.But this method is subject to the impact of litho pattern exposure, causes there are differences between different disks and different batches, and the uniformity of PI hole dimension is poor.
Summary of the invention
Based on this, be necessary to provide a kind of method that can reduce hole etching deviation, make in same process, the uniformity of hole dimension is better.
A processing method for microelectromechanical systems, comprises the steps: to form substrate layer on silicon chip; On described substrate layer, form photoresist pattern layer; Whole silicon chip is heated and ultraviolet treatment with irradiation; Carry out dry etching.
Therein in an embodiment, described to whole silicon chip heat and the step of ultraviolet treatment with irradiation in, first carry out heat treated, then carry out ultraviolet treatment with irradiation.
In an embodiment, the temperature of described heat treated is 110～130 ℃ therein.
In an embodiment, the temperature of described heat treated is 120 ℃ therein.
In an embodiment, described ultraviolet frequency is 2.45GHz therein.
In an embodiment, described ultraviolet intensity is 100～125mW/cm2 therein.
In an embodiment, described ultraviolet intensity is 110mW/cm2 therein.
Therein in an embodiment, described whole silicon chip is heated and the time of ultraviolet treatment with irradiation is 1～1.5 minute.
In an embodiment, described substrate layer adopts polyimide material to make therein.
Said method, owing to irradiating through heat treated and ultraviolet ray, strengthens the anti-etching ability of photoresist, there will not be as in conventional art because photoresist side is by the size of excessive corrosion micro mechanical structure problem bigger than normal.Therefore can guarantee the uniformity of hole etching size.
Accompanying drawing explanation
Fig. 1 is the processing method flow chart of the microelectromechanical systems of an embodiment;
Fig. 2 is the layer structure figure before etching after microelectron mechanical structure exposure;
Fig. 3 is the layer structure figure after microelectron mechanical structure etching.
The specific embodiment
In microelectromechanical systems (MEMS) technique, silica-based MEMS technology is to take silicon as basic miromaching.Traditional silica-based MEMS technology is divided into two large class, i.e. Bulk micro machining and surface silicon processing technologys.Bulk micro machining is that body silicon is carried out to three-dimensional processing, usings substrate monocrystal silicon chip as frame for movement; Surface silicon processing technology is utilized the plane machining means similar to common integrated circuit technology, usings silicon (monocrystalline or polycrystalline) film as frame for movement.
In silica-based MEMS technology, the processing technology of most critical mainly comprises anisotropic corrosion technique, bonding techniques and the surperficial sacrificial layer technology etc. that depth-to-width ratio is large.Corrosion technology forms micro mechanical structure by the base material etching that is placed in silicon substrate surface, and at present conventional base material adopts polyimides (polyimide, PI).Corrosion technology comprises wet etching and dry etching.Wet etching and integrated circuit technology are incompatible, are difficult to carry out integratedly with integrated circuit, and exist and to be difficult to accurately control lateral dimension precision and the shortcoming such as device size is larger.Dry plasma technology has become the main flow of micromachining technology.
As shown in Figure 1, be the processing method flow chart of the microelectromechanical systems of an embodiment.The method comprises the steps.
S101: form substrate layer on silicon chip.With reference to figure 2, on silicon chip 10, form substrate layer 20.Wherein substrate layer 20 can form micro mechanical structure through dry etching.Substrate layer 20 adopts polyimides (polyimide, PI).
S102: form photoresist pattern layer on described substrate layer.Continuation is with reference to figure 2, and photoresist pattern layer 30 is to be coated with photoresist on substrate layer 20, then through the steps such as overexposure, development, photoetching by the pattern transfer of micro mechanical structure to the pattern forming after photoresist.Photoetching agent pattern transfer technique is the common technology of field of lithography, is not repeated herein.Photoresist, in follow-up dry etch step, is erosion-resisting substantially, can not be etched away.Therefore the substrate layer under photoresist covers and protects is retained, and substrate layer not covered by photoresist can be etched away.It should be noted that, in microelectromechanical systems processing technology, often need to be processed to form through hole, also can relate to hole etching.Photoresist anti-etching ability in dry etching, has determined whether the size of through hole can meet predetermined requirement.In traditional etching technics; often there will be photoresist side to be corroded, cause the size of through hole to become large problem, in Fig. 2; the through hole expection forming on photoresist pattern layer 30 should be solid line edge, but because of excessive erosion, expands in practice dotted line edge to.For this reason, in traditional technological process, add step S103.
S103: whole silicon chip is heated and ultraviolet treatment with irradiation.In this step, first carry out heat treated, then carry out ultraviolet treatment with irradiation.Through heat treated, the aqueous vapor of photoresist pattern layer 30 substrate layer 20 below can discharge, particularly, for the polyimides of the easy moisture absorption, the heat treatment in early stage contributes to the volatilization of the inside aqueous vapor, and follow-up like this action of ultraviolet radiation just can not produce large impact to substrate layer 20.In addition; through heat treated; photoresist can be heated uniformly; after being heated, photoresist distributes more uniformly; although what can make like this that the size of original figure becomes is bigger; but can in follow-up UV treatment process, make photoresist more anti-etching, thereby reach the object of better protection substrate layer etch topography and critical size.The temperature of described heat treated is between 110～130 ℃, is preferably 120 ℃.Too low temperature can not function as described above, and too high temperature can affect the performance of substrate layer 20.
On the other hand, ultraviolet irradiation can be strengthened the anti-etching ability of photoresist.In the present embodiment, the ultraviolet frequencies adopting is 2.45GHz, and intensity is 100～125mW/cm
2, be preferably 110mW/cm
2.
The time of this step process is 1～1.5 minute.
S104: carry out dry etching.Through after the step of above-mentioned S101～S103, can carry out the step of dry etching.Dry etching is generally the method for using plasma bombardment.After this step, substrate layer 20 not covered by photoresist is etched away, thereby forms micro mechanical structure, with reference to figure 3.
Said method, owing to irradiating through heat treated and ultraviolet ray, strengthens the anti-etching ability of photoresist, there will not be as in conventional art because photoresist side is by the size of excessive corrosion micro mechanical structure problem bigger than normal.Through test, change in size can be controlled at 20 nanometer left and right.Therefore can guarantee the uniformity of hole etching size.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (9)
1. a processing method for microelectromechanical systems, comprises the steps:
On silicon chip, form substrate layer;
On described substrate layer, form photoresist pattern layer;
Whole silicon chip is heated and ultraviolet treatment with irradiation;
Carry out dry etching.
2. the processing method of microelectromechanical systems according to claim 1, is characterized in that, described to whole silicon chip heat and the step of ultraviolet treatment with irradiation in, first carry out heat treated, then carry out ultraviolet treatment with irradiation.
3. the processing method of microelectromechanical systems according to claim 1, is characterized in that, the temperature of described heat treated is 110～130 ℃.
4. the processing method of microelectromechanical systems according to claim 1, is characterized in that, the temperature of described heat treated is 120 ℃.
5. the processing method of microelectromechanical systems according to claim 1, is characterized in that, described ultraviolet frequency is 2.45GHz.
6. the processing method of microelectromechanical systems according to claim 1, is characterized in that, described ultraviolet intensity is 100～125mW/cm
2.
7. the processing method of microelectromechanical systems according to claim 1, is characterized in that, described ultraviolet intensity is 110mW/cm
2.
8. the processing method of microelectromechanical systems according to claim 1, is characterized in that, described whole silicon chip is heated and time of ultraviolet treatment with irradiation is 1～1.5 minute.
9. the processing method of microelectromechanical systems according to claim 1, is characterized in that, described substrate layer adopts polyimide material to make.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108520856A (en) * | 2018-05-18 | 2018-09-11 | 中国科学院微电子研究所 | A kind of patterning method of ito thin film |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214524B1 (en) * | 1997-10-03 | 2001-04-10 | Fusion Systems Corporation | Controlled amine poisoning for reduced shrinkage of features formed in photoresist |
| US6306780B1 (en) * | 2000-02-07 | 2001-10-23 | Agere Systems Guardian Corp. | Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation |
| US20080041816A1 (en) * | 2006-08-16 | 2008-02-21 | Samsung Electronics Co., Ltd. | Systems and methods for manufacturing wire grid polarizers |
| CN101561629A (en) * | 2008-04-16 | 2009-10-21 | 中国科学院微电子研究所 | Method for manufacturing gradual slope of medium edge by photoresist with inverse trapezium section |
| CN101863447A (en) * | 2009-04-15 | 2010-10-20 | 中国科学院半导体研究所 | Method for manufacturing sloped sidewall silicon dioxide structure by adopting photoetching and dry etching |
-
2013
- 2013-03-21 CN CN201310092536.6A patent/CN104058362B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214524B1 (en) * | 1997-10-03 | 2001-04-10 | Fusion Systems Corporation | Controlled amine poisoning for reduced shrinkage of features formed in photoresist |
| US6306780B1 (en) * | 2000-02-07 | 2001-10-23 | Agere Systems Guardian Corp. | Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation |
| US20080041816A1 (en) * | 2006-08-16 | 2008-02-21 | Samsung Electronics Co., Ltd. | Systems and methods for manufacturing wire grid polarizers |
| CN101561629A (en) * | 2008-04-16 | 2009-10-21 | 中国科学院微电子研究所 | Method for manufacturing gradual slope of medium edge by photoresist with inverse trapezium section |
| CN101863447A (en) * | 2009-04-15 | 2010-10-20 | 中国科学院半导体研究所 | Method for manufacturing sloped sidewall silicon dioxide structure by adopting photoetching and dry etching |
Non-Patent Citations (1)
| Title |
|---|
| 潘桂忠: "《MOS集成电路工艺与制造技术》", 30 June 2012, 上海科学技术出版社 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108520856A (en) * | 2018-05-18 | 2018-09-11 | 中国科学院微电子研究所 | A kind of patterning method of ito thin film |
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Effective date of registration: 20170926 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |