CN104050923B - 像素电路及采用此像素电路的显示设备 - Google Patents
像素电路及采用此像素电路的显示设备 Download PDFInfo
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Abstract
一种像素电路及采用此像素电路的显示设备。像素电路包括第一至第四晶体管、第一至第二电容及发光组件。第一晶体管的闸极接收扫描讯号,其一源/汲极接收显示数据,另一源/汲极电性耦接第三晶体管的闸极,并通过第一电容电性耦接第二晶体管的其一源/汲极。第二晶体管的闸极与其一源/汲极通过第二电容接收重置讯号,另一源/汲极接收开关讯号。第四晶体管的闸极接收致能讯号,其一源/汲极电性耦接第一电源电压,另一源/汲极通过第三晶体管电性耦接发光组件的阳极。发光组件的阴极电性耦接第二电源电压。第二电源电压小于第一电源电压。本发明可有效地改善面板显示不均匀的问题以及发光组件的材料衰变的问题,进而提供高质量的显示画面。
Description
技术领域
本发明是有关于一种有机发光二极管的显示技术领域,尤其是有关于一种有机发光二极管的像素电路及采用此像素电路的显示设备。
背景技术
有机发光二极管(OrganicLightEmittingDiode,OLED)显示设备中的每一个像素电路一般以二个晶体管搭配一个电容来控制有机发光二极管的亮度表现。但是现有像素电路于电路设计上往往会造成面板显示不均匀的问题,以图1来说明之。
图1即为传统像素电路的示意图。如图1所示,此种像素电路100一般由二个晶体管101与晶体管102、一个电容103以及有机发光二极管104所组成。晶体管101的闸极与其一源/汲极分别适用于接收扫描讯号SCAN与显示数据DATA,晶体管102的另一源/汲极则电性耦接至晶体管101的闸极,并通过电容103电性耦接至电源电压OVDD与晶体管102的其一源/汲极。晶体管102的另一源/汲极电性耦接至有机发光二极管104的阳极。有机发光二极管104的阴极电性耦接至电源电压OVSS,此电源电压OVSS小于所述的电源电压OVDD。这样的像素电路架构是藉由晶体管102的闸极与源极的跨压VGS控制流过晶体管102的电流大小,即流过有机发光二极管104的像素电流IOLED=K*(VGS-|Vth|)2。在此例中,K为常数,VGS的大小相关于显示数据DATA的电压大小,Vth为晶体管102的临界电压(ThresholdVoltage)。
然而,由于这种有机发光二极管显示设备中的电源电压OVDD是通过金属线将每一个像素电路互相电性耦接一起,当驱动有机发光二极管104发亮时,因金属线上本身具有阻抗,所以会有电源电压降(IR-drop)的存在,使得每一个像素电路所接收的电源电压OVDD产生差异而造成每一个像素电路的像素电流IOLED会有差异,使得流过每一个有机发光二极管104的电流不同而其所发出的亮度就会不同,进而造成面板显示不均匀的问题。另外,由于制程的影响,每一个像素电路中的晶体管102的临界电压Vth均不相同,导致有机发光二极管显示设备中的每一个像素电路的像素电流IOLED会有差异,使得流过每一个有机发光二极管104的电流不同而其所发出的亮度就会不同,亦会造成面板显示不均匀的问题。
发明内容
本发明提出一种像素电路,其可改善面板显示不均匀的问题。
本发明另提出一种显示设备,其采用上述的像素电路。
本发明提供的像素电路,其包括第一至第四晶体管、第一至第二电容以及发光组件。其中,第一晶体管具有第一闸极、第一源/汲极与第二源/汲极,第一闸极适用于接收扫描讯号,第一源/汲极则适用于接收显示数据。第一电容具有第一端与第二端,第一端电性耦接第二源/汲极。第二晶体管具有第二闸极、第三源/汲极与第四源/汲极,第二闸极电性耦接第三源/汲极与第一电容的第二端,第四源/汲极适用于接收开关讯号。第二电容具有第三端与第四端,第三端适用于接收重置讯号,第四端电性耦接第一电容的第二端。第三晶体管具有第三闸极、第五源/汲极与第六源/汲极,第三闸极电性耦接第一电容的第一端。第四晶体管具有第四闸极、第七源/汲极与第八源/汲极,第四闸极适用于接收致能讯号,第七源/汲极电性耦接第一电源电压,第八源/汲极电性耦接第五源/汲极。发光组件具有阳极与阴极,阳极电性耦接第六源/汲极,阴极则电性耦接第二电源电压,第二电源电压小于第一电源电压。
本发明另提供的显示设备,其包括显示面板、数据驱动器以及扫描驱动器。显示面板具有像素电路,此像素电路包括第一至第四晶体管、第一至第二电容以及发光组件。其中,第一晶体管具有第一闸极、第一源/汲极与第二源/汲极,第一闸极适用于接收扫描讯号,第一源/汲极则适用于接收显示数据。第一电容具有第一端与第二端,第一端电性耦接第二源/汲极。第二晶体管具有第二闸极、第三源/汲极与第四源/汲极,第二闸极电性耦接第三源/汲极与第一电容的第二端,第四源/汲极适用于接收开关讯号。第二电容具有第三端与第四端,第三端适用于接收重置讯号,第四端电性耦接第一电容的第二端。第三晶体管具有第三闸极、第五源/汲极与第六源/汲极,第三闸极电性耦接第一电容的第一端。第四晶体管具有第四闸极、第七源/汲极与第八源/汲极,第四闸极适用于接收致能讯号,第七源/汲极电性耦接第一电源电压,第八源/汲极电性耦接第五源/汲极。发光组件具有阳极与阴极,阳极电性耦接第六源/汲极,阴极则电性耦接第二电源电压,第二电源电压小于第一电源电压。数据驱动器用以提供上述显示数据。扫描驱动器用以提供上述扫描讯号、开关讯号、重置讯号与致能讯号,并在预充电期间中将扫描讯号与致能讯号呈现高准位,而将开关讯号呈现低准位,在重置补偿期间中将扫描讯号、开关讯号与致能讯号呈现高准位,在写入期间中将扫描讯号与开关讯号呈现高准位,而将致能讯号与重置讯号呈现低准位,在发光期间中将扫描讯号与重置讯号呈现低准位,而将开关讯号与致能讯号呈现高准位,其中重置补偿期间在预充电期间之后,写入期间在重置补偿期间之后,而发光期间在写入期间之后。
本发明解决前述问题的方式,乃是以四个晶体管、二个电容及一个发光组件来进行像素电路结构的设计。借着这种像素电路结构的设计,可使流过发光组件的像素电流相关于电容与显示数据。因此,本发明实施例提出的像素电路及采用此像素电路的显示设备可有效地改善面板显示不均匀的问题以及发光组件的材料衰变的问题,进而提供高质量的显示画面。
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图说明
图1为传统像素电路的示意图。
图2为依照本发明一实施例的像素电路的示意图。
图3绘示图2所示像素电路的各个讯号的时序图。
图4(A)绘示传统像素电路的实验仿真示意图。
图4(B)绘示本发明像素电路的实验仿真示意图。
图5为依照本发明一实施例的显示设备的示意图。
其中,附图标记
100、200:像素电路
101、102、201、203、205、206:晶体管
103、202、204:电容
104:有机发光二极管
SCAN:扫描讯号
DATA:显示数据
OVDD、OVSS:电源电压
IOLED:像素电流
207:发光组件
SW:开关讯号
RESET:重置讯号
EM:致能讯号
301:预充电期间
302:重置补偿期间
303:写入期间
304:发光期间
G、S:接点
Vlow:开关讯号的低准位电压
Vref:显示数据的参考电压
400:显示设备
410:显示面板
411:像素电路
420:数据驱动器
430:扫描驱动器
440:电源电压供应器
具体实施方式
下面结合附图和具体实施例对本发明技术方案进行详细的描述,以更进一步了解本发明的目的、方案及功效,但并非作为本发明所附权利要求保护范围的限制。
图2为依照本发明一实施例的像素电路的示意图。请参照图2,此像素电路200由晶体管201、电容202、晶体管203、电容204、晶体管205、晶体管206以及发光组件207所组成。晶体管201的闸极适用于接收扫描讯号SCAN,其一源/汲极则适用于接收显示数据DATA。电容202的其一端电性耦接晶体管201的另一源/汲极。晶体管203的闸极电性耦接晶体管203的其一源/汲极与电容202的另一端,而另一源/汲极适用于接收开关讯号SW。电容204的其一端适用于接收重置讯号RESET,而另一端则电性耦接电容202的另一端。晶体管205的闸极电性耦接电容202的其一端。晶体管206的闸极适用于接收致能讯号EM,其一源/汲极电性耦接电源电压DVDD,而另一源/汲极则电性耦接晶体管205的其一源/汲极。发光组件207的阳极电性耦接晶体管205的另一源/汲极,而阴极则电性耦接电源电压OVSS,此电源电压OVSS小于电源电压DVDD。在本实施例中,所述的发光组件207即采用有机发光二极管来实现。
图3绘示图2所示像素电路的各个讯号的时序图。在图3中,标示与图2的标示相同者表示为相同的讯号。此外,在图3中,以301来表示为像素电路200的预充电期间,以302来表示为像素电路200的重置补偿期间,以303来表示为像素电路200的写入期间,以304来表示为像素电路200的发光期间,而所述的重置补偿期间302在预充电期间301之后,写入期间303在重置补偿期间302之后,而发光期间304则在写入期间303之后。
请同时参照图3与图2,在预充电期间301中,扫描讯号SCAN与致能讯号EM皆为高准位,而开关讯号SW则为低准位。由于扫描讯号SCAN与致能讯号EM皆为高准位与开关讯号SW为低准位的情形下,将使得晶体管201与晶体管206皆为导通状态。而由于在预充电期间301中,重置讯号RESET的上升缘在扫描讯号SCAN的上升缘与开关讯号SW的下降缘之后,将使得晶体管203亦为导通状态。此时,接点G的电压大小与接点S的电压大小可分别由下列式(1)与式(2)来表示:
VG=Vref……(1)
VS=Vlow+Vth’……(2)
其中,VG表示为接点G的电压大小,VS表示为接点S的电压大小,Vref表示为显示数据DATA的参考电压,Vlow表示为开关讯号SW的低准位电压,Vth’表示为晶体管203的临界电压。
接着,在重置补偿期间302中,扫描讯号SCAN、开关讯号SW与致能讯号EM皆为高准位。由于扫描讯号SCAN、开关讯号SW与致能讯号EM皆为高准位的情形下,将使得晶体管201与晶体管206皆为导通状态。而由于在重置补偿期间302中,重置讯号RESET的下降缘在开关讯号SW的上升缘之后,将使得晶体管203为关闭状态。此时,接点G的电压大小与接点S的电压大小可分别由下列式(3)与式(4)来表示:
VG=Vref……(3)
VS=Vref-Vth……(4)
其中,VG表示为接点G的电压大小,VS表示为接点S的电压大小,Vref表示为显示数据DATA的参考电压,Vth表示为晶体管205的临界电压。
在此例中,重置讯号RESET不需要重置到低准位电压,一旦接点G与接点S之间的压差大于晶体管205的临界电压Vth,像素电路200便可立即执行补偿操作,以图4(A)及图4(B)来举例说明之。图4(A)绘示传统像素电路100的实验仿真示意图,图4(B)则绘示本发明像素电路200的实验仿真示意图。从图4(A)可看出,传统像素电路100需要经由重置期间将接点S的电压大小重置到大约-3.2V的电压,才能够使像素电路100执行补偿操作;而从图4(B)可看出,像素电路200则不需要经由重置期间将接点S的电压大小重置到大约-3.2V的电压,仅需要将接点S的电压大小重置到大约-0.4V的电压,便能够使像素电路200立即执行补偿操作。如此一来,本发明的像素电路200即可在短时间之内执行重置补偿操作。
然后,在写入期间303中,扫描讯号SCAN与开关讯号SW皆为高准位,而致能讯号EM与重置讯号RESET则为低准位。由于扫描讯号SCAN与开关讯号SW皆为高准位的情形下,将使得晶体管201为导通状态。而由于致能讯号EM与重置讯号RESET为低准位的情形下,将使得晶体管203与晶体管206皆为关闭状态。此时,接点G的电压大小与接点S的电压大小可分别由下列式(5)与式(6)来表示:
VG=VDATA……(5)
VS=Vref-Vth+dV……(6)
其中,VG表示为接点G的电压大小,VS表示为接点S的电压大小,VDATA表示为显示数据DATA的电压,Vref表示为显示数据DATA的参考电压,C1为电容202的电容值,C2为电容204的电容值。
最后,在发光期间304中,由于开关讯号SW与致能讯号EM皆为高准位的情形下,将使得晶体管206为导通状态。而由于扫描讯号SCAN与重置讯号RESET皆为低准位的情形下,将使得晶体管201与晶体管203皆为关闭状态。此时,接点G的电压大小与接点S的电压大小可分别由下列式(7)与式(8)来表示:
VG=VDATA+OVSS+VOLED-Vref+Vth-dV……(7)
VS=OVSS+VOLED……(8)
其中,VG表示为接点G的电压大小,VS表示为接点S的电压大小,VDATA表示为显示数据DATA的电压,OVSS表示为电源电压,VOLED表示为发光组件207的跨压,Vref表示为显示数据DATA的参考电压,Vth表示为晶体管205的临界电压,C1为电容202的电容值,C2为电容204的电容值。此时,将接点G与接点S(即VGS电压)跨压大小可由下列式(9)来表示:
VGS=VDATA-Vref+Vth-dV……(9)
而流过发光组件207的电流大小可由下列式(10)来表示:
IOLED=K*(VGS-|Vth|)2……(10)
将上述式(9)代入式(10)中,便可得出下列式(11):
IOLED=K*(VDATA-Vref-dV)2……(11)
藉由式(11)可知,在发光期间304中,流过发光组件207的像素电流IOLED和电容202与电容204的电容值、显示数据DATA有关。如此一来,发光组件207因电源电压降(IR-drop)影响及制程对晶体管205的临界电压Vth影响而造成面板显示不均匀的问题即可以得到有效改善,进而提供高质量的显示画面。
图5为依照本发明一实施例的显示设备的示意图。请参照图5,显示设备400以有机发光二极管显示设备来实现,而此显示设备400包括显示面板410、数据驱动器420、扫描驱动器430与电源电压供应器440。显示面板410具有多个像素电路411,每一个像素电路411皆以图2所示的像素电路200来实现,因此在每一个像素电路411中,标示与图2的标示相同者表示为相同的组件或讯号。事实上,在每一个像素电路411中,晶体管201的闸极通过一扫描讯号线来接收扫描驱动器430所提供的扫描讯号SCAN,而其一源/汲极则通过一数据讯号线来接收数据驱动器420所提供的显示数据DATA。晶体管203的另一源/汲极通过一开关讯号线来接收扫描驱动器430所提供的开关讯号SW。电容204的其一端通过一重置讯号线来接收扫描驱动器430所提供的重置讯号RESET。晶体管206的闸极通过一致能讯号线来接收扫描驱动器430所提供的致能讯号EM,而其一源/汲极通过一电源线电性耦接至电源电压供应器440供应的电源电压OVDD。发光组件207的阴极电性耦接至电源电压OVSS,此电源电压OVSS即为接地电压,也就是发光组件207的阴极一般电性耦接至接地电压,但在其他实施例中,此发光组件207的阴极可通过另一电源线电性耦接至电源电压供应器440供应的电源电压OVSS,只要电源电压OVSS小于上述电源电压OVDD即可。
在本实施例中,上述的扫描驱动器430可按照图3所示的讯号时序来驱动每一个像素电路411。请同时参照图5与图3。事实上,扫描驱动器430在预充电期间310中将扫描讯号SCAN与致能讯号EM呈现高准位,而将开关讯号SW呈现低准位,使得晶体管201、晶体管203与晶体管206皆为导通状态。扫描驱动器430在重置补偿期间302中将扫描讯号SCAN、开关讯号SW与致能讯号EM呈现高准位,使得晶体管201与晶体管206皆为导通状态,并使得晶体管203为关闭状态。扫描驱动器430在写入期间303中将扫描讯号SCAN与开关讯号SW呈现高准位,而将致能讯号EM与重置讯号RESET呈现低准位,使得晶体管201为导通状态,并使得晶体管203与晶体管206皆为关闭状态。扫描驱动器430在发光期间304中将扫描讯号SCAN与重置讯号RESET呈现低准位,而将开关讯号SW与致能讯号EM呈现高准位,使得晶体管206为导通状态,并使得晶体管201与晶体管203皆为关闭状态。其中,所述的重置补偿期间302在预充电期间301之后,写入期间303在重置补偿期间302之后,而发光期间304在写入期间303之后。
综上所述,本发明解决前述问题的方式,乃是以四个晶体管、二个电容及一个发光组件来进行像素电路结构的设计。借着这种像素电路结构的设计,可使流过发光组件的像素电流相关于电容与显示数据。因此,本发明实施例提出的像素电路及采用此像素电路的显示设备可有效地改善面板显示不均匀的问题以及发光组件的材料衰变的问题,进而提供高质量的显示画面。
当然,本发明还可有其它多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (11)
1.一种像素电路,其特征在于,包括:
一第一晶体管,具有一第一闸极、一第一源/汲极与一第二源/汲极,该第一闸极适用于接收一扫描讯号,该第一源/汲极则适用于接收一显示数据;
一第一电容,具有一第一端与一第二端,该第一端电性耦接该第二源/汲极;
一第二晶体管,具有一第二闸极、一第三源/汲极与一第四源/汲极,该第二闸极电性耦接该第三源/汲极与该第一电容的该第二端,该第四源/汲极适用于接收一开关讯号;
一第二电容,具有一第三端与一第四端,该第三端适用于接收一重置讯号,该第四端电性耦接该第一电容的该第二端;
一第三晶体管,具有一第三闸极、一第五源/汲极与一第六源/汲极,该第三闸极电性耦接该第一电容的该第一端;
一第四晶体管,具有一第四闸极、一第七源/汲极与一第八源/汲极,该第四闸极适用于接收一致能讯号,该第七源/汲极电性耦接一第一电源电压,该第八源/汲极电性耦接该第五源/汲极;以及
一发光组件,具有一阳极与一阴极,该阳极电性耦接该第六源/汲极,该阴极则电性耦接一第二电源电压,该第二电源电压小于该第一电源电压。
2.如权利要求1所述的像素电路,其特征在于,在一预充电期间中,该扫描讯号与该致能讯号皆为高准位,而该开关讯号则为低准位,在一重置补偿期间中,该扫描讯号、该开关讯号与该致能讯号皆为高准位,在一写入期间中,该扫描讯号与该开关讯号皆为高准位,而该致能讯号与该重置讯号则为低准位,在一发光期间中,该扫描讯号与该重置讯号皆为低准位,而该开关讯号与该致能讯号皆为高准位,其中该重置补偿期间在该预充电期间之后,该写入期间在该重置补偿期间之后,而该发光期间在该写入期间之后。
3.如权利要求2所述的像素电路,其特征在于,在该预充电期间中,该重置讯号的上升缘在该扫描讯号的上升缘与该开关讯号的下降缘之后,在该重置补偿期间中,该重置讯号的下降缘在该开关讯号的上升缘之后。
4.如权利要求1所述的像素电路,其特征在于,该发光组件以一有机发光二极管来实现。
5.如权利要求1所述的像素电路,其特征在于,该第一晶体管、该第二晶体管、该第三晶体管与该第四晶体管皆以一薄膜晶体管来实现。
6.一种显示设备,其特征在于,包括:
一显示面板,具有一像素电路,该像素电路包括一第一晶体管、一第一电容、一第二晶体管、一第二电容、一第三晶体管、一第四晶体管、以及一发光组件,该第一晶体管具有一第一闸极、一第一源/汲极与一第二源/汲极,该第一闸极适用于接收一扫描讯号,该第一源/汲极则适用于接收一显示数据;该第一电容具有一第一端与一第二端,该第一端电性耦接该第二源/汲极;该第二晶体管具有一第二闸极、一第三源/汲极与一第四源/汲极,该第二闸极电性耦接该第三源/汲极与该第一电容的该第二端,该第四源/汲极适用于接收一开关讯号;该第二电容具有一第三端与一第四端,该第三端适用于接收一重置讯号,该第四端电性耦接该第一电容的该第二端;该第三晶体管具有一第三闸极、一第五源/汲极与一第六源/汲极,该第三闸极电性耦接该第一电容的该第一端;该第四晶体管具有一第四闸极、一第七源/汲极与一第八源/汲极,该第四闸极适用于接收一致能讯号,该第七源/汲极电性耦接一第一电源电压,该第八源/汲极电性耦接该第五源/汲极;该发光组件具有一阳极与一阴极,该阳极电性耦接该第六源/汲极,该阴极则电性耦接一第二电源电压,该第二电源电压小于该第一电源电压;
一数据驱动器,用以提供该显示数据;以及
一扫描驱动器,用以提供该扫描讯号、该开关讯号、该重置讯号与该致能讯号,并在一预充电期间中将该扫描讯号与该致能讯号呈现高准位,而将该开关讯号呈现低准位,在一重置补偿期间中将该扫描讯号、该开关讯号与该致能讯号呈现高准位,在一写入期间中将该扫描讯号与该开关讯号呈现高准位,而将该致能讯号与该重置讯号呈现低准位,在一发光期间中将该扫描讯号与该重置讯号呈现低准位,而将该开关讯号与该致能讯号呈现高准位,其中该重置补偿期间在该预充电期间之后,该写入期间在该重置补偿期间之后,而该发光期间在该写入期间之后。
7.如权利要求6所述的显示设备,其特征在于,在该预充电期间中,该重置讯号的上升缘在该扫描讯号的上升缘与该开关讯号的下降缘之后,在该重置补偿期间中,该重置讯号的下降缘在该开关讯号的上升缘之后。
8.如权利要求6所述的显示设备,其特征在于,该发光组件以一有机发光二极管来实现。
9.如权利要求6所述的显示设备,其特征在于,该第一晶体管、该第二晶体管、该第三晶体管与该第四晶体管皆以一薄膜晶体管来实现。
10.如权利要求6所述的显示设备,其特征在于,更包括一电源电压供应器,该电源电压供应器用以供应该第一电源电压与该第二电源电压。
11.如权利要求6所述的显示设备,其特征在于,以一有机发光二极管显示设备来实现。
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