CN104038230A - Focal-plane block-matrix transformation column-parallel arithmetic analog-digital conversion method and converter - Google Patents

Abstract

The invention relates to the field of integrated circuits in microelectronics, and provides a novel column parallel arithmetic ADC used for achieving accumulation operation in block matrix transformation. Accordingly, the accumulation operation in block matrix transformation becomes an inherent part in the ADC quantization process, hardware resources can not be increased too many, and processing efficiency can be guaranteed. According to the technical scheme, the focal-plane block-matrix transformation column parallel arithmetic ADC comprises a first adding device, a second adding device, a multiplier and a third adding device connected in sequence. The output of the first adding device is compared with reference voltage through a first comparator, and a comparison result is output to the second adding device; the output of the multiplier is compared with the reference voltage through a second comparator, and the comparison result is output to the third adding device; the output of the third adding device is fed back to the first adding device through a delayer. The focal-plane block-matrix transformation column parallel arithmetic analog-digital conversion method is mainly applied to design and manufacturing of integrated circuits.

Description

Focal plane block matrix conversion row parallel arithmetic D conversion method and transducer

Technical field

The present invention relates to microelectronic integrated circuit fields, relate in particular to row parallel A/D converter.Specifically, relate to the row parallel arithmetic analog to digital converter for realizing focal plane block matrix conversion.

Technical background

In the last few years, cmos image sensor (CIS) rely on its can integrated, the low area of monolithic and the advantage such as low-power consumption become gradually the mainstream technology means in video acquisition field.In the field such as wireless sensing and biologic medical, for being preserved and transmitted, the data of magnanimity need to pay expensive cost.The pressure that relieve transmission bandwidth is subject to significantly video processing technique such as image compression, but this needs accurate DSP (digital signal processor) to complete corresponding block matrix conversion operations conventionally, and the power consumption that it is shared and area are all huge.

The image focal plane compress technique that sensor based system realizes can effectively reduce area and the power consumption of chip, and it can utilize the high accuracy of the low-power consumption of analog circuit, low area and digital circuit simultaneously.But this compressed format is also faced with many challenges: on focal plane, limited silicon area is restricting the complexity of circuit, lower signal to noise ratio (SNR), and between limited circuit resource and the image compression algorithm of complexity, carry out suitable compromise.Block matrix is changed as a kind of Image Lossy Compression algorithm, relies on its larger compression ratio to be widely used in many video acquisitions and process field.

Inventor finds that mostly the existing block matrix conversion method based on focal plane is to utilize the ratio of capacitance in switched-capacitor circuit to complete the multiply operation of pixel value and corresponding core coefficient, and the means such as recycling simulation accumulator complete cumulative operation.All operations all completes in analog domain, does like this and can make the shortcoming of analog circuit unintentional nonlinearity and low precision highlight, and the result precision of image processing is very limited.In addition, added the treatment cycle that can greatly increase CIS for the circuit module of block matrix conversion.

Summary of the invention

In order to overcome the deficiencies in the prior art, provide a kind of novel row parallel arithmetic ADC, for realizing the cumulative operation of block matrix conversion.Make the cumulative operation in block matrix conversion become a part intrinsic in ADC quantizing process, and do not make the too much increase of hardware resource, therefore make treatment effeciency also be ensured.For this reason, the technical scheme that the present invention takes is that focal plane block matrix conversion row parallel arithmetic analog to digital converter, comprising: connected first adder, second adder, multiplier, the 3rd adder successively; The output of first adder is also through the first comparator and reference voltage comparison, and comparative result outputs to second adder; The output of multiplier is also through the second comparator and reference voltage comparison, and comparative result outputs to the 3rd adder; The output of the 3rd adder feeds back to first adder through delayer.

Multiplier is paired multiplier.

Focal plane block matrix conversion row parallel arithmetic D conversion method: adopt discrete input signal P[k], be a T in following formula _{ij, h}:

$\underset{h=1}{\overset{H}{\mathrm{\Σ}}}\underset{v=1}{\overset{V}{\mathrm{\Σ}}}{C}_{\mathrm{hv}}{I}_{\mathrm{xy}}=\underset{h=1}{\overset{H}{\mathrm{\Σ}}}{T}_{\mathrm{ij},h}$

Above formula is the formula of block matrix conversion, wherein I _xythe pixel value of correspondence position, C _hvit is corresponding core coefficient; Each T _ijall obtained by h × v multiply operation and cumulative operation, wherein h and v line number and the columns of presentation video respectively;

Above-mentioned input signal is inputted to aforementioned arithmetic module number converter, suppose that described ADC quantified precision is N bit, the period 1 finishes rear residual value and is so:

w ₂[1]＝2(P[1]-d ₁[1])-d ₂[1] (1)

In a remaining N-1 cycle, residual value is:

w ₂[k]＝2(P[k]+w ₂[k-1]-d ₁[k]-d ₂[k]),k＝2,3...,N. (2)

After being added up according to its binary weights, the residual value in this N cycle can obtain:

$\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-(k+1)}\left({2d}_1\right[k]+d_2[k\left]\right)=\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-k}P\left[k\right]-2^{-(N+1)}{w}_2\left[N\right]---\left(3\right)$

After being converted, above formula can obtain:

$\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-(k+1)}\left({2d}_1\right[k]+d_2[k\left]\right)=T_{\mathrm{ij},h}---\left(4\right)$

Wherein, w ₂[k] represents the k time output of the 3rd adder, d ₁[k], d ₂[k] represents respectively the k time output of the first comparator, the second comparator;

To T _{ij, h}after adding up, obtain a core coefficient after conversion, from formula (6), can find out and will calculate T _{ij, h}also will to the 2 bit number character codes that extract take advantage of two and be added operation, these action needs utilize adder to complete in numeric field.

In numeric field, utilize adder to complete specifically, adder first will be according to weight by d ₁[k], d ₂[k] is transformed into numeric field from analog domain and stores, then carries out add operation.

Compared with the prior art, technical characterstic of the present invention and effect:

The present invention proposes a kind of arithmetic type ADC for the conversion of focal plane block matrix.By traditional circular form ADC is improved, add an analog comparator module and block matrix is converted to required cumulative operation be dissolved in ADC, become a part intrinsic in ADC quantizing process, greatly improve treatment effeciency.Avoid traditional image focal plane compression method due to all operations is all completed and caused non-linear and low precision in analog domain, and owing to not needing a large amount of switched-capacitor circuits, can make the area of circuit and power consumption significantly reduce.

Brief description of the drawings

Fig. 1 is structure chart and the fundamental diagram of traditional cyclic analog-to-digital converters;

Fig. 2 is structure chart and the fundamental diagram after the present invention makes improvements;

Fig. 3 is the adder structure figure that d1 and d2 will be carried out to add operation.

In figure, 2 fingers are taken advantage of 2 operations to the magnitude of voltage of input;

Square frame and inner waveform thereof refer to input voltage and reference voltage are compared to produce comparative result d1 or d2;

What Z-1 represented is delay operation, for turning back to input port after output valve time delay a period of time;

Embodiment

The technical scheme that the present invention takes is:

$T_{\mathrm{ij}}=\underset{h=1}{\overset{H}{\mathrm{\Σ}}}\underset{v=1}{\overset{V}{\mathrm{\Σ}}}{C}_{\mathrm{hv}}{I}_{\mathrm{xy}}=\underset{h=1}{\overset{H}{\mathrm{\Σ}}}{T}_{\mathrm{ij},h}---\left(5\right)$

Above formula is the formula of block matrix conversion, and wherein Ixy is the pixel value of correspondence position, and Chv is corresponding core coefficient.Can find out, each Tij is obtained by h × v multiply operation and cumulative operation, wherein h and v line number and the columns of presentation video respectively.First traditional focal plane block matrix conversion method normally utilizes switched-capacitor circuit to complete the multiply operation of pixel value and corresponding core coefficient, next utilizes simulation accumulator to complete twice required cumulative operation.Due to analog circuit unintentional nonlinearity, completing such complex calculations can have a huge impact result.

By observing above-mentioned operational formula the characteristic in conjunction with traditional cyclic analog-to-digital converters (ADC), inventor finds can be by being dissolved into cumulative operation in ADC and becoming the intrinsic part of its course of work the improvement of ADC structure.

The structure chart of tradition circular form ADC and fundamental diagram, referring to Fig. 1, are sampled to input signal in first cycle, difference are fed back and carry out the quantification work of next circulation extract a quantized result by comparator after.Because each cycle value to be quantified is all few 1 in binary weights than the value in last cycle, therefore before starting, circulation also to take advantage of 2 amplitude ranges of processing to keep input value to difference.In order to incorporate accumulation function in traditional circular form ADC, the present invention proposes a kind of new A DC structure, structured flowchart and schematic diagram are referring to Fig. 2.The prerequisite that adopts this structure is that input signal must be discrete, supposes that input signal expression formula is:

P[k]＝Ic[k] (6)

P[k] be a Tij in former formula, h.Different with traditional circular form ADC is, each cycle analog quantity to be quantified is by the P[k newly inputting] and the residual value in a upper cycle be added and obtain, therefore the peak value of comparator input voltage can be by double, and need to adopt circuit structure in Fig. 2 dotted line frame to maintain peak value is normal value.This makes each cycle of this arithmetic ADC can obtain the digital code of 2 bits, is obtained respectively, as shown in Figure 2 by two comparators.After all input variables are all transported in ADC, ADC will carry out work according to the operation principle of traditional circular form ADC until produced the digital code of N bit.

Specific works principle is as follows, supposes that this ADC quantified precision is N bit, and the period 1 finishes rear residual value and is so:

w ₂[1]＝2(P[1]-d ₁[1])-d ₂[1] (7)

In a remaining N-1 cycle, residual value is:

w ₂[k]＝2(P[k]+w ₂[k-1]-d ₁[k]-d ₂[k]),k＝2,3...,N. (8)

After being added up according to its binary weights, the residual value in this N cycle can obtain:

$\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-(k+1)}\left({2d}_1\right[k]+d_2[k\left]\right)=\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-k}P\left[k\right]-2^{-(N+1)}{w}_2\left[N\right]---\left(9\right)$

After being converted, above formula can obtain:

$\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-(k+1)}\left({2d}_1\right[k]+d_2[k\left]\right)=T_{\mathrm{ij},h}---\left(10\right)$

To Tij, after adding up, h just can obtain a core coefficient after conversion, from formula (6), can find out and will calculate Tij, h also will to the 2 bit number character codes that extract take advantage of two and be added operation, these action needs utilize adder to complete in numeric field, as shown in Figure 3, first this adder will be transformed into numeric field by d1 and d2 from analog domain according to weight and store, then carry out add operation.

So far, in the process quantizing at ADC, completed block matrix and convert required cumulative operation, and this structure is only than the many analog comparators of traditional circular form ADC, but improved treatment effeciency and conversion accuracy.

For the operation principle of more detailed this arithmetic of elaboration type ADC, the quantizing process of concrete numerical value will be provided below.

Suppose that quantified precision is 8 bits, comparator peak value is 3.3V, and reference voltage is 1.65V, and the discrete variable of input is 2V and 1V.Want to obtain be two input variables by its binary weights cumulative and, desirable result is 2V × 2-1+1V × 2-2=1.25V.

In the time completing above-mentioned cumulative process with this ADC, first, the period 1, while arrival, 2V was transported in ADC, and the digital code that obtains 2 bits is: 1,0, and residual volume is 0.7V.After arriving second round, the input variable 1.7V obtaining after residual volume 0.7V and second input variable 1V are added can be transported in ADC, and 2 bit number character codes of generation are: 1,0, and residual volume is 0.1V.So far, the sampling of all input signals completes, and next will the residual volume of 0.1V be quantized until obtain the digital code of 82 bits according to the operation principle of traditional circular form ADC.Therefore 8 groups of digital codes are respectively: 1,0; 1,0; 0,0; 0,0; 0,0; 0,0; 0,1; 0,1.Therefore can calculate value after quantification according to formula (6) and convert the decimal system to and be about 1.255, and desired result is similar.

Therefore this arithmetic type ADC can successfully be fused to cumulative operation in the quantizing process of ADC.

Claims (4)

1. a focal plane block matrix conversion row parallel arithmetic analog to digital converter, is characterized in that, comprising: connected first adder, second adder, multiplier, the 3rd adder successively; The output of first adder is also through the first comparator and reference voltage comparison, and comparative result outputs to second adder; The output of multiplier is also through the second comparator and reference voltage comparison, and comparative result outputs to the 3rd adder; The output of the 3rd adder feeds back to first adder through delayer.

2. focal plane as claimed in claim 1 block matrix conversion row parallel arithmetic analog to digital converter, is characterized in that, multiplier is paired multiplier.

3. a focal plane block matrix conversion row parallel arithmetic D conversion method, is characterized in that, adopts discrete input signal P[k], be a T in following formula _{ij, h}:

$\underset{h=1}{\overset{H}{\mathrm{\Σ}}}\underset{v=1}{\overset{V}{\mathrm{\Σ}}}{C}_{\mathrm{hv}}{I}_{\mathrm{xy}}=\underset{h=1}{\overset{H}{\mathrm{\Σ}}}{T}_{\mathrm{ij},h}$

Above formula is the formula of block matrix conversion, wherein I _xythe pixel value of correspondence position, C _hvit is corresponding core coefficient; Each T _ijall obtained by h × v multiply operation and cumulative operation, wherein h and v line number and the columns of presentation video respectively;

Above-mentioned input signal is inputted to aforementioned arithmetic module number converter, suppose that described ADC quantified precision is N bit, the period 1 finishes rear residual value and is so:

w ₂[1]＝2(P[1]-d ₁[1])-d ₂[1] (1)

In a remaining N-1 cycle, residual value is:

w ₂[k]＝2(P[k]+w ₂[k-1]-d ₁[k]-d ₂[k]),k＝2,3...,N. (2)

After being added up according to its binary weights, the residual value in this N cycle can obtain:

$\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-(k+1)}\left({2d}_1\right[k]+d_2[k\left]\right)=\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-k}P\left[k\right]-2^{-(N+1)}{w}_2\left[N\right]---\left(3\right)$

After being converted, above formula can obtain:

$\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{2}^{-(k+1)}\left({2d}_1\right[k]+d_2[k\left]\right)=T_{\mathrm{ij},h}---\left(4\right)$

Wherein, w ₂[k] represents the k time output of the 3rd adder, d ₁[k], d ₂[k] represents respectively the k time output of the first comparator, the second comparator;

To T _{ij, h}after adding up, obtain a core coefficient after conversion, from formula (6), can find out and will calculate T _{ij, h}also will to the 2 bit number character codes that extract take advantage of two and be added operation, these action needs utilize adder to complete in numeric field.

4. focal plane as claimed in claim 3 block matrix conversion row parallel arithmetic D conversion method, is characterized in that, in numeric field, utilize adder to complete specifically, adder first will be according to weight by d ₁[k], d ₂[k] is transformed into numeric field from analog domain and stores, then carries out add operation.