CN104038230A

CN104038230A - Focal-plane block-matrix transformation column-parallel arithmetic analog-digital conversion method and converter

Info

Publication number: CN104038230A
Application number: CN201410299022.2A
Authority: CN
Inventors: 姚素英; 于潇; 徐江涛; 史再峰; 高静; 聂凯明; 高志远
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2014-06-26
Filing date: 2014-06-26
Publication date: 2014-09-10
Anticipated expiration: 2034-06-26
Also published as: CN104038230B

Abstract

The invention relates to the field of integrated circuits of microelectronics, and aims to provide a novel column-parallel arithmetic ADC, which is used to realize accumulation operation in block-matrix conversion. The accumulation operation in the block-matrix conversion is made an inherent part of the ADC quantization process, and the hardware resources are not increased too much, so the processing efficiency is also guaranteed. For this reason, the technical solution that the present invention takes is that the focal plane block matrix conversion column parallel arithmetic analog-to-digital converter includes: first adder, second adder, multiplier, third adder connected in sequence; the first adder The output of the multiplier is also compared with the reference voltage by the first comparator, and the comparison result is output to the second adder; the output of the multiplier is also compared with the reference voltage by the second comparator, and the comparison result is output to the third adder; the third adder The output of the device is fed back to the first adder through the delay device. The invention is mainly applied to the design and manufacture of integrated circuits.

Description

Focal plane block matrix conversion column-parallel arithmetic analog-to-digital conversion method and converter

技术领域technical field

本发明涉及微电子学的集成电路领域，尤其涉及列并行模数转换器。具体讲，涉及用于实现焦平面块矩阵转换的列并行算术模数转换器。The present invention relates to the field of integrated circuits of microelectronics, in particular to column-parallel analog-to-digital converters. In particular, it relates to column-parallel arithmetic analog-to-digital converters for implementing focal plane block-matrix conversions.

技术背景technical background

近些年来，CMOS图像传感器(CIS)凭借其可单片集成、低面积和低功耗等优点逐渐成为了视频获取领域的主流技术手段。在无线传感和生物医疗等领域，为了对海量的数据进行保存和传输需要付出昂贵的代价。诸如图像压缩等视频处理技术可以显著地缓解传输带宽受到的压力，但是这通常需要精密的DSP(数字信号处理器)来完成相应的块矩阵转换操作，其所占用的功耗和面积都是巨大的。In recent years, CMOS image sensor (CIS) has gradually become the mainstream technology in the field of video acquisition due to its advantages of monolithic integration, low area and low power consumption. In the fields of wireless sensing and biomedicine, it is expensive to save and transmit massive amounts of data. Video processing technologies such as image compression can significantly relieve the pressure on the transmission bandwidth, but this usually requires a sophisticated DSP (Digital Signal Processor) to complete the corresponding block matrix conversion operation, which consumes a huge amount of power and area of.

基于传感器系统实现的焦平面图像压缩技术能有效的降低芯片的面积和功耗，其可以同时利用模拟电路的低功耗、低面积和数字电路的高精度。但是这种压缩形式也面临着不少挑战：焦平面上有限的硅片面积制约着电路的复杂度，比较低的信噪比(SNR)，并且要在有限的电路资源和复杂的图像压缩算法之间进行适当的折中。块矩阵转换作为一种有损图像压缩算法，凭借其较大的压缩比已经被广泛的应用于许多视频获取和处理领域。The focal plane image compression technology based on the sensor system can effectively reduce the area and power consumption of the chip, and it can take advantage of the low power consumption and area of the analog circuit and the high precision of the digital circuit at the same time. However, this form of compression also faces many challenges: the limited silicon chip area on the focal plane restricts the complexity of the circuit, relatively low signal-to-noise ratio (SNR), and requires limited circuit resources and complex image compression algorithms. Appropriate compromises are made. As a lossy image compression algorithm, block matrix transformation has been widely used in many video acquisition and processing fields due to its large compression ratio.

发明人发现已有的基于焦平面的块矩阵转换方法多是利用开关电容电路中电容值的比例完成像素值和对应核系数的乘法操作，再利用模拟累加器等手段完成累加操作。所有操作都在模拟域中完成，这样做会使模拟电路固有的非线性和低精度的缺点凸显出来，图像处理的结果精度非常有限。此外，添加了用于块矩阵转换的电路模块会大大增大CIS的处理周期。The inventors found that most of the existing focal plane-based block matrix conversion methods use the ratio of the capacitance value in the switched capacitor circuit to complete the multiplication operation of the pixel value and the corresponding kernel coefficient, and then use analog accumulators and other means to complete the accumulation operation. All operations are completed in the analog domain, which will highlight the inherent nonlinearity and low precision of analog circuits, and the accuracy of image processing results is very limited. Furthermore, the addition of circuit blocks for block-matrix conversion greatly increases the processing cycle of the CIS.

发明内容Contents of the invention

为了克服现有技术的不足，提供一种新型的列并行算术ADC，用于实现块矩阵转换中的累加操作。使块矩阵转换中的累加操作成为ADC量化过程中固有的一部分，并且不使硬件资源过多的增加，因此使得处理效率也得以保证。为此，本发明采取的技术方案是，焦平面块矩阵转换列并行算术模数转换器，包括：依次相连的第一加法器、第二加法器、乘法器、第三加法器；第一加法器的输出还经过第一比较器与参考电压比较，比较结果输出到第二加法器；乘法器的输出还经过第二比较器与参考电压比较，比较结果输出到第三加法器；第三加法器的输出经延时器反馈回第一加法器。In order to overcome the deficiencies of the prior art, a novel column-parallel arithmetic ADC is provided for implementing the accumulation operation in block-matrix conversion. The accumulation operation in the block-matrix conversion is made an inherent part of the ADC quantization process, and the hardware resources are not increased too much, so the processing efficiency is also guaranteed. For this reason, the technical solution that the present invention takes is that the focal plane block matrix conversion column parallel arithmetic analog-to-digital converter includes: first adder, second adder, multiplier, third adder connected in sequence; the first adder The output of the multiplier is also compared with the reference voltage by the first comparator, and the comparison result is output to the second adder; the output of the multiplier is also compared with the reference voltage by the second comparator, and the comparison result is output to the third adder; the third adder The output of the device is fed back to the first adder through the delay device.

乘法器为乘二乘法器。The multiplier is a multiplier by two.

焦平面块矩阵转换列并行算术模数转换方法：采用离散输入信号P[k]，即为以下公式中的一个T_ij,h：Focal plane block matrix conversion Column-parallel arithmetic analog-to-digital conversion method: using a discrete input signal P[k], which is a T _ij,h in the following formula:

${Σ Σ}_{h h = = 11}^{H h} {Σ Σ}_{v v = = 11}^{V V} {C C}_{hv hv} {I I}_{xy xy} = = {Σ Σ}_{h h = = 11}^{H h} {T T}_{ij ij,, h h}$

上式为块矩阵转换的公式，其中I_xy是对应位置的像素值，C_hv是相应的核系数；每一个T_ij都是由h×v次乘法操作和累加操作得到的，其中h与v分别表示图像的行数和列数；The above formula is the formula for block matrix conversion, where I _xy is the pixel value at the corresponding position, C _hv is the corresponding kernel coefficient; each T _ij is obtained by h×v times of multiplication and accumulation operations, where h and v represent the number of rows and columns of the image, respectively;

将上述输入信号输入前述算术模数转换器，假定所述ADC量化精度为N比特，那么第一周期结束后残余值为：Input the above-mentioned input signal into the aforementioned arithmetic analog-to-digital converter, assuming that the ADC quantization precision is N bits, then the residual value after the end of the first cycle is:

w₂[1]＝2(P[1]-d₁[1])-d₂[1] (1)w ₂ [1]=2(P[1]-d ₁ [1])-d ₂ [1] (1)

在余下的N-1个周期中，残余值为：In the remaining N-1 cycles, the residual value is:

w₂[k]＝2(P[k]+w₂[k-1]-d₁[k]-d₂[k]),k＝2,3...,N. (2)w ₂ [k]=2(P[k]+w ₂ [k-1]-d ₁ [k]-d ₂ [k]),k=2,3...,N. (2)

将这N个周期的残余值按照其二进制权重进行累加之后可以得到：After accumulating the residual values of these N cycles according to their binary weights, we can get:

${Σ Σ}_{k k = = 11}^{N N} 22^{- - ((k k + + 11))} (({22 d d}_{11} [[k k]] + + {d d}_{22} [[k k]])) = = {Σ Σ}_{k k = = 11}^{N N} 22^{- - k k} P P [[k k]] - - 22^{- - ((N N + + 11))} {w w}_{22} [[N N]] - - - - - - ((33))$

对上式进行变换后可以得到：After transforming the above formula, we can get:

${Σ Σ}_{k k = = 11}^{N N} 22^{- - ((k k + + 11))} (({22 d d}_{11} [[k k]] + + {d d}_{22} [[k k]])) = = {T T}_{ij ij,, h h} - - - - - - ((44))$

其中，w₂[k]表示第三加法器的第k次输出，d₁[k]、d₂[k]分别表示第一比较器、第二比较器的第k次输出；Wherein, w ₂ [k] represents the k-th output of the third adder, and d ₁ [k] and d ₂ [k] represent the k-th output of the first comparator and the second comparator respectively;

对T_ij,h进行累加之后得到一个变换后的核系数，从式(6)中可以看出要计算出T_ij,h还要对提取出的2比特数字码做乘二和相加的操作，这些操作需要在数字域中利用加法器完成。After accumulating T _ij,h, a transformed kernel coefficient is obtained. It can be seen from the formula (6) that to calculate T _ij,h, the extracted 2-bit digital code needs to be multiplied by two and added. , these operations need to be done in the digital domain using adders.

在数字域中利用加法器完成具体是，加法器首先将按照权重将d₁[k]、d₂[k]从模拟域转换到数字域进行存储，再进行加法操作。In the digital domain, an adder is used to complete the process. Specifically, the adder first converts d ₁ [k] and d ₂ [k] from the analog domain to the digital domain according to the weight for storage, and then performs the addition operation.

与已有技术相比，本发明的技术特点与效果：Compared with prior art, technical characteristic and effect of the present invention:

本发明提出了一种用于焦平面块矩阵变换的算术型ADC。通过对传统循环型ADC进行改进，添加了一个模拟比较器模块将块矩阵变换所需的累加操作融入到了ADC中，使其成为ADC量化过程中固有的一部分，大大提高了处理效率。避免了传统的焦平面图像压缩方法由于将所有操作都在模拟域中完成而造成了非线性和低精度，并且由于不需要大量的开关电容电路，可以使电路的面积和功耗显著降低。The present invention proposes an arithmetic type ADC for focal plane block matrix transformation. By improving the traditional circular ADC, an analog comparator module is added to integrate the accumulation operation required for block matrix transformation into the ADC, making it an inherent part of the ADC quantization process, which greatly improves the processing efficiency. It avoids the non-linearity and low precision caused by the traditional focal plane image compression method because all operations are completed in the analog domain, and because it does not require a large number of switched capacitor circuits, the area and power consumption of the circuit can be significantly reduced.

附图说明Description of drawings

图1是传统的循环型模数转换器的结构图和工作原理图；Fig. 1 is a structural diagram and a working principle diagram of a traditional circular analog-to-digital converter;

图2是本发明对其进行改进后的结构图和工作原理图；Fig. 2 is the improved structural diagram and working principle diagram of the present invention;

图3是要将d1和d2进行加法操作的加法器结构图。Fig. 3 is a structural diagram of an adder for adding d1 and d2.

图中2指对输入的电压值进行乘2操作；2 in the figure refers to multiplying the input voltage value by 2;

方框及其内部波形指的是将输入电压与参考电压进行比较以产生比较结果d1或者d2；The box and its internal waveform refer to comparing the input voltage with the reference voltage to generate the comparison result d1 or d2;

Z-1表示的是延时操作，用于将输出值延时一段时间后返回到输入端口；Z-1 represents a delay operation, which is used to delay the output value for a period of time and return it to the input port;

具体实施方式Detailed ways

本发明采取的技术方案是：The technical scheme that the present invention takes is:

${T T}_{ij ij} = = {Σ Σ}_{h h = = 11}^{H h} {Σ Σ}_{v v = = 11}^{V V} {C C}_{hv hv} {I I}_{xy xy} = = {Σ Σ}_{h h = = 11}^{H h} {T T}_{ij ij,, h h} - - - - - - ((55))$

上式为块矩阵转换的公式，其中Ixy是对应位置的像素值，Chv是相应的核系数。可以看出，每一个Tij都是由h×v次乘法操作和累加操作得到的，其中h与v分别表示图像的行数和列数。传统的焦平面块矩阵转换方法通常是首先利用开关电容电路完成像素值和相应核系数的乘法操作，接下来利用模拟累加器完成所需的两次累加操作。由于模拟电路固有的非线性，完成这样复杂的运算会对结果产生很大的影响。The above formula is a formula for block matrix conversion, where Ixy is the pixel value at the corresponding position, and Chv is the corresponding kernel coefficient. It can be seen that each Tij is obtained by h×v multiplication operations and accumulation operations, where h and v represent the number of rows and columns of the image, respectively. The traditional focal plane block matrix conversion method usually first uses the switched capacitor circuit to complete the multiplication operation of the pixel value and the corresponding kernel coefficient, and then uses the analog accumulator to complete the required two accumulation operations. Due to the inherent nonlinearity of analog circuits, completing such complex calculations can have a large impact on the results.

通过观察上述运算公式并结合传统循环型模数转换器(ADC)的特性，发明人发现可以通过对ADC结构的改进将累加操作融入到ADC中并成为其工作过程固有的一部分。By observing the above calculation formula and combining the characteristics of the traditional circular analog-to-digital converter (ADC), the inventors found that the accumulation operation can be integrated into the ADC and become an inherent part of its working process by improving the structure of the ADC.

传统循环型ADC的结构图和工作原理图参见图1，在第一个周期中对输入信号进行采样，在通过比较器提取出一位量化结果之后将差值反馈回来并进行下一循环的量化工作。由于每一周期待量化的值都比前一周期的值在二进制权重上少1，因此在循环开始前还要对差值进行乘2处理以保持输入值的幅值范围。为了在传统循环型ADC中融入累加功能，本发明提出了一种新型ADC结构，结构框图和原理图参见图2。采用这个结构的前提是输入信号必须是离散的，假设输入信号表达式为：See Figure 1 for the structure diagram and working principle diagram of the traditional cyclic ADC. The input signal is sampled in the first cycle, and the difference is fed back after the one-bit quantization result is extracted by the comparator and quantized in the next cycle. Work. Since the value expected to be quantized each week is 1 less in binary weight than the value of the previous period, the difference is also multiplied by 2 before the cycle starts to maintain the magnitude range of the input value. In order to integrate the accumulative function into the traditional cyclic ADC, the present invention proposes a new ADC structure, see FIG. 2 for the structural block diagram and schematic diagram. The premise of adopting this structure is that the input signal must be discrete, assuming that the input signal expression is:

P[k]＝Ic[k] (6)P[k]=Ic[k] (6)

P[k]即为原公式中的一个Tij,h。和传统循环型ADC不同的是，每一周期待量化的模拟量是由新输入的P[k]和上一周期的残余值相加而得到的，因此比较器输入电压的峰值会被翻倍，需要采用图2虚线框中的电路结构来维持峰值为正常值。这使得本算术ADC每一周期会得到2比特的数字码，分别是由两个比较器得到的，如图2所示。当所有的输入量都输送到ADC中以后，ADC将按照传统循环型ADC的工作原理进行工作直到产生了N比特的数字码。P[k] is a Tij,h in the original formula. Different from the traditional cyclic ADC, the analog quantity expected to be quantified every week is obtained by adding the newly input P[k] and the residual value of the previous period, so the peak value of the comparator input voltage will be doubled, The circuit structure in the dotted box in Figure 2 needs to be used to maintain the peak value at a normal value. This makes the arithmetic ADC obtain 2-bit digital codes in each cycle, which are respectively obtained by two comparators, as shown in Fig. 2 . When all the input quantities are sent to the ADC, the ADC will work according to the working principle of the traditional cyclic ADC until an N-bit digital code is generated.

具体工作原理如下，假定本ADC量化精度为N比特，那么第一周期结束后残余值为：The specific working principle is as follows, assuming that the quantization accuracy of this ADC is N bits, then the residual value after the first cycle is:

w₂[1]＝2(P[1]-d₁[1])-d₂[1] (7)w ₂ [1]=2(P[1]-d ₁ [1])-d ₂ [1] (7)

w₂[k]＝2(P[k]+w₂[k-1]-d₁[k]-d₂[k]),k＝2,3...,N. (8)w ₂ [k]=2(P[k]+w ₂ [k-1]-d ₁ [k]-d ₂ [k]),k=2,3...,N. (8)

${Σ Σ}_{k k = = 11}^{N N} 22^{- - ((k k + + 11))} (({22 d d}_{11} [[k k]] + + {d d}_{22} [[k k]])) = = {Σ Σ}_{k k = = 11}^{N N} 22^{- - k k} P P [[k k]] - - 22^{- - ((N N + + 11))} {w w}_{22} [[N N]] - - - - - - ((99))$

${Σ Σ}_{k k = = 11}^{N N} 22^{- - ((k k + + 11))} (({22 d d}_{11} [[k k]] + + {d d}_{22} [[k k]])) = = {T T}_{ij ij,, h h} - - - - - - ((1010))$

对Tij,h进行累加之后便可以得到一个变换后的核系数，从式(6)中可以看出要计算出Tij,h还要对提取出的2比特数字码做乘二和相加的操作，这些操作需要在数字域中利用加法器完成，如图3所示，该加法器首先将按照权重将d1和d2从模拟域转换到数字域进行存储，再进行加法操作。After accumulating Tij,h, a transformed kernel coefficient can be obtained. It can be seen from the formula (6) that to calculate Tij,h, the extracted 2-bit digital code needs to be multiplied by two and added. , these operations need to be completed in the digital domain using an adder, as shown in Figure 3, the adder will first convert d1 and d2 from the analog domain to the digital domain according to the weight for storage, and then perform the addition operation.

至此，在ADC量化的过程中完成了块矩阵变换所需的累加操作，而本结构只比传统循环型ADC多一个模拟比较器，但却提高了处理效率和转换精度。So far, the accumulation operation required for block matrix conversion is completed in the process of ADC quantization, and this structure only has one more analog comparator than the traditional cyclic ADC, but it improves the processing efficiency and conversion accuracy.

为更加详细的阐述本算术型ADC的工作原理，下面将给出具体数值的量化过程。In order to describe the working principle of the arithmetic ADC in more detail, the quantization process of specific values will be given below.

假设量化精度为8比特，比较器峰值为3.3V，参考电压为1.65V，输入的离散变量为2V和1V。想要得到的是两个输入量按其二进制权重累加的和，则理想的结果是2V×2-1+1V×2-2＝1.25V。Suppose the quantization precision is 8 bits, the peak value of the comparator is 3.3V, the reference voltage is 1.65V, and the discrete variables of the input are 2V and 1V. What you want to get is the sum of the two input quantities accumulated according to their binary weights, and the ideal result is 2V×2-1+1V×2-2=1.25V.

当用本ADC完成上述累加过程时，首先，第一周期到来时，2V输送到ADC中，得到2比特的数字码为：1,0，残余量为0.7V。第二周期到来后，残余量0.7V和第二个输入变量1V相加后得到的输入量1.7V会被输送到ADC中，产生的2比特数字码为：1,0，残余量为0.1V。至此，所有输入信号的采样完成，接下来将按照传统循环型ADC的工作原理对0.1V的残余量进行量化直至得到8个2比特的数字码。因此8组数字码分别为：1,0；1,0；0,0；0,0；0,0；0,0；0,1；0,1。因此按照式(6)可以计算出量化后的值转换成十进制约为1.255，和理想结果相仿。When using this ADC to complete the above accumulation process, first, when the first cycle comes, 2V is sent to the ADC, and the 2-bit digital code is obtained: 1,0, and the residual value is 0.7V. After the second cycle arrives, the input value 1.7V obtained by adding the residual value 0.7V and the second input variable 1V will be sent to the ADC, and the generated 2-bit digital code is: 1,0, and the residual value is 0.1V . At this point, the sampling of all input signals is completed, and then the 0.1V residual will be quantized according to the working principle of the traditional cyclic ADC until eight 2-bit digital codes are obtained. Therefore, the 8 groups of digital codes are: 1,0; 1,0; 0,0; 0,0; 0,0; 0,0; 0,1; 0,1. Therefore, according to formula (6), it can be calculated that the quantized value converted into decimal is about 1.255, which is similar to the ideal result.

因此本算术型ADC可以成功将累加操作融合到ADC的量化过程中。Therefore, the arithmetic ADC can successfully integrate the accumulation operation into the quantization process of the ADC.

Claims

1. A focal plane block matrix conversion column parallel arithmetic analog-to-digital converter is characterized in that, comprising: the first adder, the second adder, the multiplier, the third adder connected successively; the output of the first adder It is also compared with the reference voltage by the first comparator, and the comparison result is output to the second adder; the output of the multiplier is also compared with the reference voltage by the second comparator, and the comparison result is output to the third adder; the output of the third adder Feedback to the first adder through the delayer.

2. The focal plane block matrix conversion column-parallel arithmetic analog-to-digital converter according to claim 1, wherein the multiplier is a multiplication-square multiplier.

3. A focal plane block matrix conversion column-parallel arithmetic analog-to-digital conversion method is characterized in that the discrete input signal P[k] is adopted, which is a T _ij,h in the following formula:

{Σ Σ}_{h h = = 11}^{H h} {Σ Σ}_{v v = = 11}^{V V} {C C}_{hv hv} {I I}_{xy xy} = = {Σ Σ}_{h h = = 11}^{H h} {T T}_{ij ij,, h h}

The above formula is the formula for block matrix conversion, where I _xy is the pixel value at the corresponding position, C _hv is the corresponding kernel coefficient; each T _ij is obtained by h×v times of multiplication and accumulation operations, where h and v represent the number of rows and columns of the image, respectively;

Input the above-mentioned input signal into the aforementioned arithmetic analog-to-digital converter, assuming that the ADC quantization precision is N bits, then the residual value after the end of the first cycle is:

w ₂ [1]=2(P[1]-d ₁ [1])-d ₂ [1] (1)

In the remaining N-1 cycles, the residual value is:

w ₂ [k]=2(P[k]+w ₂ [k-1]-d ₁ [k]-d ₂ [k]),k=2,3...,N. (2)

After accumulating the residual values of these N cycles according to their binary weights, we can get:

{Σ Σ}_{k k = = 11}^{N N} 22^{- - ((k k + + 11))} (({22 d d}_{11} [[k k]] + + {d d}_{22} [[k k]])) = = {Σ Σ}_{k k = = 11}^{N N} 22^{- - k k} P P [[k k]] - - 22^{- - ((N N + + 11))} {w w}_{22} [[N N]] - - - - - - ((33))

After transforming the above formula, we can get:

{Σ Σ}_{k k = = 11}^{N N} 22^{- - ((k k + + 11))} (({22 d d}_{11} [[k k]] + + {d d}_{22} [[k k]])) = = {T T}_{ij ij,, h h} - - - - - - ((44))

Wherein, w ₂ [k] represents the k-th output of the third adder, and d ₁ [k] and d ₂ [k] represent the k-th output of the first comparator and the second comparator respectively;

After accumulating T _ij,h, a transformed kernel coefficient is obtained. It can be seen from the formula (6) that to calculate T _ij,h, the extracted 2-bit digital code needs to be multiplied by two and added. , these operations need to be done in the digital domain using adders.

4. focal plane block matrix conversion column parallel arithmetic analog-to-digital conversion method as claimed in claim 3, it is characterized in that, utilize adder to finish specifically in digital domain, adder at first will d ₁ [k], d ₂ [k] is converted from the analog domain to the digital domain for storage, and then the addition operation is performed.