CN104022033B - A kind of processing method of TI-IGBT chip back structure - Google Patents
A kind of processing method of TI-IGBT chip back structure Download PDFInfo
- Publication number
- CN104022033B CN104022033B CN201410274412.4A CN201410274412A CN104022033B CN 104022033 B CN104022033 B CN 104022033B CN 201410274412 A CN201410274412 A CN 201410274412A CN 104022033 B CN104022033 B CN 104022033B
- Authority
- CN
- China
- Prior art keywords
- disk
- back side
- igbt
- graphic element
- mask plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 230000003213 activating effect Effects 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 238000001465 metallisation Methods 0.000 claims abstract description 5
- 238000010586 diagram Methods 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000004377 microelectronic Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012067 mathematical method Methods 0.000 description 2
- 108010022579 ATP dependent 26S protease Proteins 0.000 description 1
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The processing method that the invention discloses a kind of TI-IGBT chip back structure, belongs to microelectronics technology.The method includes: after disk Facad structure processes, in the back side implanting p-type doping of described disk；Back side resist coating to described disk, then divides zones of different according to backside mask plate to the back light photoresist of disk and is exposed successively.Mask plate figure contains multiple graphic element, the arrangement of graphic element translational symmetry ground；Control the relative position between exposure area, make the exposure figure of whole disk based on graphic element the most also translational symmetry；After development, n-type doping is injected at the back side to described disk, then back light photoresist is removed, and final annealing carries out back face metalization after activating doping.The present invention can make the TI-IGBT product of different voltage and current class share same backside mask plate, saves substantial amounts of plate-making cost, improves productivity ratio.
Description
Technical field
The present invention relates to microelectronics technology, expose particularly to a kind of TI-IGBT chip back structure
The method of light.
Background technology
TI-IGBT:Triple mode Integrate-Insulated Gate Bipolar
Transistor, three Mode integrating insulated gate bipolar transistors.It is by IGBT, VDMOS, FRD
The 26S Proteasome Structure and Function of three kinds of devices combines cleverly.Device is similar to IGBT device when forward conduction
Part, has less conduction voltage drop.In turn off process, similar VDMOS device, has and closes faster
Disconnected speed.When device bears backward voltage, the similar FRD device of device work.TI-IGBT device
Can be with conduct current in either direction, when driving inductive load without inverse parallel afterflow FRD.Relative to tradition
IGBT device, TI-IGBT mono-aspect improves the overall performance of device, on the other hand significantly reduces
The manufacturing cost of device.
The back side of VDMOS device is N-type semiconductor, belongs to unipolar device, and switching speed is fast, but
Along with pressure increase, the conduction voltage drop of device increases rapidly.The back side of IGBT device is that p-type is partly led
Body, when conducting, p-type colelctor electrode can inject substantial amounts of hole, thus conductivity modulation effect occurs, fall
Low conduction voltage drop.But then owing to being filled with a large amount of few son, need surplus when device turns off
Few son be combined, this cause device turn off slower.TI-IGBT is by VDMOS structure, IGBT knot
The structure that structure and FRD structure blend, the existing low conduction voltage drop of its performance, there is again fast shutoff speed
Degree, device also has against leading function simultaneously.
As it is shown in figure 1, first process front technique and the N+ cushion of TI-IGBT in prior art,
Then the back side Zone Full implanting p-type doping at disk forms P+ collecting zone (seeing Fig. 2), then
Expose with backside mask plate after the resist coating of the disk back side, by development, needs are injected n-type doping
Overlying regions photoresist remove after inject n-type doping.The dosage of n-type doping is sufficiently large, with
Ensure all to compensate p type impurity.N-type doping distribution junction depth is enough deep, to ensure N+ collecting zone
(seeing Fig. 3) is connected with N+ cushion.
Require when prior art makes mask plate that back side domain mates with front domain size, for different
Front domain needs the corresponding backside mask plate of special making.During disk back-exposure, backside mask plate needs
Generally to use stepper by the most individual core with the figure alignment of each chip in disk front
Sheet or minority chip back are exposed.Its shortcoming is: the first, for different voltage x current grades
TI-IGBT product, need to make corresponding backside mask plate, add plate-making cost；The second,
Backside mask plate and front description alignment difficulty, need advanced equipment, and technology difficulty is bigger；3rd,
The back side being every time only a chip or minority chip is exposed, inefficient.
Summary of the invention
The technical problem to be solved is to provide the processing of a kind of TI-IGBT chip back structure
Method, solves in prior art the TI-IGBT chip to different voltages or current class and is exposed
Need technical problem that is individually designed and that make corresponding backside mask plate.
For solving above-mentioned technical problem, the invention provides adding of a kind of TI-IGBT chip back structure
Work method, specifically includes following steps:
After disk Facad structure processes, in the back side implanting p-type doping of described disk；
Back side resist coating to described disk, then according to the backside mask plate back side to described disk
Divide zones of different, be exposed successively, the mask plate figure formed according to described backside mask plate,
Eventually form back side figure；
Wherein, described mask plate figure contains multiple graphic element, and the plurality of graphic element translates
It is symmetrically arranged, controls the relative position between exposure area successively, make the exposure diagram of whole described disk
Shape is based on graphic element the most also translational symmetry；After development, the back side injection N-type to described disk is mixed
Miscellaneous, then described photoresist to be removed, final annealing carries out back face metalization after activating doping.
Further, the orientation of the graphic element at multiple described disk back sides and described disk front
The orientation of chip parallel.
Further, the orientation of the graphic element at multiple described disk back sides and described disk front
Chip orientation between form a deflection angle.
Further, the chip size in described disk front is the graphic element size at the described disk back side
Integral multiple.
Further, described TI-IGBT structure is N-channel TI-IGBT or P-channel TI-IGBT.
The processing method of the TI-IGBT chip back structure that the present invention provides, by accurately controlling the back side
The relative position of different exposure areas, makes back side graphic element continuous and flat in the range of whole silicon chip
Move symmetry.Can be improved the concordance of chip parameter on this basis by two ways, one is to control
The orientation of back side figure, two is the integral multiple that size is back side figure unit size making chip.
So, without the figure alignment with disk front chip during the graph exposure of the back side, only need to accurately control the back of the body
The relative position of difference exposure area, face.Can use same for different voltages, the chip of current class
Block backside mask plate is processed, and also can share the processing of backside mask plate even for various sizes of disk,
Save substantial amounts of plate-making cost.Method described in this patent is performance and the parameter suitably to reduce product
Concordance is the production cost of cost, as much as possible compressed products, improves productivity ratio.
Accompanying drawing explanation
The front technique of the processing TI-IGBT that Fig. 1 provides for prior art and N+ cushion schematic diagram；
The formation P+ collector region structure schematic diagram that Fig. 2 provides for prior art；
Fig. 3 for prior art provide by N+ collecting zone and N+ cushion connectivity structure schematic diagram；
The processing method flow chart of the TI-IGBT chip back structure that Fig. 4 provides for the embodiment of the present invention；
Fig. 5 has exposed whole disk for the disk that the embodiment of the present invention one provides by subregion and has exposed
Schematic diagram；
The TI-IGBT disk structure pattern arrangement direction that Fig. 6 provides for the embodiment of the present invention one with
The schematic diagram that arrangements of chips direction is parallel；
The N+ that on the TI-IGBT disk that Fig. 7 provides for the embodiment of the present invention one, different chip backs comprise
Collecting zone position and quantitative comparison's schematic diagram；
TI-IGBT disk back side figure orientation that Fig. 8 provides for the embodiment of the present invention two and disk
Arrangements of chips direction, front is the schematic diagram at particular offset angle；
The N+ that on the TI-IGBT disk that Fig. 9 provides for the embodiment of the present invention two, different chip backs comprise
Collecting zone position and quantitative comparison's schematic diagram；
TI-IGBT disk back side figure unit size that Figure 10 provides for the embodiment of the present invention three and disk
Front chip size relation schematic diagram.
Detailed description of the invention
See Fig. 4, the processing side of a kind of TI-IGBT chip back structure that the embodiment of the present invention provides
Method, comprises the steps:
Step 101: after disk Facad structure processes, in the back side implanting p-type doping of disk；
Step 102: the back side resist coating to disk, then according to the backside mask plate back of the body to disk
Face divides zones of different, is exposed successively, the mask plate figure formed according to backside mask plate,
Rear formation back side figure；
Wherein, mask plate figure contains multiple graphic element, multiple graphic element translational symmetry ground row
Row, control the relative position between exposure area successively, make the exposure figure of whole disk based on figure list
Unit's the most also translational symmetry；
Step 103: the disk after exposure is developed；
Step 104: n-type doping is injected at the back side of disk；
Step 105: the back light photoresist of disk is removed；
Step 106: disk is entered annealing, carries out back face metalization after activating doping.
Embodiment 1:
In the embodiment of the present invention, as a example by N-channel TI-IGBT, but it is also applied for P-channel
TI-IGBT.Having only to mutually replace P/N is the counter structure of P-channel TI-IGBT.
After the front technique of chip completes, after disk back side implanting p-type is adulterated, the disk back side is coated with light
Photoresist.Then divide zones of different according to backside mask plate to be exposed successively, form back side figure；
Mask plate figure contains multiple graphic element, the arrangement of graphic element translational symmetry ground；Accurately control
Relative position between exposure area processed, makes the exposure figure of whole disk continuously and put down based on graphic element
Move symmetry；After development, n-type doping is injected at the back side to described disk, then back light photoresist is removed,
Final annealing carries out back face metalization after activating doping.
In Figure 5, the little square frame of solid line on disk is a single chip, and dashed rectangle is the back side
The scope of exposure every time.Backside mask can be disposably numerous chip back exposure structures, back view
Shape without with front description alignment, only need to accurately control the relative position in different back-exposure region, with
Ensure back side graphic element continuous and translational symmetry in whole disk.Due to front description and back view
Shape not alignment, so the position in the N+ current collection region, the back side of each chip and quantity are incomplete same, as
Shown in Fig. 6.Parameter for TI-IGBT mainly has with the total quantity of N+ collecting zone of chip back
Close, little with these N+ collecting zone location relations.For the back side domain shown in Fig. 6, only
Ensure that the N+ collecting zone number of each chip back is more or less the same and ensure that the parameter one of chip
Cause property.If the chip on whole disk at most can comprise Nmax N+ collecting zone region, minimum bag
Containing Nmin N+ collecting zone region, then on (Nmax-Nmin)/(Nmax+Nmin)/the least whole disk
Chip parameter concordance the best.For different voltage, the TI-IGBT of current class, chip
Although size is different, but still processing can be exposed with same mask plate.
Embodiment 2:
Further, since back side figure and front description do not have alignment, frequently can lead to (Nmax-Nmin)/
(Nmax+Nmin) relatively big, that chip A as shown in Figure 7 and the chip B back side are comprised N+ collecting zone
Quantity difference is relatively big, and the parameter consistency for TI-IGBT is mainly relevant with the quantity of border circular areas.
If the N+ doped region quantitative difference that different chips comprise is big (as the chip A back side comprises 16 especially
N+ doped region, and the chip B back side only comprises 9 N+ doped regions), inevitably result in the parameter of chip
Concordance is poor.
See Fig. 8, in order to reduce (Nmax-Nmin)/(Nmax+Nmin) as far as possible, can be by described circle
Formed between the orientation of the orientation of the graphic element at the sheet back side and the chip in described disk front
One suitable deflection angle.Calculating shows that (Nmax-Nmin)/(Nmax+Nmin) can be along with offset angle
Change and change, if offset angle is chosen properly (Nmax-Nmin)/(Nmax+Nmin) and can be dropped
To the relatively low level of ratio, as shown in Figure 9.The size of offset angle needs according to disk front chip
The size of size and disk back side graphic element determines, specifically can pass through mathematical method or soft by mathematics
Part calculates and tries to achieve optimal value.
Mathematically parameter consistency and α have the biggest relation, as long as α selects properly, and the ginseng of chip
Number concordance can reach preferable level.Optimum angle of deflection be a front side of silicon wafer chip length and
Wide and silicon chip back side figure cellular length and wide function, different situation optimal corner is different, but can lead to
Cross mathematical method to try to achieve.
Embodiment 3:
See Figure 10, can be when design by the size of chip in order to improve the concordance of parameter further
Mate with the cellular size of back side figure.Different voltage, the chips of current class under normal circumstances
Share same backside mask plate, say, that the graphic element size of disk backside mask plate determines that
, so, the chip size in disk front is set as the integral multiple of the cellular size of graphic element.For
It is easy to explanation, it is assumed that the graphic element at the disk back side is rectangle, and a size of a × b.Such as fruit chip
Be designed and sized to ma × nb (m, n are natural number), then although back side figure not with front description set
Standard, but the N+ collecting zone quantity that each chip back comprises is identical, and different chip back N+
The position of collection district electricity is identical, thus in farthest improve whole disk between different chips
The concordance of parameter.
The processing method of the TI-IGBT chip back structure that the embodiment of the present invention provides, can reduce chip
Manufacturing cost, make product more competitive.In terms of three, specifically reduce cost, as follows:
(1) can use same backside mask plate for different voltages, the chip of current class, the most right
Also can share same backside mask plate in various sizes of disk, save substantial amounts of plate-making cost.
(2) avoid using advanced process equipment.Owing to without the front description alignment with disk, using
Common litho machine processing back process.If needing to use advanced processing to set by traditional method
Standby, on the one hand advanced equipment is costly, relatively costly during the most advanced equipment machine.
(3) improve working (machining) efficiency.Owing to can be tens of back side figure exposures to up to a hundred chips simultaneously
Light, film speed is multiplied, and reduces time lithographic equipment is taken machine, improves productivity ratio.
It should be noted last that, above detailed description of the invention is only in order to illustrate technical scheme
And unrestricted, although the present invention being described in detail with reference to example, the ordinary skill people of this area
Member should be appreciated that and can modify technical scheme or equivalent, without deviating from
The spirit and scope of technical solution of the present invention, it all should be contained in the middle of scope of the presently claimed invention.
Claims (4)
1. the processing method of a TI-IGBT chip back structure, it is characterised in that specifically include
Following steps:
After disk Facad structure processes, in the back side implanting p-type doping of described disk；
Back side resist coating to described disk, then according to the backside mask plate back side to described disk
Divide zones of different, be exposed successively, the mask plate figure formed according to described backside mask plate,
Eventually form back side figure；
Wherein, described mask plate figure contains multiple graphic element, and the plurality of graphic element translates
It is symmetrically arranged, controls the relative position between exposure area successively, make the exposure diagram of whole described disk
Shape is based on graphic element the most also translational symmetry；
After development, n-type doping is injected at the back side to described disk, is then removed by described photoresist,
Annealing carries out back face metalization after activating doping eventually.
Processing method the most according to claim 1, it is characterised in that multiple described disks are carried on the back
The orientation of the graphic element in face is parallel with the orientation of the chip in described disk front.
Processing method the most according to claim 1, it is characterised in that described disk front
Chip size is the integral multiple of the graphic element size at the described disk back side.
4. according to the arbitrary described processing method of claim 1-3, it is characterised in that described
TI-IGBT structure is N-channel TI-IGBT or P-channel TI-IGBT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410274412.4A CN104022033B (en) | 2014-06-18 | 2014-06-18 | A kind of processing method of TI-IGBT chip back structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410274412.4A CN104022033B (en) | 2014-06-18 | 2014-06-18 | A kind of processing method of TI-IGBT chip back structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104022033A CN104022033A (en) | 2014-09-03 |
| CN104022033B true CN104022033B (en) | 2016-08-24 |
Family
ID=51438730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410274412.4A Active CN104022033B (en) | 2014-06-18 | 2014-06-18 | A kind of processing method of TI-IGBT chip back structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104022033B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105225996B (en) * | 2015-09-18 | 2017-12-12 | 江苏中科君芯科技有限公司 | IGBT device back process with diode-built-in |
| CN105280538B (en) * | 2015-09-18 | 2018-01-30 | 江苏中科君芯科技有限公司 | It can realize that the back side becomes more meticulous the IGBT back sides preparation method of photoetching |
| JP6789121B2 (en) * | 2015-11-30 | 2020-11-25 | 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ | Die and package |
| CN107315320B (en) * | 2017-05-10 | 2019-01-22 | 株洲中车时代电气股份有限公司 | Power semiconductor chip, the reticle and its exposure method of the chip |
| CN115132576A (en) * | 2022-07-06 | 2022-09-30 | 珠海格力电器股份有限公司 | Mask structure for RC-IGBT ion implantation and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393928A (en) * | 2008-10-31 | 2009-03-25 | 电子科技大学 | Tunnel IGBT with anode in short circuit |
| CN103839988A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Structure of EMPT-TI-IGBT device and preparation method thereof |
| CN103839992A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Power device-TI-IGBT structure and preparation method thereof |
| CN103855155A (en) * | 2012-12-06 | 2014-06-11 | 江苏物联网研究发展中心 | Three-mode integrated insulated gate bipolar transistor and forming method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4659534B2 (en) * | 2005-07-04 | 2011-03-30 | 三菱電機株式会社 | Semiconductor device |
| JP2007103770A (en) * | 2005-10-06 | 2007-04-19 | Sanken Electric Co Ltd | Insulated gate bipolar transistor |
| JP2009246198A (en) * | 2008-03-31 | 2009-10-22 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device, and semiconductor device |
| US9461116B2 (en) * | 2012-12-06 | 2016-10-04 | Institute of Microelectronics, Chinese Academy of Sciences | Method of formation of a TI-IGBT |
-
2014
- 2014-06-18 CN CN201410274412.4A patent/CN104022033B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393928A (en) * | 2008-10-31 | 2009-03-25 | 电子科技大学 | Tunnel IGBT with anode in short circuit |
| CN103839988A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Structure of EMPT-TI-IGBT device and preparation method thereof |
| CN103839992A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Power device-TI-IGBT structure and preparation method thereof |
| CN103855155A (en) * | 2012-12-06 | 2014-06-11 | 江苏物联网研究发展中心 | Three-mode integrated insulated gate bipolar transistor and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104022033A (en) | 2014-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104022033B (en) | A kind of processing method of TI-IGBT chip back structure | |
| CN102569067B (en) | Method for manufacturing planar high-voltage ultrafast soft recovery diode | |
| US10600903B2 (en) | Semiconductor device including a power transistor device and bypass diode | |
| DE102014119278A1 (en) | Semiconductor devices | |
| CN109830532A (en) | Superjunction IGBT device and its manufacturing method | |
| DE102014110681A1 (en) | REVERSE LEADING IGBT | |
| WO2015042148A1 (en) | Vertical field-effect transistor device having at least two bypass schottky diodes | |
| CN107611167B (en) | Super-junction semiconductor device with multiple concentration centers and manufacturing method thereof | |
| CN106409910A (en) | Semiconductor Device with a Laterally Varying Doping Profile, and Method for Manufacturing Thereof | |
| CN103560086B (en) | The preparation method of the super-junction semiconductor device of avalanche capacity can be improved | |
| CN107482060A (en) | Superjunction devices and its manufacture method | |
| US11705510B2 (en) | Gate-turn-off thyristor and manufacturing method thereof | |
| CN107768443B (en) | Super junction device and manufacturing method thereof | |
| CN106803498A (en) | A kind of inverse preparation method for leading IGBT device | |
| CN110137081A (en) | The manufacturing method of silicon trench and the manufacturing method of super-junction structure | |
| CN106783611A (en) | A kind of trench gate IGBT with the embedded diode of grid and preparation method thereof | |
| CN203481241U (en) | High-low-junction-based majority-carrier conductivity-modulated power MOSFET device | |
| CN109256423B (en) | Oxidation tank alternate isolation type insulated gate bipolar transistor and preparation method thereof | |
| CN107994074A (en) | Groove grid super node device and its manufacture method | |
| CN103378141A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN106783940B (en) | Power semiconductor device with edge termination structure of gradual change concentration | |
| CN101877361B (en) | Resonant tunneling device of novel planer device structure | |
| CN107359125A (en) | A kind of method and device for optimizing body diode reverse recovery characteristics | |
| CN103855204B (en) | Reverse conducting IGBT collector structure and preparation method thereof | |
| CN106816463A (en) | A kind of terminal structure, semiconductor devices and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |