CN104021057A - CPU (Central Processing Unit) startup fault positioning system and positioning method thereof - Google Patents
CPU (Central Processing Unit) startup fault positioning system and positioning method thereof Download PDFInfo
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Abstract
The invention discloses a CPU (Central Processing Unit) startup fault positioning system and a positioning method of the CPU startup fault positioning system. The positioning system comprises a CPU, and a flash memory, an RAM (Random Access Memory) and a monitoring unit which are connected with the CPU, wherein a flash memory signal monitoring end of the monitoring unit is respectively connected with the input end of the flash memory and a flash memory chip selection signal output end of the CPU; an RAM signal monitoring end of the monitoring unit is respectively connected with an RAM input end and an RAM chip selection signal output end of the CPU; the monitoring unit further comprises a first state output indication end and a second state output indication end which are used for respectively displaying a fault condition of the fault positioning system. In a CPU startup process, a FLASH chip selection signal is captured in the CPU startup process and an RAM chip selection signal is captured; the monitoring unit is used for judging whether the CPU can be normally started up or not and the reason of a CPU startup fault according to the captured FLASH chip selection signal and RAM chip selection signal. The positioning system can be used for rapidly and accurately positioning a hardware fault in the CPU startup process and avoids signal measurement and judgment by using various instruments and meters; the positioning system is applicable to startup fault positioning of electronic equipment in large-batch production.
Description
Technical field
The present invention relates to computer detection system and detection method, be specifically related to a kind of CPU and start fault location system and localization method thereof.
Background technology
Along with the development of IC technology and electronic equipment, the volume of electronic equipment core CPU is constantly reducing, and the ROM that CPU is built-in and ram space no longer meet the application demand of complication system, need to have larger storage space for storing data and code.Therefore, external flash memory (FLASH Memory is called for short FLASH) and RAM become the main dilatation way of current CPU.
In existing cpu system, CPU is outer FLASH and the RAM storer of hanging with conventionally, FLASH is used for storing the files such as start-up code, system image, RAM is the data access at operational process for CPU, and CPU may be because the reasons such as failure welding, chip damage, code error cause CPU normally to start after powering on.When code is comparatively ripe, it is cannot normally have access to FLASH or RAM causes due to CPU that CPU cannot start majority.
Conventional Fault Locating Method adopts the preferential exclusive method of FLASH fault conventionally, first checks whether place FLASH chip rosin joint or scolding tin short circuit occur, and conventionally adopts electric soldering iron to be welded with mode and solve when there is rosin joint or scolding tin short circuit.If CPU cannot start, need to change former FLASH chip, welding has been mounted with the new FLASH chip of start-up code again.If CPU still cannot start, will get rid of FLASH fault, again adopt above-mentioned to be welded with or to change that RAM method solves whether is that RAM fault causes CPU to start.
The preferential exclusive method of existing fault, although can solve the starting problem of CPU, efficiency is very low, while producing in enormous quantities, is not suitable for the quick location of failure chip.In addition to the secondary welding of FLASH, also may damage trouble-free FLASH chip originally, if secondary welding is still unsuccessful, may being positioned on RAM chip bug.
Summary of the invention
The object of the present invention is to provide a kind of CPU to start fault location system and localization method thereof, monitoring means, FLASH and RAM are connected with CPU respectively, because FLASH is connected with CPU respectively with RAM, in CPU start-up course, code in FLASH can be moved to RAM and be carried out by CPU, be that CPU can first capture FLASH chip selection signal in start-up course, after catch RAM chip selection signal; Monitoring means basis is caught FLASH chip selection signal, RAM chip selection signal judges whether CPU can normally start and the concrete reason of CPU startup fault.
In order to achieve the above object, the present invention is achieved through the following technical solutions:
CPU starts a fault location system, is characterized in, this fault location system comprises: monitoring means, and the CPU, flash memory and the RAM that are connected with above-mentioned detecting unit.
The flash memory signal of above-mentioned monitoring means is monitored end and is connected with the flash memory chip selection signal output terminal of the input end of above-mentioned flash memory and above-mentioned CPU respectively.
The RAM signal of above-mentioned monitoring means is monitored end and is connected with the RAM chip selection signal output terminal of the input end (31) of above-mentioned RAM and above-mentioned CPU respectively.
Above-mentioned monitoring means also comprises the first State-output indication end and the second State-output indication end, shows respectively the failure condition of this fault location system.
A localization method that starts fault location system for above-mentioned CPU, is characterized in, this localization method comprises following steps:
Step S1, above-mentioned monitoring means is set respectively CPU section detection time T1, flash memory section detection time T2, delay time section T3 and RAM section detection time T4.
Step S2, after above-mentioned CPU powers on, the flash memory signal of this monitoring means is monitored end and by above-mentioned flash memory chip selection signal output terminal, catch the signal that this CPU sheet selects flash memory in above-mentioned CPU section detection time T1.
Step S3, the RAM signal of above-mentioned monitoring means is monitored end and by above-mentioned RAM chip selection signal output terminal, catch the signal that this CPU sheet selects RAM in above-mentioned flash memory section detection time T2.
Step S4, after the above-mentioned delay time section T3 of above-mentioned monitoring means trigger, this flash memory signal is monitored end at the above-mentioned above-mentioned flash memory chip selection signal of RAM section detection time T4 IT, and above-mentioned monitoring means records number Q1 that the pulse of flash memory chip selection signal occurs, occur for the first time the moment t1 of this flash memory chip selection signal and occur for the second time the moment t2 of this flash memory chip selection signal.
Step S5, whether the number Q1 that the flash memory chip selection signal pulse of above-mentioned monitoring means judgement record occurs is less than or equal to 1; When number Q1≤1 appears in the flash memory chip selection signal pulse of above-mentioned monitoring means record, above-mentioned monitoring means shows that CPU normally starts; When there is number Q1>1 in the flash memory chip selection signal pulse of above-mentioned monitoring means record, execution step S6.
Step S6, in above-mentioned RAM section detection time T4, above-mentioned monitoring means is according to formula: Q1< T4/ (t2-t1) <Q1+1 calculates and judges that whether above-mentioned RAM is abnormal.
The above-mentioned localization method for above-mentioned CPU startup fault location system, is characterized in, comprises following steps in above-mentioned step S2:
Step S2.1, the flash memory signal of above-mentioned monitoring means is monitored and is held while not capturing this flash memory chip selection signal in above-mentioned CPU section detection time T1, and this monitoring means shows that by the first above-mentioned State-output indication end and the second State-output indication end CPU is abnormal.
Step S2.2, the flash memory signal of above-mentioned monitoring means is monitored and is held while capturing this flash memory chip selection signal in above-mentioned CPU section detection time T1, execution step S3.
The above-mentioned localization method for above-mentioned CPU startup fault location system, is characterized in, comprises following steps in above-mentioned step S3:
Step S3.1, the RAM signal of above-mentioned monitoring means is monitored and is held while not capturing this RAM chip selection signal in above-mentioned flash memory section detection time T2, and above-mentioned monitoring means shows that by the first above-mentioned State-output indication end and the second State-output indication end flash memory is abnormal.
Step S3.2, the RAM signal of above-mentioned monitoring means is monitored and is held while capturing this RAM chip selection signal in above-mentioned flash memory section detection time T2, execution step S4.
The above-mentioned localization method for above-mentioned CPU startup fault location system, is characterized in, above-mentioned step S6 comprises following steps:
Step 6.1, above-mentioned monitoring means judgement is when meeting Q1< T4/ (t2-t1) <Q1+1 requirement, and this monitoring means is abnormal by above-mentioned the first State-output indication end, the second State-output indication end display random access memory.
Step 6.2, when above-mentioned monitoring means judgement does not meet Q1< T4/ (t2-t1) <Q1+1 requirement, above-mentioned monitoring means shows that by the first above-mentioned State-output indication end and the second State-output indication end CPU normally starts.
The present invention compared with prior art has the following advantages:
1. CPU provided by the invention starts fault location system and localization method thereof, has abandoned the drawback of traditional preferential exclusive method of FLASH, can navigate to fast and accurately the hardware fault occurring in CPU start-up course.
2. by observation circuit, CPU is started to abnormal state and indicate, avoided using signal measurement and the judgement of various instrument and meters, be highly suitable for the startup localization of fault of electronic equipment in producing in enormous quantities.
Accompanying drawing explanation
Fig. 1 is the one-piece construction schematic diagram that a kind of CPU of the present invention starts fault location system.
Fig. 2 is the overall flow figure that a kind of CPU of the present invention starts Fault Locating Method.
Fig. 3 is the embodiment schematic diagram that a kind of CPU of the present invention starts fault location system.
Embodiment
Below in conjunction with accompanying drawing, by describing a preferably specific embodiment in detail, the present invention is further elaborated.
As shown in Figure 1, a kind of CPU starts fault location system, and this positioning system comprises: CPU 10, and connected flash memory 20, RAM 30 and monitoring means 40.The flash memory signal of monitoring means 40 is monitored end 41 and is connected with the input end 21 of flash memory 20, the flash memory chip selection signal output terminal 11 of CPU 10 respectively.The RAM signal of monitoring means 40 is monitored end 42 and is connected with the input end 31 of RAM 30, the RAM chip selection signal output terminal 12 of CPU 10 respectively.Monitoring means 40 also comprises the first State-output indication end 43, the second State-output indication end 44, shows respectively the failure condition of this fault location system.
As shown in Figure 3, in one embodiment of the present of invention, can select model is that the CPU of BCM53003 is as CPU 10, selecting model is that the CPLD of EPM570 is as monitoring means 40, selecting model is that the FLASH of S29GL01G is as flash memory 20, select the DDR2 SDRAM of two MT47H128M16 as RAM 30, also comprising model is the bus buffer 50 of 74HC244.
The flash memory chip selection signal output terminal 11 of BCM53003 is connected with the input end 21 of S29GL01G, and the RAM chip selection signal output terminal 12 of BCM53003 is connected with the input end 31 of two MT47H128M16 respectively.The IO1 end of EPM570 is monitored end 41 for flash memory signal, and this flash memory signal is monitored end 41 and is connected with the flash memory chip selection signal output terminal 11 of BCM53003; The RAM chip selection signal output terminal 12 that the IO2 end of EPM570 is monitored end 42, BCM53003 for RAM signal is connected with the IO2 end of EPM570 by bus buffer 50.The IO3 end of EPM570 is as the first State-output indication end 43, and the IO4 of EPM570 holds as the first State-output indication end 44; IO3 end, the IO4 end of EPM570 are connected with two light emitting diodes 60 by current-limiting resistance R1, R2 respectively.
In the present embodiment, by EPM570, the light emitting diode 60 of IO3 end is set when luminous, for FLASH abnormal; The light emitting diode 60 of IO4 end is set when luminous, RAM is abnormal; The light emitting diode 60 of IO3 end is set, the light emitting diode 60 of IO4 end when simultaneously luminous, CPU is abnormal.
In the present embodiment, by EPM570, other display modes can be set, be respectively used to show that CPU, RAM and FLASH are abnormal.
As shown in Figure 2, a kind of CPU starts Fault Locating Method, and this localization method comprises following steps:
Step S1, monitoring means 40 is set respectively CPU section detection time T1, flash memory section detection time T2, delay time section T3 and RAM section detection time T4.
In the present embodiment, can set CPU section detection time T1 is 200ms, and setting flash memory section detection time T2 is 100ms, and setting delay time section T3 is 800ms, and setting RAM section detection time T4 is 200ms.
Step S2, after CPU 10 powers on, the flash memory signal of this monitoring means 40 is monitored end 41 (in 200ms) in above-mentioned CPU section detection time T1 and is caught 10 signals that select flash memory of this CPU by flash memory output terminal 11.In this step S2, comprise following steps:
Step S2.1, when the flash memory signal monitoring end 41 of monitoring means 40 does not capture this flash memory chip selection signal in 200ms, this monitoring means 40 shows that by the first State-output indication end 43, the second State-output indication end 44 CPU are abnormal.
Step S2.2, the flash memory signal of monitoring means 40 is monitored while holding 41 to capture this flash memory chip selection signal in 200ms, execution step S3.
In the start-up course of CPU 10, first 10 of CPU need sheet to select FLASH 20, and carry out some system initialization codes in FLASH 20.When CPU 10 occurs when abnormal, CPU 10 can not select FLASH 20 by sheet, so monitoring means 40 can not be monitored end 41 at flash memory signal and capture this flash memory chip selection signal.
Step S3, the RAM signal of monitoring means 40 is monitored end 42 (in 100ms) in above-mentioned flash memory section detection time T2 and is caught by RAM chip selection signal output terminal 12 the RAM chip selection signal that this CPU 10 sends.In this step S3, comprise following steps:
Step S3.1, the RAM signal of monitoring means 40 is monitored while holding 42 not capture this RAM chip selection signal in 100ms, and this monitoring means 40 shows that by the first State-output indication end 43, the second State-output indication end 44 flash memories are abnormal;
Step S3.2, when the RAM signal of monitoring means 40 is monitored end 42 and is captured this RAM select signal in 100ms, execution step S4.
In the start-up course of CPU 10, the code of FLASH 20 can be moved to carrying out in RAM 30 by CPU 10, so CPU 10 can first be issued to FLASH chip selection signal, then just can be issued to RAM chip selection signal.Therefore, when FLASH 20 is abnormal, CPU 10 cannot move code to RAM 30 from FLASH 20, and CPU 10 can not carry out the code in RAM 30, is also that CPU 10 can not send RAM chip selection signal.
Step S4, monitoring means 40 starts at the above-mentioned delay time section T3(800ms of time delay) after, this flash memory signal is monitored end 41 (200ms in) in above-mentioned RAM section detection time T4 and is caught above-mentioned flash memory chip selection signal, this monitoring means 40 record flash memory chip selection signal pulse appearance number Q1, there is for the first time the moment t1 of this flash memory chip selection signal and occur for the second time the moment t2 of this flash memory chip selection signal.
Step S5, monitoring means 40 judgements are in 200ms, and whether the number Q1 that the flash memory chip selection signal pulse of record occurs is less than or equal to 1; When number Q1≤1 appears in the flash memory chip selection signal pulse of monitoring means 40 records, this monitoring means 40 shows that CPU normally starts; When there is number Q1>1 in the flash memory chip selection signal pulse of monitoring means 40 records, execution step S6.
In above-mentioned RAM section detection time T4, when CPU 10 normal startup, within this time period, CPU 10 has completed moving FLASH 20 codes, therefore generally, CPU 10 can not go rotating plate to select FLASH in time period T4 again, in time period T4, capture number Q1≤1 o'clock that the pulse of flash memory chip selection signal occurs, CPU 10 normally starts.
Step S6, in above-mentioned RAM section detection time T4, above-mentioned monitoring means 40 calculates and judges that whether RAM is abnormal according to formula Q1< T4/ (t2-t1) <Q1+1.This step S6 comprises following steps:
Step 6.1, when monitoring means 40 judgements meet Q1< T4/ (t2-t1) <Q1+1 requirement, this monitoring means 40 is abnormal by the first State-output indication end 43, the second State-output indication end 44 display random access memories;
Step 6.2, when monitoring means 40 judgements do not meet Q1< T4/ (t2-t1) <Q1+1 requirement,, this monitoring means 40 shows that by the first State-output indication end 43, the second State-output indication end 44 CPU normally starts.
In this stage, 10 sheets of CPU select RAM 30, and carry out the code of moving from RAM 30.When RAM 30 occurs when abnormal, the address space code of FLASH 20 correspondences cannot successfully be moved the designated space in RAM 30 always, therefore CPU 10 can rest on certain the address space code reading in FLASH 20 always, and CPU 10 can repeat this operational motion repeatedly.
In the present invention, effective chip selection signal that CPU 10 sends, the flash memory signal of monitoring means 40 is monitored end 41, RAM signal is monitored end 42 and caught respectively RAM 30 chip selection signals, FLASH 20 chip selection signals, thereby distinguish and judge the situation that RAM is abnormal, FLASH is abnormal, effectively, accurately judge whether CPU periphery has memory hardware to break down, and accurately navigate to abort situation.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Those skilled in the art, read after foregoing, for multiple modification of the present invention with to substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (5)
1. CPU starts a fault location system, it is characterized in that, this fault location system comprises: monitoring means (40), and the CPU(10 being connected with described detecting unit (40)), flash memory (20) and RAM(30);
The flash memory signal of described monitoring means (40) monitor end (41) respectively with the input end (21) of described flash memory (20) and described CPU(10) flash memory chip selection signal output terminal (11) be connected;
The RAM signal of described monitoring means (40) monitor end (42) respectively with described RAM(30) input end (31) and described CPU(10) RAM chip selection signal output terminal (12) be connected;
Described monitoring means (40) also comprises the first State-output indication end (43) and the second State-output indication end (44), shows respectively the failure condition of this fault location system.
2. for above-mentioned CPU, start a localization method for fault location system, it is characterized in that, this localization method comprises following steps:
Step S1, described monitoring means (40) is set respectively CPU section detection time T1, flash memory section detection time T2, delay time section T3 and RAM section detection time T4;
Step S2, described CPU(10) after powering on, the flash memory signal of this monitoring means (40) is monitored end (41) and by described flash memory chip selection signal output terminal (11), catch this CPU(10 in described CPU section detection time T1) sheet selects the signal of flash memory;
Step S3, the RAM signal of described monitoring means (40) is monitored end (42) and by described RAM chip selection signal output terminal (12), catch this CPU(10 in described flash memory section detection time T2) sheet selects the signal of RAM;
Step S4, after delay time section T3 described in described monitoring means (40) trigger, this flash memory signal is monitored end (41) at the flash memory chip selection signal described in described RAM section detection time T4 IT, and described monitoring means (40) records number Q1 that the pulse of flash memory chip selection signal occurs, occur for the first time the moment t1 of this flash memory chip selection signal and occur for the second time the moment t2 of this flash memory chip selection signal;
Step S5, whether the number Q1 that the flash memory chip selection signal pulse of described monitoring means (40) judgement record occurs is less than or equal to 1; When number Q1≤1 appears in the flash memory chip selection signal pulse of described monitoring means (40) record, described monitoring means (40) shows that CPU normally starts; When there is number Q1>1 in the flash memory chip selection signal pulse of described monitoring means (40) record, execution step S6;
Step S6, in described RAM section detection time T4, described monitoring means (40) is according to formula: whether Q1< T4/ (t2-t1) <Q1+1 calculates the described RAM of judgement abnormal.
3. the localization method that starts fault location system for above-mentioned CPU as claimed in claim 2, is characterized in that, comprises following steps in described step S2:
Step S2.1, the flash memory signal of described monitoring means (40) is monitored while holding (41) not capture this flash memory chip selection signal in described CPU section detection time T1, and this monitoring means (40) shows that by the first described State-output indication end (43) and the second State-output indication end (44) CPU is abnormal;
Step S2.2, the flash memory signal of described monitoring means (40) is monitored while holding (41) to capture this flash memory chip selection signal in described CPU section detection time T1, execution step S3.
4. the localization method that starts fault location system for above-mentioned CPU as claimed in claim 2, is characterized in that, comprises following steps in described step S3:
Step S3.1, the RAM signal of described monitoring means (40) is monitored while holding (42) not capture this RAM chip selection signal in described flash memory section detection time T2, and described monitoring means (40) shows that by the first described State-output indication end (43) and the second State-output indication end (44) flash memory is abnormal;
Step S3.2, the RAM signal of described monitoring means (40) is monitored while holding (42) to capture this RAM chip selection signal in described flash memory section detection time T2, execution step S4.
5. the localization method that starts fault location system for above-mentioned CPU as claimed in claim 2, is characterized in that, described step S6 comprises following steps:
Step 6.1, described monitoring means (40) judgement is when meeting Q1< T4/ (t2-t1) <Q1+1 requirement, and this monitoring means (40) is abnormal by described the first State-output indication end (43), the second State-output indication end (44) display random access memory;
Step 6.2, when described monitoring means (40) judgement does not meet Q1< T4/ (t2-t1) <Q1+1 requirement, described monitoring means (40) shows that by the first described State-output indication end (43) and the second State-output indication end (44) CPU normally starts.
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Effective date of abandoning: 20200407 |