CN108319529A - The method and system of the start-up course of monitoring CPU, CPLD - Google Patents
The method and system of the start-up course of monitoring CPU, CPLD Download PDFInfo
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- CN108319529A CN108319529A CN201810059587.1A CN201810059587A CN108319529A CN 108319529 A CN108319529 A CN 108319529A CN 201810059587 A CN201810059587 A CN 201810059587A CN 108319529 A CN108319529 A CN 108319529A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/327—Alarm or error message display
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Abstract
The present invention provides the method and system of the start-up course of monitoring CPU, CPLD, this method is applied to CPLD, including：When CPU starts start-up course, execute：S1：Judge that CPU is powered on and whether the process that resets is abnormal, if it is, the information that output CPU is powered on and the process that resets is abnormal, otherwise, execution S2；S2：Judge whether the process of CPU readings RCW is abnormal, if it is, output CPU reads the information that the process of RCW is abnormal, otherwise, executes S3；S3：Judge that CPU reads BootFlash and whether the process of control serial ports is abnormal, if it is, output CPU reads BootFlash and controls the information that the process of serial ports is abnormal.The present invention is capable of the start-up course of more easily monitoring CPU.
Description
Technical field
The present invention relates to field of computer technology, the more particularly to method and system of the start-up course of monitoring CPU, CPLD.
Background technology
In hardware debugging process, the start-up course of monitoring CPU is needed.
In the prior art, usually commissioning staff by equipment such as oscillograph and multimeters come the start-up course of monitoring CPU.
As can be seen from the above description, the monitoring scheme of the prior art is more inconvenient.
Invention content
An embodiment of the present invention provides the method and system of the start-up course of monitoring CPU, CPLD, can more easily supervise
Control the start-up course of CPU.
In a first aspect, an embodiment of the present invention provides a kind of method of the start-up course of monitoring CPU, it is applied to CPLD
(Complex Programmable Logic Device, Complex Programmable Logic Devices), including：
When CPU starts start-up course, execute：
S1：Judge whether the process that CPU is powered on and resetted is abnormal, if it is, the process hair that output CPU is powered on and resetted
Otherwise raw abnormal information executes S2；
S2：Judge whether the process of CPU readings RCW (Reset Configuration Word reset configuration) is abnormal, such as
Fruit is then to export CPU to read the information that the process of RCW is abnormal, and otherwise, executes S3；
S3：Judge that CPU reads BootFlash (starting flash memory) and whether the process of control serial ports is abnormal, if it is,
Output CPU reads BootFlash and controls the information that the process of serial ports is abnormal.
Further,
The S1, including：
A1：The nuclear power information for obtaining the nuclear power of CPU judges whether the nuclear power of the CPU is different according to the nuclear power information
Often, if so, otherwise the information of output nuclear power exception executes A2；
A2：The reset signal for obtaining CPU judges whether the reset of the CPU is abnormal according to the reset signal, if
It is that output resets abnormal information, otherwise, executes A3；
A3：The operating current for detecting CPU judges whether the operating current is abnormal, if it is, output services electric current is different
Otherwise normal information executes S2.
Further,
The S2, including：
B1：Judge whether the SRC for the RCW that CPU is read is correct, if it is, executing B2, otherwise, the SRC for exporting RCW is wrong
Information accidentally；
B2：Judge whether the format for the RCW that CPU is read is correct, if it is, otherwise executing S3 exports RCW's
The information of format error.
Further,
The S3, including：
C1：Judge that CPU reads whether BootFlash succeeds, if it is, executing C2, otherwise, output is read
The information of BootFlash failures；
C2：Judge whether serial ports work is normal, abnormal information if it is not, then output serial ports works.
Second aspect, an embodiment of the present invention provides a kind of CPLD, including：
First monitoring unit, the second monitoring unit and third monitoring unit；
First monitoring unit, for when CPU starts start-up course, executing：Judge the process that CPU is powered on and resetted
Whether abnormal, if it is, the information that output CPU is powered on and the process that resets is abnormal, otherwise, triggering described second monitors
Unit；
Second monitoring unit, whether the process for judging CPU readings RCW is abnormal, if it is, output CPU is read
Otherwise the information for taking the process of RCW to be abnormal triggers the third monitoring unit；
The third monitoring unit, whether the process for judging CPU reading BootFlash and control serial ports is abnormal,
If it is, output CPU reads BootFlash and controls the information that the process of serial ports is abnormal.
Further,
First monitoring unit, for executing：
A1：The nuclear power information for obtaining the nuclear power of CPU judges whether the nuclear power of the CPU is different according to the nuclear power information
Often, if so, otherwise the information of output nuclear power exception executes A2；
A2：The reset signal for obtaining CPU judges whether the reset of the CPU is abnormal according to the reset signal, if
It is that output resets abnormal information, otherwise, executes A3；
A3：The operating current for detecting CPU judges whether the operating current is abnormal, if it is, output services electric current is different
Otherwise normal information triggers second monitoring unit.
Further,
Second monitoring unit, for executing：
B1：Judge whether the SRC (source) for the RCW that CPU is read is correct, if it is, executing B2, otherwise, exports RCW
SRC mistakes information；
B2：Judge whether the format for the RCW that CPU is read is correct, if it is, the third monitoring unit is triggered,
Otherwise, the information of the format error of RCW is exported.
Further,
The third monitoring unit, for executing：
C1：Judge that CPU reads whether BootFlash succeeds, if it is, executing C2, otherwise, output is read
The information of BootFlash failures；
C2：Judge whether serial ports work is normal, abnormal information if it is not, then output serial ports works.
The third aspect, an embodiment of the present invention provides a kind of systems of the start-up course of monitoring CPU, including：
Any CPLD and display module in second aspect；
The CPLD is connected with the display module；
The CPLD includes：First monitoring unit, the second monitoring unit and third monitoring unit；
The display module, the process generation that the CPU for receiving the first monitoring unit output is powered on and resetted are different
Normal information, and show；The CPU for receiving the second monitoring unit output reads the information that the process of RCW is abnormal, and shows
Show；The CPU for receiving the third monitoring unit output reads BootFlash and controls the letter that the process of serial ports is abnormal
Breath, and show.
Further,
The display module includes：Charactron, display screen.
In embodiments of the present invention, the start-up course of CPU is divided into：CPU is powered on and the process that resets, CPU read RCW
Process and CPU read BootFlash and control the process of serial ports, are monitored automatically to these three processes by CPLD, nothing
It need to manually monitor, be capable of the start-up course of more easily monitoring CPU.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is a kind of flow chart of the method for the start-up course for monitoring CPU that one embodiment of the invention provides；
Fig. 2 is the flow chart of the method for the start-up course for another monitoring CPU that one embodiment of the invention provides；
Fig. 3 is a kind of schematic diagram for CPLD that one embodiment of the invention provides；
Fig. 4 is a kind of schematic diagram of the system of the start-up course for monitoring CPU that one embodiment of the invention provides.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments, based on the embodiments of the present invention, those of ordinary skill in the art
The every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As shown in Figure 1, an embodiment of the present invention provides a kind of method of the start-up course of monitoring CPU, it is applied to CPLD, it should
Method may comprise steps of：
When CPU starts start-up course, execute：
Step 101：Judge whether the process that CPU is powered on and resetted is abnormal, if so, thening follow the steps 102, otherwise, holds
Row step 103；
Step 102：The information that output CPU is powered on and the process that resets is abnormal；
Step 103：Judge whether the process of CPU readings RCW is abnormal, if so, thening follow the steps 104, otherwise, executes step
Rapid 105；
Step 104：Output CPU reads the information that the process of RCW is abnormal；
Step 105：Judge that CPU reads BootFlash and whether the process of control serial ports is abnormal, if it is, executing
Step 106；
Step 106：Output CPU reads BootFlash and controls the information that the process of serial ports is abnormal.
In embodiments of the present invention, the start-up course of CPU is divided into：CPU is powered on and the process that resets, CPU read RCW
Process and CPU read BootFlash and control the process of serial ports, are monitored automatically to these three processes by CPLD, nothing
It need to manually monitor, be capable of the start-up course of more easily monitoring CPU.
In embodiments of the present invention, which can be the CPLD being connected with the CPU being monitored.
In an embodiment of the present invention, whether the process for judging that CPU is powered on and resetted is abnormal, if it is, executing
Step 102：The information that output CPU is powered on and the process that resets is abnormal, otherwise, execution step 103, including：
A1：The nuclear power information for obtaining the nuclear power of CPU judges whether the nuclear power of the CPU is different according to the nuclear power information
Often, if so, otherwise the information of output nuclear power exception executes A2；
A2：The reset signal for obtaining CPU judges whether the reset of the CPU is abnormal according to the reset signal, if
It is that output resets abnormal information, otherwise, executes A3；
A3：The operating current for detecting CPU judges whether the operating current is abnormal, if it is, output services electric current is different
Otherwise normal information executes step 103.
In embodiments of the present invention, the nuclear power of CPU includes the I/O point signals etc. of the logic electric signal of CPU, CPU.CPU's
Reset signal can be the whether successful signal of reset of CPU outputs.When judging whether operating current is abnormal, specifically, sentence
Whether disconnected operating current is in preset current range, if it is, operating current is normal, otherwise, operating current is abnormal.Here
The CPU that monitors as needed of current range be configured.
In an embodiment of the present invention, described to judge whether the process of CPU readings RCW is abnormal, if so, thening follow the steps
104：Output CPU reads the information that the process of RCW is abnormal, and otherwise, executes step 105；Including：
B1：Judge whether the SRC for the RCW that CPU is read is correct, if it is, executing B2, otherwise, the SRC for exporting RCW is wrong
Information accidentally；
B2：Judge whether the format for the RCW that CPU is read is correct, if so, 105 are thened follow the steps, otherwise, output
The information of the format error of RCW.
Read RCW be CPU hardware reset after first process, the RCW be mainly used for be arranged platform clock, DDR clocks,
High-speed peripheral pattern, the key parameters such as IRQ.After CPU detects hardware reset signal, internal key logic and clock are initialized
Start detection reads RCW from which kind of medium after PLL, PowerPC series CPU is supported from EEPROM, NorFlash, SD Card
Read RCW.After RCW does not have exception, CPU is set according to the file content of RCW.
It in embodiments of the present invention, can be defeated by obtaining CPU when judging whether the SRC of the RCW of CPU readings is correct
The SRC gone out whether correct signals determine.It, can be by obtaining when judging whether the format of the RCW of CPU readings is correct
The whether correct signal of format of the RCW of CPU outputs is taken to determine.
In an embodiment of the present invention, described to judge that CPU reads BootFlash and whether the process of control serial ports is different
Often, if so, thening follow the steps 106：Output CPU reads BootFlash and controls the information that the process of serial ports is abnormal,
Including：
C1：Judge that CPU reads whether BootFlash succeeds, if it is, executing C2, otherwise, output is read
The information of BootFlash failures；
C2：Judge whether serial ports work is normal, abnormal information if it is not, then output serial ports works.
After configuring CPU according to RCW, CPU reads application program from BootFlash, executes program initialization serial ports, serial ports
Output content is had under normal circumstances.
In embodiments of the present invention, when judging whether CPU readings BootFlash is successful, following procedure reality can be passed through
It is existing：Judge that CPU reads whether the content in BootFlash is full 0 or complete 1, if it is, determining that CPU reads BootFlash and do not have
There is success, if it is not, then determining that CPU reads BootFlash successes.
In embodiments of the present invention, it when judging whether serial ports work is normal, can be realized by following procedure：Judge string
Whether the content of mouth output is full 0 or complete 1, if it is, determining that serial ports work is abnormal, otherwise, it determines serial ports is working properly.
In an embodiment of the present invention, it can judge whether the process that CPU is powered on and resetted is abnormal in the following manner：
When CPU is powered on and resetted, ASLEEP signals are high level, and ASLEEP signals are low electricity after powering on and resetting successfully
It is flat.
Whether the variation for measuring ASLEEP signals is by high level to low level, if so, determination CPU is powered on and resetted
Process is without abnormal, otherwise, it determines the process that CPU is powered on and resetted has exception.
Specifically, CPU here can be T4240.
In an embodiment of the present invention, it can judge whether the SRC for the RCW that CPU is read is correct in the following manner：
Cfg_rcw_src [0 can be passed through:8] it realizes.
Specifically, the level for detecting the pin of CPU determines the actual SRC of RCW according to the level of the pin of CPU, judges
Whether actual SRC and the SRC of design are identical, if it is, determining that the SRC for the RCW that CPU is read is correct, otherwise, it determines CPU
The SRC of the RCW of reading is incorrect.
In an embodiment of the present invention, the error codes of RCW can be determined by detecting DCFG_CCSR_RSTRQPBLSR
It is whether correct.
In an embodiment of the present invention, it can determine whether serial ports is normal, has on pin by detecting UARTn_SOUT
Signal exports, then serial ports is normal, and otherwise, serial ports is abnormal.
Here serial ports can be uart serial ports.
As shown in Fig. 2, an embodiment of the present invention provides a kind of method of the start-up course of monitoring CPU, when CPU starts to start
When process, following steps are executed：
Step 201：The nuclear power information for obtaining the nuclear power of CPU judges whether the nuclear power of CPU is abnormal, such as according to nuclear power information
Fruit is to execute step 202, otherwise, executes step 203.
Step 202：Export the information of nuclear power exception.
Step 203：The reset signal for obtaining CPU judges whether the reset of CPU is abnormal according to reset signal, if so,
Step 204 is executed, otherwise, executes step 205.
Specifically, reset signal can be exported by the pin of CPU, may determine that whether CPU resets by reset signal
Success.
Step 204：Output resets abnormal information.
Step 205：The operating current for detecting CPU judges whether operating current is abnormal, if so, step 206 is executed, it is no
Then, step 207 is executed.
Step 206：The information of output services current anomaly.
Step 207：Judge whether the SRC for the RCW that CPU is read is correct, if so, thening follow the steps 208, otherwise, executes
Step 209.
Step 208：Judge whether the format for the RCW that CPU is read is correct, if so, thening follow the steps 210, otherwise, executes
Step 211.
Step 209：Export the information of the SRC mistakes of RCW.
Step 210：Judge that CPU reads whether BootFlash succeeds, if so, thening follow the steps 212, otherwise, executes step
Rapid 213.
Step 211：Export the information of the format error of RCW.
Step 212：Judge whether serial ports work is normal, if so, executing step 214, otherwise, executes step 215.
Step 213：The information of BootFlash failures is read in output.
Step 214：Export the normal information of CPU start-up courses.
Step 215：Export the abnormal information of serial ports work.
In embodiments of the present invention, when CPU start-up courses are abnormal, corresponding exception information can be exported, these
Exception information can help the quick locating hardware faults of commissioning staff, improve the maintainability and stability of product.
As shown in figure 3, an embodiment of the present invention provides a kind of CPLD, including：
First monitoring unit 301, the second monitoring unit 302 and third monitoring unit 303；
First monitoring unit 301, for when CPU starts start-up course, executing：Judge that CPU is powered on and resetted
Whether process is abnormal, if it is, otherwise the information that output CPU is powered on and the process that resets is abnormal triggers described second
Monitoring unit 302；
Second monitoring unit 302, whether the process for judging CPU readings RCW is abnormal, if it is, output CPU
Otherwise the information that the process of reading RCW is abnormal triggers the third monitoring unit 303；
Whether the third monitoring unit 303, the process for judging CPU reading BootFlash and control serial ports are different
Often, if it is, output CPU reads BootFlash and controls the information that the process of serial ports is abnormal.
In an embodiment of the present invention, first monitoring unit, for executing：
A1：The nuclear power information for obtaining the nuclear power of CPU judges whether the nuclear power of the CPU is different according to the nuclear power information
Often, if so, otherwise the information of output nuclear power exception executes A2；
A2：The reset signal for obtaining CPU judges whether the reset of the CPU is abnormal according to the reset signal, if
It is that output resets abnormal information, otherwise, executes A3；
A3：The operating current for detecting CPU judges whether the operating current is abnormal, if it is, output services electric current is different
Otherwise normal information triggers second monitoring unit.
In an embodiment of the present invention, second monitoring unit, for executing：
B1：Judge whether the SRC for the RCW that CPU is read is correct, if it is, executing B2, otherwise, the SRC for exporting RCW is wrong
Information accidentally；
B2：Judge whether the format for the RCW that CPU is read is correct, if it is, the third monitoring unit is triggered,
Otherwise, the information of the format error of RCW is exported.
In an embodiment of the present invention, the third monitoring unit, for executing：
C1：Judge that CPU reads whether BootFlash succeeds, if it is, executing C2, otherwise, output is read
The information of BootFlash failures；
C2：Judge whether serial ports work is normal, abnormal information if it is not, then output serial ports works.
As shown in figure 4, an embodiment of the present invention provides a kind of systems of the start-up course of monitoring CPU, including：
Any CPLD 401 and display module 402 in the embodiment of the present invention；
The CPLD 401 is connected with the display module 402；
The CPLD 401 includes：First monitoring unit 4011, the second monitoring unit 4012 and third monitoring unit 4013；
The display module 402, the process for powering on and resetting for receiving the CPU that first monitoring unit 4011 exports
The information being abnormal, and show；The process for receiving the CPU readings RCW that second monitoring unit 4012 exports is abnormal
Information, and show；The CPU that the third monitoring unit 4013 exports is received to read BootFlash and control the mistake of serial ports
The information that journey is abnormal, and show.
In an embodiment of the present invention, the display module includes：Charactron, display screen.
Here charactron can be realized by LED.
In an embodiment of the present invention, which, which can be also used for working as, judges that the process that CPU is powered on and resetted does not have
When being abnormal, display CPU is powered on and the process that resets is not abnormal information.
In an embodiment of the present invention, which, which can be also used for working as, judges that the process of CPU readings RCW is not sent out
When raw abnormal, display CPU reads the information that the process of RCW is not abnormal.
In an embodiment of the present invention, which, which can be also used for working as, judges that CPU reads BootFlash and control
When the process of serial ports processed is not abnormal, display CPU reads BootFlash and the process of control serial ports is not abnormal
Information.
In embodiments of the present invention, display module needs information to be shown that can be shown by the form of code.
Specifically, can corresponding code be set to each exception in CPU start-up courses, can also is normal process
Corresponding code is set.As shown in table 1.
Table 1
| Code | Explanation |
| 10 | CPU core electricity is normally and reset is normal |
| 11 | Nuclear power is abnormal |
| 12 | It resets abnormal |
| 13 | Operating current is abnormal |
| 20 | CPU reads RCW successes and configuration successful |
| 21 | The SRC mistakes of RCW |
| 22 | The format error of RCW |
| 30 | CPU is normal, and can read BootFlash |
| 31 | CPU is normal, reads BootFlash failures |
| 32 | CPU is normal, and serial ports work is abnormal |
In an embodiment of the present invention, which is used for：When the first monitoring unit judges that the nuclear power generation of CPU is different
Chang Shi shows the information (can show code 11) of nuclear power exception；When the first monitoring unit judges that the reset of CPU is abnormal
When, display resets abnormal information (can show code 12)；When the first monitoring unit judges that operating current is abnormal,
The information (can show code 13) for showing operating current exception, when to judge that operating current does not occur different for the first monitoring unit
Chang Shi, display CPU core electricity is normal and resets normal information (can show code 10).
In an embodiment of the present invention, which is used for：When the second monitoring unit judges the RCW's that CPU is read
When SRC is incorrect, the information (can show code 21) of the SRC mistakes of RCW is shown；When the second monitoring unit judges that CPU is read
When the format of the RCW taken is incorrect, the information (can show code 22) of the format error of RCW is shown；When the second monitoring unit
When judging that the format for the RCW that CPU is read is correct, display CPU reads RCW successes and configuration successful (can show code 20).
In an embodiment of the present invention, which is used for：When third monitoring unit judges that CPU is read
When BootFlash is unsuccessful, the information (can show code 31) of BootFlash failures is read in display；When third monitoring unit
When judging that serial ports work is abnormal, the abnormal information (can show code 32) of display serial ports work；When third monitors list
When member judges that serial ports is working properly, display CPU is normal and can read the information (can show code 30) of BootFlash.
Furthermore it is also possible to judge whether CPU executes the success of BootFlash programs by third monitoring unit, if it is not, then
Output executes the unsuccessful information of BootFlash programs.
The each embodiment of the present invention at least has the advantages that：
1, in embodiments of the present invention, the start-up course of CPU is divided into：CPU power on and reset process, CPU read RCW
Process and CPU read BootFlash and control serial ports process, these three processes are monitored automatically by CPLD,
Without manually monitoring, it is capable of the start-up course of more easily monitoring CPU.
2, in embodiments of the present invention, when CPU start-up courses are abnormal, corresponding exception information can be exported, this
A little exception informations can help the quick locating hardware faults of commissioning staff, improve the maintainability and stability of product.
It should be noted that herein, such as first and second etc relational terms are used merely to an entity
Or operation is distinguished with another entity or operation, is existed without necessarily requiring or implying between these entities or operation
Any actual relationship or order.Moreover, the terms "include", "comprise" or its any other variant be intended to it is non-
It is exclusive to include, so that the process, method, article or equipment including a series of elements includes not only those elements,
But also include other elements that are not explicitly listed, or further include solid by this process, method, article or equipment
Some elements.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including
There is also other identical factors in the process, method, article or equipment of the element.
One of ordinary skill in the art will appreciate that：Realize that all or part of step of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can be stored in computer-readable storage medium, the program
When being executed, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes：ROM, RAM, magnetic disc or light
In the various media that can store program code such as disk.
Finally, it should be noted that：The foregoing is merely presently preferred embodiments of the present invention, is merely to illustrate the skill of the present invention
Art scheme, is not intended to limit the scope of the present invention.Any modification for being made all within the spirits and principles of the present invention,
Equivalent replacement, improvement etc., are included within the scope of protection of the present invention.
Claims (10)
1. a kind of method of the start-up course of monitoring CPU, which is characterized in that be applied to complex programmable logic device (CPLD), packet
It includes：
When CPU starts start-up course, execute：
S1：Judge whether the process that CPU is powered on and resetted is abnormal, if it is, the process generation that output CPU is powered on and resetted is different
Otherwise normal information executes S2；
S2：Judge that CPU is read and reset whether the process for configuring RCW is abnormal, if it is, the process that output CPU reads RCW occurs
Otherwise abnormal information executes S3；
S3：Judge that CPU reads startup flash memory BootFlash and whether the process of control serial ports is abnormal, if it is, output
CPU reads BootFlash and controls the information that the process of serial ports is abnormal.
2. according to the method described in claim 1, it is characterized in that,
The S1, including：
A1：The nuclear power information for obtaining the nuclear power of CPU judges whether the nuclear power of the CPU is abnormal, such as according to the nuclear power information
Fruit is to export the information of nuclear power exception, otherwise, executes A2；
A2：The reset signal for obtaining CPU judges whether the reset of the CPU is abnormal, if so, defeated according to the reset signal
Go out to reset abnormal information, otherwise, executes A3；
A3：The operating current for detecting CPU judges whether the operating current is abnormal, if it is, output services current anomaly
Otherwise information executes S2.
3. according to the method described in claim 1, it is characterized in that,
The S2, including：
B1：Judge whether the SRC for the RCW that CPU is read is correct, if it is, otherwise executing B2 exports the SRC mistakes of RCW
Information；
B2：Judge whether the format for the RCW that CPU is read is correct, if it is, otherwise executing S3 exports the format of RCW
The information of mistake.
4. according to any method in claim 1-3, which is characterized in that
The S3, including：
C1：Judge that CPU reads whether BootFlash succeeds, if it is, executing C2, otherwise, output is read BootFlash and lost
The information lost；
C2：Judge whether serial ports work is normal, abnormal information if it is not, then output serial ports works.
5. a kind of complex programmable logic device (CPLD), which is characterized in that including：
First monitoring unit, the second monitoring unit and third monitoring unit；
First monitoring unit, for when CPU starts start-up course, executing：Judge that CPU is powered on and whether is the process that resets
It is abnormal, if it is, the information that output CPU is powered on and the process that resets is abnormal, otherwise, triggering the second monitoring list
Member；
Second monitoring unit, whether the process for judging CPU reading reset configurations RCW is abnormal, if it is, output
Otherwise the information that the process of CPU readings RCW is abnormal triggers the third monitoring unit；
Whether the third monitoring unit, the process for judging CPU readings startup flash memory BootFlash and control serial ports are different
Often, if it is, output CPU reads BootFlash and controls the information that the process of serial ports is abnormal.
6. CPLD according to claim 5, which is characterized in that
First monitoring unit, for executing：
A1：The nuclear power information for obtaining the nuclear power of CPU judges whether the nuclear power of the CPU is abnormal, such as according to the nuclear power information
Fruit is to export the information of nuclear power exception, otherwise, executes A2；
A2：The reset signal for obtaining CPU judges whether the reset of the CPU is abnormal, if so, defeated according to the reset signal
Go out to reset abnormal information, otherwise, executes A3；
A3：The operating current for detecting CPU judges whether the operating current is abnormal, if it is, output services current anomaly
Otherwise information triggers second monitoring unit.
7. CPLD according to claim 5, which is characterized in that
Second monitoring unit, for executing：
B1：Judge whether the SRC for the RCW that CPU is read is correct, if it is, otherwise executing B2 exports the SRC mistakes of RCW
Information；
B2：Judge whether the format for the RCW that CPU is read is correct, if it is, the third monitoring unit is triggered, otherwise,
Export the information of the format error of RCW.
8. according to any CPLD in claim 5-7, which is characterized in that
The third monitoring unit, for executing：
C1：Judge that CPU reads whether BootFlash succeeds, if it is, executing C2, otherwise, output is read BootFlash and lost
The information lost；
C2：Judge whether serial ports work is normal, abnormal information if it is not, then output serial ports works.
9. a kind of system of the start-up course of monitoring CPU, which is characterized in that including：
Any complex programmable logic device (CPLD) and display module in claim 5-8；
The CPLD is connected with the display module；
The CPLD includes：First monitoring unit, the second monitoring unit and third monitoring unit；
The display module, the CPU for receiving first monitoring unit output is powered on and the process that resets is abnormal
Information, and show；The CPU for receiving the second monitoring unit output reads the information that the process of reset configuration RCW is abnormal,
And it shows；The CPU for receiving the third monitoring unit output reads the process hair for starting flash memory BootFlash and controlling serial ports
Raw abnormal information, and show.
10. system according to claim 9, which is characterized in that
The display module includes：Charactron, display screen.
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