CN103996637A - Method for measuring electric leakage of PMOS device - Google Patents
Method for measuring electric leakage of PMOS device Download PDFInfo
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- CN103996637A CN103996637A CN201410253237.0A CN201410253237A CN103996637A CN 103996637 A CN103996637 A CN 103996637A CN 201410253237 A CN201410253237 A CN 201410253237A CN 103996637 A CN103996637 A CN 103996637A
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- pmos
- contact zone
- pmos device
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- source electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- Microelectronics & Electronic Packaging (AREA)
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention provides a method for measuring an electric leakage of a PMOS device. The method comprises the steps that a wafer with a formed CMOS device is placed on a test tray, wherein the CMOS device comprises the PMOS device and an NMOS device which are formed on the same substrate in pair, the PMOS device comprises a P-type drain electrode, a P-type source electrode and an N-body contact zone, the P-type drain electrode, the P-type source electrode and the N-body contact zone are formed in an N-well in the substrate, the NMOS device comprises an N-type drain electrode, an N-type source electrode and a P-body contact zone, the N-type drain electrode, the N-type source electrode and the P-body contact zone are formed in an P-well in the substrate, and the N-well is electrically isolated from the P-well through an isolation zone; under the condition that the voltage exerted on the contact zone of the NMOS device is identical to the voltage exerted on the N-body contact zone, electric leakage measurement is conducted on the PMOS device. By the adoption of the method for measuring the electric leakage of the PMOS device, under the condition that the layout of an existing CMOS device is not changed, the problem that when the PMOS is in the switched-off state, the electric leakage is large is solved, the utilization efficiency of the device is improved, the occupied area of the layout is reduced, and the purpose of cost reduction is achieved.
Description
Technical field
The present invention relates to the WAT test (wafer acceptance test, wafer acceptability test) of cmos semiconductor device, more particularly, the present invention relates to a kind of PMOS element leakage method of measurement.
Background technology
Along with the development of cmos semiconductor device technology and in proportion size dwindle, when design will taking into account system standby power consumption, the closed condition electric leakage of the inevitable low cmos device of will begging to surrender.Metric data is the basic of processing procedure research and development accurately.
After WAT (wafer acceptance test, wafer acceptability test) refers to that whole wafer manufacturing completes, but before also not encapsulating, the feeler switch in Cutting Road (testkey) is tested.WAT test is that semi-conductor silicon chip completes after all making technologies, the testing electrical property carrying out for the various test structures on silicon chip.By the analysis to WAT data, can find the problem in manufacture of semiconductor technique, help making technology to adjust.
But in existing WAT test, traditional method is to add operating voltage Vdd in drain electrode, source electrode, grid and tagma ground connection, remove to measure drain current.But as shown in Figure 1, in fact because wafer is placed on test pallet (chuck) 100, test pallet 100, because board is imperfect, causes having parasitic electric charge and retains.In measuring process, this electric charge just may flow to substrate, and then flows to the N trap 20 on substrate 10.Now, the leakage current IB that termination contact area 50 places, tagma record will increase, and causes test data inaccurate.Shown in Fig. 2, be the datagram of long channel device, leakage current IB has obviously been greater than drain current ID.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, a kind of PMOS element leakage method of measurement is provided, it can be under the situation of layout that does not change existing cmos device, solve the PMOS closed condition occurring in the WAT test situation bigger than normal of leaking electricity, the utilization ratio of boost device, thereby reduce layout area occupied, reach the object reducing costs.
In order to realize above-mentioned technical purpose, according to the present invention, a kind of PMOS element leakage method of measurement is provided, and it comprises: the wafer that is formed with cmos device is placed on test pallet, and wherein cmos device comprises paired PMOS device and the nmos device that are formed on same substrate; And PMOS device comprises the drain electrode of P type, P type source electrode and the contact zone, N-type tagma in the N trap being formed in substrate, nmos device comprises N-type drain electrode, N-type source electrode and the contact zone, P type tagma in the P trap being formed in substrate; N trap and P trap are by the isolation of isolated area electricity; And the voltage identical with voltage on contact zone, N-type tagma, PMOS device is carried out to electric leakage and measure in the case of the contact zone of nmos device is applied.
Preferably, the voltage identical with voltage on contact zone, N-type tagma is 0V voltage.
Preferably, PMOS device is carried out to electric leakage measurement to be comprised: electric current, the electric current at grid place of PMOS device and the electric current at the source electrode place of PMOS device of the leakage current at the termination contact area place, tagma of measurement PMOS device, drain electrode place of PMOS device, and determine the relation between these electric currents.
The present invention utilizes the conduction of nmos device tagma end and substrate in cmos device, increase a 0V voltage at the tagma of NMOS end, like this, substrate has just had a 0V voltage, and 0 voltage difference between the N trap of PMOS device can ensure that the electric leakage that spurious charge can not affect IB measures.Thus, the invention provides a kind of PMOS element leakage method of measurement, it can be under the situation of layout that does not change existing cmos device, solve the PMOS closed condition occurring in the WAT test situation bigger than normal of leaking electricity, the utilization ratio of boost device, thereby reduce layout area occupied, reach the object reducing costs.
Brief description of the drawings
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows according to the PMOS element leakage of prior art and measures structure.
Fig. 2 schematically shows the PMOS element leakage measurement result according to prior art.
Fig. 3 schematically shows PMOS element leakage according to the preferred embodiment of the invention and measures structure.
Fig. 4 schematically shows PMOS element leakage measurement result according to the preferred embodiment of the invention.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 3 schematically shows PMOS element leakage according to the preferred embodiment of the invention and measures structure.
As shown in Figure 3, PMOS element leakage method of measurement comprises according to the preferred embodiment of the invention:
The wafer that is formed with cmos device is placed on test pallet 100, and wherein cmos device comprises paired PMOS device and the nmos device that are formed on same substrate 10; And PMOS device comprises P type drain electrode 40, P type source electrode 50 and the contact zone, N-type tagma 60 in the N trap 20 being formed in substrate 10, PMOS device also comprises the base stage 70 being formed on substrate 10; Nmos device comprises N-type drain electrode 41, N-type source electrode 51 and the contact zone, P type tagma 61 in the P trap 21 being formed in substrate 10, and nmos device also comprises the base stage 71 being formed on substrate 10; N trap 20 is isolated by isolated area 30 electricity with P trap 21;
Apply in the contact zone 61 to nmos device and in the situation of the voltage (preferably, 0V voltage) identical with voltage on contact zone, N-type tagma, PMOS device is carried out to electric leakage and measure.Now, can adopt the PMOS element leakage metering system of any appropriate of prior art to carry out follow-up measurement.
For example, PMOS device is carried out to electric leakage to be measured and can comprise: under test condition, measure electric current, the electric current at grid 70 places of PMOS device and the electric current at source electrode 60 places of PMOS device at drain electrode 40 places of leakage current, the PMOS device at termination contact area 50 places, tagma of PMOS device, and determine the relation between these electric currents.
By so doing, get rid of the interference that board spurious charge is brought, and do not increased cost, utilize existing CMOS layout.The technical enforcement of the method is fairly simple.Only many use tests board emulation input, does not increase the testing time.Test result demonstration, as shown in Figure 4, the more original value bigger than normal of leakage current IB value that termination contact area 50 places, tagma record, has had significant improvement, approaches desirable measured value; Approximate have ID=IG+IB+IS, and wherein ID refers to the electric current recording in drain electrode, and IG refers to the electric current recording at grid, and IS refers to the electric current recording at source electrode.
Thus, the present invention utilizes the conduction of nmos device tagma end and substrate in cmos device, as shown in Figure 3, increase a 0V voltage at the tagma of NMOS end, like this, substrate has just had a 0V voltage, and 0 voltage difference between the N trap 20 of PMOS device can ensure that the electric leakage that spurious charge can not affect IB measures (now, electric charge can flow to the tagma end of NMOS).
Thus, the invention provides a kind of PMOS element leakage method of measurement, it can be under the situation of layout that does not change existing cmos device, solve the PMOS closed condition occurring in the WAT test situation bigger than normal of leaking electricity, the utilization ratio of boost device, thereby reduce layout area occupied, reach the object reducing costs.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the descriptions such as term " first " in specification, " second ", " the 3rd " are only for distinguishing each assembly, element, step of specification etc., instead of for representing logical relation or the ordinal relation etc. between each assembly, element, step.
Be understandable that, although the present invention discloses as above with preferred embodiment, but above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (3)
1. a PMOS element leakage method of measurement, is characterized in that comprising:
The wafer that is formed with cmos device is placed on test pallet, and wherein cmos device comprises paired PMOS device and the nmos device that are formed on same substrate; And PMOS device comprises the drain electrode of P type, P type source electrode and the contact zone, N-type tagma in the N trap being formed in substrate, nmos device comprises N-type drain electrode, N-type source electrode and the contact zone, P type tagma in the P trap being formed in substrate; N trap and P trap are by the isolation of isolated area electricity; And
The voltage identical with voltage on contact zone, N-type tagma, PMOS device is carried out to electric leakage and measure in the case of the contact zone of nmos device is applied.
2. PMOS element leakage method of measurement according to claim 1, is characterized in that, the voltage identical with voltage on contact zone, N-type tagma is 0V voltage.
3. PMOS element leakage method of measurement according to claim 1 and 2, it is characterized in that, PMOS device is carried out to electric leakage measurement to be comprised: electric current, the electric current at grid place of PMOS device and the electric current at the source electrode place of PMOS device of the leakage current at the termination contact area place, tagma of measurement PMOS device, drain electrode place of PMOS device, and determine the relation between these electric currents.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410253237.0A CN103996637B (en) | 2014-06-09 | PMOS device electric leakage measuring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410253237.0A CN103996637B (en) | 2014-06-09 | PMOS device electric leakage measuring method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103996637A true CN103996637A (en) | 2014-08-20 |
| CN103996637B CN103996637B (en) | 2016-11-30 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192676A (en) * | 2018-09-11 | 2019-01-11 | 长江存储科技有限责任公司 | The characterizing method of boundary defect |
| CN114252680A (en) * | 2021-12-16 | 2022-03-29 | 上海华虹宏力半导体制造有限公司 | Voltage contrast method for detecting leakage between source and drain |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001060628A (en) * | 1999-08-23 | 2001-03-06 | Hitachi Ltd | Semiconductor integrated circuit device |
| CN1742209A (en) * | 2003-02-20 | 2006-03-01 | 国际商业机器公司 | Integrated circuit testing methods using trap bias modification |
| CN1812102A (en) * | 2004-12-22 | 2006-08-02 | 恩益禧电子股份有限公司 | CMOS semiconductor device |
| US20090170255A1 (en) * | 2002-12-13 | 2009-07-02 | Hrl Laboratories, Llc | Integrated circuit modification using well implants |
| CN101545945A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for testing leakage current of MOS device |
| CN102420226A (en) * | 2011-06-15 | 2012-04-18 | 上海华力微电子有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor Transistor) for inhibiting drain induced barrier lowering effect and manufacturing method of CMOS |
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001060628A (en) * | 1999-08-23 | 2001-03-06 | Hitachi Ltd | Semiconductor integrated circuit device |
| US20090170255A1 (en) * | 2002-12-13 | 2009-07-02 | Hrl Laboratories, Llc | Integrated circuit modification using well implants |
| CN1742209A (en) * | 2003-02-20 | 2006-03-01 | 国际商业机器公司 | Integrated circuit testing methods using trap bias modification |
| CN1812102A (en) * | 2004-12-22 | 2006-08-02 | 恩益禧电子股份有限公司 | CMOS semiconductor device |
| CN101545945A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for testing leakage current of MOS device |
| CN102420226A (en) * | 2011-06-15 | 2012-04-18 | 上海华力微电子有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor Transistor) for inhibiting drain induced barrier lowering effect and manufacturing method of CMOS |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192676A (en) * | 2018-09-11 | 2019-01-11 | 长江存储科技有限责任公司 | The characterizing method of boundary defect |
| CN114252680A (en) * | 2021-12-16 | 2022-03-29 | 上海华虹宏力半导体制造有限公司 | Voltage contrast method for detecting leakage between source and drain |
| CN114252680B (en) * | 2021-12-16 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Voltage contrast method for detecting leakage between source and drain |
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