CN103986889B

CN103986889B - For the system and method for Transducer fault detection

Info

Publication number: CN103986889B
Application number: CN201410041409.8A
Authority: CN
Inventors: R.约翰逊; T.马蒂努森
Original assignee: Omnivision Technologies Inc
Current assignee: Omnivision Technologies Inc
Priority date: 2013-02-08
Filing date: 2014-01-28
Publication date: 2017-06-13
Anticipated expiration: 2034-01-28
Also published as: CN103986927A; CN103986927B; CN103986889A

Abstract

Novel imageing sensor includes pel array, line control circuit, test signal injection circuit, sample circuit, image processing circuit, comparison circuit and control circuit.In a specific embodiment, test signal is injected into the pel array by the test signal injection circuit, and the sample circuit obtains the pixel data from the pel array, and the comparison circuit compares the pixel data and the test signal.If the pixel data does not correspond to the test signal, the comparison circuit output error signal.Additionally, the comparison circuit is provided to detect the failure in the control circuit of the imageing sensor.

Description

For the system and method for Transducer fault detection

Related application

This application is entitled " for the system and method for Transducer fault detection ", is filed in 2013 by identical inventor 8 days 2 months year, the divisional application of the Copending U.S. Patent Application of Application No. 13/763,498, application 13/763,498 is on the whole It is hereby incorporated.

Technical field

This patent disclosure relates generally to imageing sensor, more particularly to imageing sensor fault detect.

Background technology

Electronic image sensor is generally integrated into including such as mobile phone, computer, digital camera, personal digital assistant （Personal Digital Assistant, PDA）Deng various devices in.Except the stationary video camera of legacy user's control Outside, increasing image sensor application is being risen.For example, overall machine vision applications promptly expand In car industry, manufacturing industry, medical treatment, safety and national defense industry.In such applications, machine is typically based on by the figure of the machine As the information of capture systems capture（For example, position of the object relative to another object）Perform some operation tasks（For example, anti- Only collide task）.In order that the machine performs the appropriate task related to particular case, imageing sensor must reliably catch Obtain, process and export the view data for representing situation about observing exactly.

Complementary metal oxide semiconductors (CMOS)（Complementary Metal Oxide Semiconductor, CMOS）Figure As sensor is generally included：Sensor array, control circuit, line control circuit（For example, row-address decoder, pixel driver Deng）, row sample circuit and image processing circuit.The lens assembly that imageing sensor is generally aligned with sensor array coordinates and makes With with focusedimage thereon.Incident light is changed into the sensor array the electric data for representing image.The sensor array by Constituted with multiple light sensitive pixels that multiple row and columns are arranged.These pixels are electrically coupled to via the grid of row and column holding wire respectively Line control circuit and row sample circuit.That is, each independent pixel is passed through by including such as transmission line, reset line （reset line）And the associated row signal line group of row select line is connected to line control circuit and by the line control circuit control System.Each independent pixel is arranged and is connected to row sample circuit via separate row sampling line.The row sample circuit generally includes all Such as the sampling element of amplifier, analogue-to-digital converters and data storage elements etc, it is coupled to row sampling line, is used for Digitize and store the electric signal from pixel output.In with the parallel imageing sensor for reading framework of row, row sample circuit Discrete groups including these sampling elements for each row sampling line, in order to the whole pixel column that can sample simultaneously.In row In parallel reading framework, row sample circuit also includes routing to the various holding wires of various sampling elements, with to there conveying control Signal processed.（The parallel framework that reads of non-row is also required to various level signal lines, although be not with row parallel architecture as many.）The figure The digitalized data of row sample circuit output is received from as process circuit, and view data is produced with readable format.Interface energy Enough make imageing sensor and host computer system（For example, hand-set host plate, carried-on-vehicle computer system, manufacture machine computer system etc.） Communicated（For example, output formatting image/video data, reception operational order etc.）.Generally, the control electricity of imageing sensor Road is connected to line control circuit, row sample circuit, image processing circuit and interface, to perform various timings and control operation.

Each pixel includes：Light-sensitive element（For example, photodiode, light electric switch（photogate）Deng）, transmission crystal Pipe, floating diffusion region, reset transistor, source electrode are followed（source-follower）Transistor and row selecting transistor.Should Light-sensitive element operates the electric charge proportional to accumulate the intensity of the incident light being exposed to during shutter operation to it.The transmission is brilliant Light-sensitive element is connected to floating diffusion region by body pipe, and including being connected to single transmission line simultaneously therefore by the single transmission line The gate pole of control, the wherein single transmission line are exclusively used in whole pixel column.When logical high voltage signal applies on the transmission line, Electric charge from light-sensitive element is transferred to floating diffusion region.Floating diffusion region is connected to voltage source by the reset transistor Terminal, and including being connected to the reset line of row signal line simultaneously therefore by the gate pole of the reset line traffic control of the row signal line.When patrolling Collect high voltage signal to be applied to when on reset line, floating diffusion region is connected to voltage source terminal by the reset transistor, therefore Any previously stored resetting charge is known into state to oneself.It is brilliant that voltage source terminal is connected to row selection by the source following transistor Body pipe, and including being connected to the gate pole of floating diffusion region, the electric charge accumulated in floating diffusion region is represented to produce Amplify voltage signal.Source following transistor is connected to the row selecting transistor pixel output line of the alignment, and including The gate pole being connected with the row select line of the line.When logic low-voltage is applied in row select line, row selecting transistor conduct Unlatching switch between source following transistor and pixel output line.On the contrary, the logic being applied on the gate pole of row select line High voltage makes row selecting transistor as the closure switch between source following transistor and row sampling line, in order to pass through The state of row sampling line sampling floating diffusion.

Although conventional image sensor meets the demand of many images and Video Capture application, current design exists scarce Fall into.For example, cmos pixel by be easy to break down integrated circuit component（For example, transistor, diode, capacitor etc.）Structure Make.As another example, pixel row signal line（For example, transmission line, reset line, row select line etc.）, row sampling line and row adopt Sample element control line（For example, gain amplifier control line, analogue-to-digital converters control line, digitized pixel data storage are filled Put control line etc.）It is easily damaged, be especially subjected to a large amount of distributing pressure cause formula load those.As another problem, Line control circuit is also easy to break down.In the case of occurring any one of above-mentioned failure in conventional image sensor, its Generally the view data of mistake is exported to host computer system.Certainly, the view data of the usual nonrecognition mistake of host computer system with just Difference between true view data.This may especially in which the view data be indicated by the operation task of host computer system execution Some application（That is, overall machine vision applications）In there is problem.Even when circuit is not very easy to damage or occur event During barrier, some applications（For example, automobile application）Needing system has high reliability.

Accordingly, it would be desirable to have the image sensor design of the view data output reliability of improvement.

The content of the invention

The present invention overcomes problem associated with the prior art by providing the imageing sensor with integrated fault detect. Failure in various aspects of the invention detection light sensitive pixels, the control line of pel array and sample/hold circuit.

Example images acquisition equipment includes multiple pixels.Each pixel has optical sensor, charge storage region, letter Number output end and test signal input.The charge storage region optionally couples to receive the light from the optical sensor Electric current.The signal output part is coupled to the charge storage region, and exports the electricity for representing storage in the charge storage region The signal of lotus amount.The test signal input is also coupled to the charge storage region.Test signal injection circuit be coupled to by Test signal provides to the test signal input of pixel, and sample circuit and is selectively coupled to receive from pixel The output signal of output end.Comparison circuit is compared the test signal provided to pixel with the output signal received from pixel Compared with, and if the output signal does not correspond to test signal, then the comparison circuit provides error signal.Alternatively, the test Injection circuit is coupled to the comparison circuit, and the test signal provided to pixel is directly supplied into the comparison circuit. Disclose various devices to be compared with the output signal received from pixel with by the test signal provided to pixel, and respond Error signal is provided in the output signal for not corresponding to test signal.

In the embodiment disclosed, pixel arrangement is arranged for multiple, and the image capture apparatus inject including a plurality of electric charge Line.Each the test signal input of the pixel of respective column is coupled to test signal injection circuit by electric charge injection line.It is each The charge storage region of individual pixel injects line via capacitor coupled to a corresponding electric charge, and is not inserted into pixel Switching device between charge storage region and electric charge injection line.

In the embodiment disclosed, the test signal injection circuit can provide different on different electric charge injection lines Test signal, it is also possible to provide different test signals on identical electric charge injection line with different timing.

Exemplary test injection circuit includes multiple test signal memory elements and measuring signal generator.It is each Individual selectively coupled to the corresponding electric charge injection line of test signal memory element.Measuring signal generator is coupled to test signal Memory element, and operate to produce test signal value, and by the storage of test signal value in memory element.

In a particular embodiment, measuring signal generator operation is to produce digital test signal value, and each is stored Element is unit（single-bit）Memory element.The measuring signal generator includes random bit generators.Memory element string It is coupled connection, and the position from random bit generators is moved to memory element.

Pixel can be operated in image capture mode or test pattern.The charge storage region of each pixel is by every The switching device of one pixel is selectively coupled to the optical sensor of each pixel.Controller is coupled to transmission signal There is provided to the switching device of pixel.In response to the first value of transmission signal, switching device conduction optical sensor and electric charge storage region Photoelectric current between domain, to be easy to image capture.In response to the second value of transmission signal, switching device prevents optical sensor with electricity Photoelectric current between lotus storage region, to be easy to test signal injection.In operation, the image capture apparatus are in continuous frame Between it is upper perform the image capture process for repeating, with capture images data frame.The controller applies the second value of the transmission signal Plus the duration of image capture process, being injected with the test signal for being easy to every N frame times, wherein N is the integer more than 1.

The device of the failure in the control circuit of detection image acquisition equipment is also disclosed that in addition.In example images capture In device, controller provides control signal.In response to control signal, driver operation drives letter to be produced based on control signal Number, and drive signal is applied on the control line of image capture apparatus.If control signal does not correspond in a predefined manner The drive signal of applying, then comparator is in response to the first input based on control signal and in response to based on drive signal second Input produces error signal.In a particular embodiment, comparator directly comparison control signal and drive signal, to determine to drive Whether signal corresponds to control signal.Disclose various devices and be input into and based on driving letter for comparing based on control signal first Number second input, and if control signal in a predefined manner correspond to apply drive signal, then produce error signal.

In one example, driver is the row control driver of image sensor array.In another example, driver is The element of image data samples circuit, it receives the data row from image sensor array.

The open various devices for being used for comparison control signal and drive signal.In one exemplary embodiment, image capture Device further includes to be coupled to receive control signal and operates and produces the of the second drive signal with based on control signal Two drivers, and comparator compares the second drive signal and drive signal.

In a further exemplary embodiment, the first encoder at first point be coupled to a plurality of control line, and based on The drive signal detected on a plurality of control line produces the first encoded radio.Second encoder is apart from first certain distance The a plurality of control line is coupled at the second point at place, and second is produced based on the drive signal detected on a plurality of control line Encoded radio.Comparator operations are comparing first encoded radio and second encoded radio.

Method for the failure in detection image acquisition equipment is also disclosed.Illustrative methods include：Offer includes sensing The image capture apparatus of device array, make image focus on the sensor array, and repeatedly caught using the sensor array Obtain the frame of view data.The pictorial data representation focuses on the image on the sensor array.The method is further included：At this Test data is periodically injected into the sensor array between the repetition capture of view data, is read from the image capture apparatus The test data is taken, and compares read test data and the test data injected.If the test data for reading is not Corresponding to the test data of the injection, then error signal is produced.

Another exemplary method includes：Control signal is received, drive signal is produced based on the control signal, and this is driven Dynamic signal is applied on the control line of image capture apparatus.The method is further included：Compare drive signal and the control of applying Signal, and if the control signal does not correspond to the drive signal for applying in a predefined manner, then produce error signal.Specific In method, step drive signal being applied on the control line of image capture apparatus includes：Drive signal is applied to image On the row control line of sensor array.In another ad hoc approach, drive signal is applied to the control line of image capture apparatus On step include：Drive signal is applied on the control line of image data samples circuit.In another ad hoc approach, compare The step of drive signal of applying is with control signal includes：Second drive signal is produced based on control signal, and compare this Two driving signal and the drive signal.

Include in another exemplary method, the step of compare the drive signal of applying with control signal：Based on being applied to Drive signal at the first point on a plurality of control line produces the first encoded radio, and based on being applied on a plurality of control line These drive signals at second point produce the second encoded radio.Then, first encoded radio and second encoded radio are compared.

The additional method of the open failure for being used for detection image acquisition equipment.One illustrative methods include：Receive control letter Number, drive signal is produced based on the control signal, the drive signal is applied on the control line of the image capture apparatus, and Compare the drive signal and the control signal of the applying.The method is further included：If the control signal is not in a predefined manner Corresponding to the drive signal for being applied, then error signal is produced.

In an ad hoc approach, step drive signal being applied on the control line of image capture apparatus includes：To drive Dynamic signal is applied on the row control line of image sensor array.In another ad hoc approach, drive signal is applied to image Step on the control line of acquisition equipment includes：Drive signal is applied on the control line of image data samples circuit.

Alternatively, the step of comparing the drive signal of applying with control signal can include：The is produced based on control signal Two driving signal, and compare second drive signal and the drive signal.Alternately, the drive signal of applying is compared The step of with control signal, can include：First is produced to compile based on the drive signal at the first point being applied on a plurality of control line Code value, and the second encoded radio is produced based on these drive signals at the second point being applied on a plurality of control line, and Compare first encoded radio and second encoded radio.

Various methods can also be used in combination.For example, the method for above-mentioned summary may further include：Second is received to control Signal, the second drive signal is produced based on second control signal, and second drive signal is applied into image capture apparatus On second control line, and compare the input based on second drive signal He second control signal.If second control Signal does not correspond to second drive signal in a predefined manner, produces the second error signal.

In an illustrative methods, the image capture apparatus further include that image sensor array and view data are adopted Sample circuit, is coupled to receive the data row from the image sensor array.In the illustrative methods, the drive signal is Row control drive signal in the image sensor array, and during second drive signal is the image data samples circuit Drive signal.

Another exemplary method is further included：Test data is periodically injected into image sensor array；And Compare and be injected into the test data of the image sensor array and connect from the sensor array with by the image data samples circuit The test data for receiving.The illustrative methods also include：If being injected into the test data of the image sensor array not with pre- Determine mode and correspond to the pass the test data that the image data samples circuit is received from the sensor array, then produce the 3rd mistake Error signal.

A kind of example images acquisition equipment is also disclosed.The example images acquisition equipment includes：Controller, operates to carry For control signal；Driver and comparator.The driver is operated with based on control letter in response to the control signal Number drive signal is produced, and the drive signal is applied on the control line of the image capture apparatus.The comparator in response to The first input based on the control signal and the second input based on the drive signal.If the control signal is not with predetermined party Formula corresponds to applied drive signal, then the comparator produces error signal.

Various devices are disclosed, for comparing the first input based on control signal and the second input based on drive signal, And if the control signal then produces error signal not in a predefined manner corresponding to the drive signal of the applying.

In a certain exemplary embodiments, the comparator directly compares the control signal and the drive signal, to determine Whether the drive signal corresponds to the control signal.

In one example, the image capture apparatus further include image sensor array, and the driver is the figure As the row control driver of sensor array.In another example, the image capture apparatus further include to be coupled to receive The image data samples circuit of the data row from the image sensor array, and the driver is image data samples electricity The element on road.

It is open to be used to determine the multiple devices whether control signal corresponds to drive signal.For example, in an exemplary implementation In example, the image capture apparatus further include the second driver, are coupled to receive the control signal.Second driver is grasped Make to produce the second drive signal, and the comparator operations to compare second drive signal and the drive with based on the control signal Dynamic signal.

In a further exemplary embodiment, the image capture apparatus further include a plurality of control line.First encoder exists The a plurality of control line is coupled at first point, and is operable to be produced based on the drive signal detected on a plurality of control line Raw first encoded radio.Second encoder at first second point of certain distance be coupled to a plurality of control line, and And be operable to produce the second encoded radio based on the drive signal detected on a plurality of control line.Then, the comparator ratio Compared with first encoded radio and second encoded radio.

Multiple exemplary embodiments of the invention can be embodied in single image acquisition equipment.For example, except the first driving Outside device, disclosed embodiment includes the second driver in response to the second control signal.Second driver is operable to produce Raw second drive signal, and second drive signal is applied on the second control line of the image capture apparatus.Second ratio Compared with device in response to the first input based on second control signal and the second input based on second drive signal.This second If comparator is operable to be easy to second control signal not correspond to second drive signal in a predefined manner, the is produced Two error signals.Additionally, the image capture apparatus include image sensor array and image data samples circuit, it is coupled to Receive the data row from the image sensor array.The driver is the row control driver of the image sensor array, should Second driver is the element of the image data samples circuit.Additionally, the example images acquisition equipment further includes test Data injection circuit, is operable to be periodically injected into test data to the image sensor array.3rd comparator is grasped Work is injected into the test data of the image sensor array to compare and passes through the image data samples circuit from sensor array The test data for receiving.If the test data for being injected into image sensor array does not correspond to the pass the figure in a predefined manner As data sampling circuit from sensor array received to test data, then the 3rd comparator also produce the 3rd error signal.

Brief description of the drawings

With reference to the following Description of Drawings present invention, wherein similar reference represents essentially similar element：

Fig. 1 is the perspective view of the imageing sensor installed on host apparatus circuit board；

Fig. 2 is the block diagram of the imageing sensor of Fig. 1；

Fig. 3 is the schematic diagram of the pixel of the imageing sensor of Fig. 1；

Fig. 4 is the schematic diagram of the test signal injection circuit of the imageing sensor of Fig. 1；

Fig. 5 is two circuit diagrams of adjacent column injection circuit of the test signal injection circuit of Fig. 4；

Fig. 6 is pel array, the first line control unit, the second line control unit and the comparison circuit of the imageing sensor of Fig. 1 Circuit diagram；

Fig. 7 is the circuit diagram of the feature of the comparison circuit for showing Fig. 6；

Fig. 8 is the electricity of control circuit, pel array, sample circuit and the comparison circuit of the imageing sensor for showing Fig. 1 Lu Tu；

Fig. 9 is the circuit diagram of the additional detail of the comparison circuit for showing Fig. 8；

Figure 10 is the circuit diagram of another comparison circuit of the imageing sensor of Fig. 1；

Figure 11 is the timing diagram of operation of the imageing sensor of explanatory diagram 1 in image capture mode；

Figure 12 is the timing diagram of operation of the imageing sensor of explanatory diagram 1 in test pattern；

Figure 13 is the circuit diagram according to the comparison circuit of Fig. 7 in alternative embodiment of the invention；And

Figure 14 is according to the circuit diagram that sample circuit and replacement comparison circuit are replaced in another embodiment of the present invention.

Specific embodiment

The present invention includes the imageing sensor of failure detector circuit and overcomes problem associated with the prior art by providing. In the following description, illustrate many specific details (for example, image sensor types, type of pixel, transistor types, pixel Quantity etc.), to provide complete understanding of the present invention.However, those of ordinary skill in the art will be, it is realized that the present invention can be with Depart from these specific details and put into practice.In other examples, well known image sensor integrated circuit production practices are had been left out The details of (for example, transistor formation, colored filter formation, wafer cutting, semiconductor doping etc.) and element, so as not to it is unnecessary Obscure the present invention.

Fig. 1 is that the image in a part for printed circuit board (PCB) (Printed Circuit Board, PCB) 102 is passed The perspective view of sensor 100, the wherein PCB 102 represent camera hosting device (for example, automobile, manufacture machinery, Medical Devices, hand Machine etc.) PCB.Imageing sensor 100 carries out telecommunication with the other elements of host apparatus via a plurality of electric conduction routing 104. In exemplary embodiment, imageing sensor 100 is described as a part for camera model 106, and it further includes optical element 108 and shell 110.As illustrated, shell 110 is installed on imageing sensor 100, and optical element 108 is fixed therebetween.It is familiar with Those skilled in the art by, it is realized that PCB 102, cabling 104, optical element 108 and shell 110 particular design and/ Or presence will be depending on application-specific and not especially related to the present invention.Therefore, PCB 102, cabling 104, optics unit Part 108 and shell 110 are only character representation.

Fig. 2 is the block diagram of imageing sensor 100, and in this exemplary embodiment, the imageing sensor 100 is back-illuminated type (Backside Illuminated, BSI) cmos image sensor on-chip system (System-On-Chip, SOC).Image sensing Device 100 includes：Control circuit 200, pel array 202, test signal injection circuit 204, the first line control unit 206, the second row Controller 208, the first comparison circuit 210, sample circuit 212, the second comparison circuit 214, image processor 216 and the 3rd ratio Compared with circuit 218.

Control circuit 200 provide for coordinating and control imageing sensor 100 various elements main device.For example, Control circuit 200 is operated so that test signal injection circuit 204 is operated in test pattern or image capture mode.As another One example, control circuit 200 is operated and provides row control signal with to the first line control unit 206 and the second line control unit 208.As Another example, control circuit 200 provides sampling control signal to sample circuit 212.

Pel array 202 includes the multiple pixels 220 arranged with multiple rows 222 and multiple row 224_i,j.That is, picture Pixel array 202 includes M+1 rows 222, wherein first is expressed as row 222₀, and last is expressed as row 222_M.Similarly, as Pixel array 202 includes N+1 row 224, wherein first is expressed as row 224₀, and last is expressed as row 224_N.Pixel 220_i,j Each have unique address i, j, wherein i represents the row of address, and j represents the row of address.

Test signal injection circuit 204 include N+1 row injection circuit 226, its be connected to row 224 and with the phase of row 224 Same mode is represented.Therefore, first of row injection circuit 226 is expressed as row injection circuit 226₀, and last is expressed as Row injection circuit 226_N.When test signal injection circuit 204 receives control circuit 200 performs the order of the operation, row injection Circuit 226₀To 226_NEach operation be injected into pixel column 224 with by test signal₀To 224_NIn it is corresponding one row.Work as survey Trial signal injection circuit 204 is command by being all row injection circuits 226 when being operated in image capture mode₀To 226_NWill be identical Reference signal is injected into respective column 224₀To 224_NEach.

First line control unit 206 operates to produce by the row control signal instruction definition from the control output of circuit 200 Row control signal.Additionally, the first line control unit 206 is electrically coupled to each of row 222, produced by directly applying thereon Row control signal.Second line control unit 208 also operates to produce the mutually colleague's control signal by being exported from control circuit 200 Mutually colleague's control signal of instruction definition.Row controls different from the first line control unit 206, being produced by the second line control unit 208 Signal processed is not intended to drive row 222.On the contrary, it is used by the first comparison circuit 210, the first line control unit is passed through to check Whether 206 control signals for producing have passed over row 222 is suitably distributed.That is, the first comparison circuit 210 receives logical The control signal of the generation of the second line control unit 208 is crossed, then it is compared with the electricity condition of row 222.If the electricity of row 222 State does not correspond to the control signal produced by the second line control unit 208, then the output of the first comparison circuit 210 is represented by the The error signal that the control signal that one line control unit 206 is produced is not distributed suitably across one or more rows 222.

Sample circuit 212 operates the row sampling instruction from control circuit 200 with basis to perform sampling operation.Because each Individual row 222 is sequentially selected by the first line control unit 206, and sample circuit 212 obtains the number of the electricity condition for representing each row 224 Digital data.Therefore, each pixel 220 for pel array 202 is obtained_i,jNumerical data need the row per frame sampling N+1 Each of 224 M+1 times altogether.Sample circuit 212 obtains row sample each time, and it is just via data wire 228 by numerical data Output is to image processor 216 for further treatment.

Second comparison circuit 214 is received and referred to by controlling circuit 200 to provide to the identical row sampling of sample circuit 212 Order.The sampling is instructed and drives sample circuit 212 to be compared with actual control signal by the second comparison circuit 214.If the reality Border signal drives sample circuit 212 not correspond to sampling instruction, then the second comparison circuit output error signal.

Image processor 216 operates the digital number will be obtained by sample circuit 212 via known image treatment technology According to being converted to readable image data.

3rd comparison circuit 218 operate with will be injected into via test signal injection circuit 204 test signal of row 224 with The numerical data as obtained by sample circuit 212 is obtained is compared.If the digital number as obtained by sample circuit 212 is obtained According to inadequately corresponding to the test signal, then the output error signal of the 3rd comparison circuit 218.3rd comparison circuit 218 can be with Directly received from sample circuit 212 via image processor 216 and data wire 230 via data wire 228 or selection Numerical data.

Fig. 3 is and one group of row control signal wire 300_i, electric charge injection line 302_jAnd the pel array of read line 304j couplings 202 pixel 220_i,jSchematic diagram.Row control signal wire 300_iIncluding：Row select line 306_i, reset line 308_iAnd transmission line 310_i.Row control signal wire 300 can extend across full line 222_i, so that the first line control unit 206 can control identical to believe Number provide to row 222_iPixel 220_i,0To 220_i,N.Similarly, electric charge injection line 302_jWith read line 304_jCan be along permutation 224_jExtend.Electric charge injects line 302_jEnable test signal injection circuit 204 that test signal is injected into pixel 220_0,jExtremely 220_M,j.Read line 304_jEnable the sampled pixel 220 of sample circuit 212_0,jTo 220_M,jElectricity condition.

In this exemplary embodiment, pixel 220_i,jIt is four transistors（Four-transistor, 4T）Pixel, its bag Include：Optical sensor 312, charge storage region 314, pixel voltage source terminal（V_dd）316th, reset transistor 318, transmission transistor 320th, source following transistor 322, row selecting transistor 324 and coupled capacitor device 326.Optical sensor 312 is, for example, photoelectricity Diode（Photodiode, PD）, operate to convert incident light into charged particles.Charge storage region 314 is floating diffusion Element, operates to store the electric charge produced by optical sensor 312.Voltage is provided brilliant to resetting by pixel voltage source terminal 316 Body pipe 318 and source following transistor 322.Reset transistor 318 includes：The first terminal 328, coupled to pixel voltage source terminal 316；Second terminal 330, coupled to charge storage region 314；And gate pole 332, coupled to reset line 308_i.When the first row control Device processed 206 is via reset line 308_iMake reset signal（It is in the case high voltage pulse）It is applied to when on gate pole 332, crystal Pipe 318 is momentarily placed in conducting state, and wherein charge storage region 314 is coupled to pixel voltage source terminal 316.Therefore, electric charge is deposited The previous charge state in storage area domain 314 is back to known reference state of charge.Once reset line 308_iIt is back to low-voltage state, Reset transistor 318 is returned to nonconducting state, and wherein charge storage region 314 is electrically insulated with pixel voltage source terminal 316. Transmission transistor 320 includes：The first terminal 334, is coupled to optical sensor 312；Second terminal 336, is coupled to electric charge and deposits Storage area domain 314；And gate pole 338, coupled to transmission line 310_i.When the first line control unit 206 is via transmission line 310_iTransmission is believed Number（It is in the case high voltage）When being applied to gate pole 338, transmission transistor 320 is placed in conducting state, wherein optical sensor 312 are coupled to charge storage region 314.Therefore, the electric charge for being produced by optical sensor 312 is transferred to charge storage region 314.Once transmission line 310_iLow-voltage state is back to, transmission transistor 320 is returned to nonconducting state, wherein electric charge Storage region 314 is electrically insulated with optical sensor 312.Source following transistor 322 includes：The first terminal 340, coupled to pixel electricity Source terminal 316；Second terminal 342, coupled to row selection electric crystal 324；And gate pole 344, coupled to charge storage region 314.Those of ordinary skill in the art are by, it is realized that the electricity condition of Second terminal 342 will be referred to by the state of charge of gate pole 344 Show, and then indicated by the state of charge of charge storage region 314.Therefore, Second terminal 342 can be as pixel 220_i,jIt is defeated Go out terminal, it is operable to the electric signal that output represents the electric charge for being stored in charge storage region 314.Row selecting transistor 324 Including：The first terminal 346, coupled to the Second terminal 342 of source following transistor 322；Second terminal 348, coupled to reading Line 304_j；And third terminal 350, coupled to row select line 306_i.When the first line control unit 206 is by row selection signal（In this feelings It is high voltage under condition）It is applied to row select line 306_iWhen upper, row selecting transistor 324 is operated in the on-state, wherein first Terminal 346 and Second terminal 348 are electrically coupled to one another, so as to the signal exported from Second terminal 342 is applied into read line 304_j On.When row selection signal is not applied in row select line 306_iWhen upper, row selecting transistor 324 is operated in the on state, from And make pixel 220_i,jLead-out terminal not with read line 304_jConnection.Coupled capacitor device 326 includes：The first terminal 352, coupling To charge storage region 314；And Second terminal 354, inject line 302 coupled to electric charge_j.Coupled capacitor device 326 can pass through Control is applied to electric charge injection line 302_jOn voltage make test signal injection circuit 204（From Fig. 2）Control electric charge storage region The state of charge in domain 314.When imageing sensor 100 is operated in image capture mode, the voltage of electric charge injection line 302 keeps The known reference level to charge storage region 314 is transmitted in the electric charge produced by optical sensor 312.Due to electric charge note Enter line 302 and be maintained at fixed voltage, the quantity of the electric charge produced by optical sensor 312 in the given time be measured as come Transmitted to charge storage region 314 between the state of charge of charge storage region 314 from the electric charge of optical sensor 312 Difference.

When imageing sensor 100 is operated in test pattern, test signal injection circuit 204 is applied to electricity by change Lotus injects line 302（Therefore in the terminal 354 of capacitor 326）On voltage, and test signal is transmitted to pixel 220.Pass through Change the voltage level, the state of charge of charge storage region 314 is adjusted to simulate the value of known light intensity.If for example, The same reference voltage being applied to during image capture mode on electric charge injection line 302 is applied to electric charge note during test pattern Enter on line 302, then read line 304_jElectricity condition seem optical sensor 312 and generated lowest charge.Such as will Ground, sample circuit 212 are hereinafter explained in further detail（From Fig. 2）It is normal as it during image capture mode Ground sampling read line 304_j, and the 3rd comparison circuit 218 compares the data sample with the test signal injected and when it Output error signal when inconsistent.

In the exemplary embodiment of Fig. 3, test signal is injected into charge storage region 314.However, the test signal can To be optionally for example injected into optical sensor 312 via reset transistor 318 and transmission transistor 320.

Fig. 4 is the schematic diagram of the test signal injection circuit 204 according to one embodiment of the invention.Except row injection circuit 226₀ To 226_NOutside, test signal injection circuit 204 includes：Random bit generators 400, random order supply line 402, logic high voltage Supply line 404 and logic low-voltage supply line 406.Additionally, test signal injection circuit 204 is coupled to buffer clock signal line 408 and electric charge injection reseting signal line 410.Buffer clock signal line 408 is routed to test signal injection from control circuit 200 In circuit 204, clock signal is supplied to row injection circuit 226₀To 226_NAnd random bit generators 400.Buffer 420 Can be coupled between control circuit 200 and row injection circuit 204, to buffer and/or amplify the clock from control circuit 200 Signal.

Electric charge injection reset line 410 will reset from controlling circuit 200 to be routed in test signal injection circuit 204 Signal is supplied to row injection circuit 226₀To 226_N.Random bit generators 400 include input terminal 412 and lead-out terminal 414, point Ou Hezhi not buffer clock signal line 408 and random order supply line 402.In one embodiment, random bit generators 400 can be Linear feedback shift register（Linear Feedback Shift Register, LFSR）, it is operated to randomly generate Data bit be applied on random order supply line 402, with respond from buffer clock signal line 408 receive clock signal.Random order Supply line 402 is route is supplied to row injection circuit 226 with by random data bits₀To 226_N, and also inject electricity from test signal Road 204 routes to the 3rd comparison circuit 218（From Fig. 2）.High voltage supply line 404 and low-voltage supply line 406 route across Cross test signal injection circuit 204 to row injection circuit 226₀To 226_N。

Fig. 5 is row injection circuit 226_jWith adjacent column injection circuit 226_j-1Schematic diagram.Each row injection circuit 226_N To 226₀Including：Memory element 500, first switch circuit 502 and second switch circuit 504.In an illustrated embodiment, often One memory element 500 is flip-flop circuit, and there is the flip-flop circuit clock coupled to buffer clock signal line 408 to be input into Terminal 506, data bit input terminal 508 and data bit lead-out terminal 510.Memory element 500_N（It is not shown）Data bit it is defeated Enter terminal 508 coupled to random order supply line 402（From Fig. 4）.Except memory element 500_NOutside, subsequent memory element 500_N-1To 500₀Data bit input terminal 508 coupled to adjacent memory element 500 lead-out terminal 510.For example, storage unit Part 500_jData bit input terminal 508 be coupled to adjacent memory element 500_j+1Data bit lead-out terminal 510.Equally, store Element 500_j-1Data bit input terminal 508 be coupled to adjacent memory element 500_jData bit lead-out terminal 510.Therefore, deposit Storage element 500 is to be concatenated together forming single serial input（single serial-in）The trigger of shift register, Wherein data bit is serially moved into via random order supply line 402 from random bit generators 400.Those of ordinary skill in the art Will be, it is realized that when buffer clock signal line 408 is timed, it is defeated in data bit that random bit generators 400 apply new data bit Enter terminal 508_NOn, so as to memory element 500 will be previously stored in_NData bit transmit to memory element 500_N-1.Therefore, will be new The data bit of generation is loaded onto memory element 500₀Need to make N+1 clock signals be applied on buffer clock signal line 408.In figure In 5 exemplary embodiment, memory element 500 is trigger, and in other embodiments, memory element 500 can be pulsed Latch or random access memory（Random Access Memory, RAM）.

First switch circuit 502 includes：Control terminal 512, reseting signal line 410 is injected coupled to electric charge；First input Terminal 514, coupled to logic high voltage line 404；Second input terminal 516, coupled to second switch circuit 504；And output Terminal 518, line 302 is injected coupled to electric charge.Under the control of electric charge injection reseting signal line 410, first switch circuit 502 will Electric charge injection line 302 is selectively coupled to logic high voltage line 404 or second switch circuit 504.Second switch circuit 504 is wrapped Include：Control terminal 520, coupled to the input terminal 508 of memory element 500；First input end 522, coupled to logically high electricity Pressure supply line 404；Second input terminal 524, coupled to logic low-voltage supply line 406；And lead-out terminal 526, it is coupled to Second input terminal 516 of first switch circuit 502.Under the control of input terminal 508, second switch circuit 504 is by first Second input terminal 516 of switch 502 is selectively coupled to logic high voltage supply line 404 or logic low-voltage supply line 406。

Fig. 6 is to show pel array 202, the first line control unit 206, the second line control unit 208 and the first comparison circuit The circuit diagram of 210 feature.First line control unit 206 is coupled to receive defeated from control circuit 200 with the second line control unit 208 The row control instruction of the data bit form for going out.In an illustrated embodiment, from the row control instruction bag of the control output of circuit 200 Include：Row address is instructed, for controlling row select line 306₀To 306_M；Reset line control instruction, for controlling reset line 308₀Extremely 308_M；And transmission line control instruction, for controlling transmission line 310₀To 310_M.Row address instruction is the form of data bit, its table Show row select line 306₀To 306_MWhich will be applied in.Row select line 306₀To 306_MEach include：First end 600 With the second end 602, the first line control unit 206 and the first comparison circuit 210 are coupled respectively to.Reset line 308₀To 308_MIt is each It is individual also to include：The end 606 of first end 604 and second, is coupled respectively to the first line control unit 206 and the first comparison circuit 210.Transmission Line 310₀To 310_MEach also include：The end 610 of first end 608 and second, is coupled respectively to the first line control unit 206 and One comparison circuit 210.

First line control unit 206 includes main row decoder 612 and line driver 614.Main row decoder 612 includes input Terminal 616, is coupled to receive the row control signal instruction from control circuit 200.Line driver 614 is decoded coupled to main row Device 612 and it is operable to that row selection signal is applied into choosing of being expert at according to the row control instruction that is decoded by main row decoder 612 Select line 306₀To 306_MAbove, reset signal is applied to reset line 308₀To 308_MAbove and transmission signal is applied to transmission line 310₀To 310_MOn.Line driver 614 includes multiple lead-out terminals 618₀To 618_M、620₀To 620_MAnd 622₀To 622_M.Output Terminal 618₀To 618_MIt is operable to output and corresponding row select line 306₀To 306_MRelated row selection signal.First end 600₀Extremely 600_MIt is coupled respectively to lead-out terminal 618₀To 618_M.Lead-out terminal 620₀To 620_MIt is operable to output and corresponding reset line 308₀ To 308_MRelated reset signal.First end 604₀To 604_MIt is coupled respectively to lead-out terminal 620₀To 620_M.Lead-out terminal 622₀ To 622_MIt is operable to output and corresponding transmission line 310₀To 310_MRelated transmission signal.First end 608₀To 608_MCouple respectively To lead-out terminal 622₀To 622_M。

Second line control unit 208 includes secondary row decoder 624, and the secondary row decoder 624 includes input terminal 626.Second Line control unit 208 further includes multiple lead-out terminals 628₀To 628_M、630₀To 630_MAnd 632₀To 632_M, it is referred to as respectively Lead-out terminal 628,630 and 632.The input terminal 626 of secondary row decoder 624 is coupled to be received by controlling circuit 200 Instructed to the identical row control signal of main row decoder 612 is input into offer.Therefore, main row decoder 612 and secondary row decoder 624 decode the instruction of identical row control signal simultaneously, so that lead-out terminal 628₀To 628_MLogic state and corresponding output terminals 618₀To 618_MLogic state matching, make lead-out terminal 630₀To 630_MLogic state and corresponding output terminals 620₀To 620_M Logic state matching, and make lead-out terminal 632₀To 632_MLogic state and corresponding output terminals 622₀To 622_MPatrol The state of collecting matching.For example, working as lead-out terminal 618₀When being changed into high-voltage state from low-voltage state, lead-out terminal 628₀Also in reality The border identical time is changed into high-voltage state from low-voltage state.

First comparison circuit 210 is operable to row control signal wire 300₀To 300_MElectricity condition with from secondary row decoder The control signal of 624 outputs is compared, wherein row control signal wire 300₀To 300_MIncluding row select line 306₀To 306_M, it is multiple Bit line 308₀To 308_MAnd transmission line 310₀To 310_M.If given row（Such as row select line 306₀）Particular row control signal Logic state not with lead-out terminal 628₀Logic state it is consistent, then the first comparison circuit 210 is defeated from error signal output line 634 Error error signal.

First comparison circuit 210 includes multiple first input ends, and these first input ends include input terminal 636₀ To 636_M、638₀To 638_MAnd 640₀To 640_M.Input terminal 636₀To 636_MIt is electrically coupled to corresponding output terminals 628₀Extremely 628_M, input terminal 638₀To 638_MIt is electrically coupled to corresponding output terminals 630₀To 630_MAnd input terminal 640₀To 640_MElectricity Coupled to corresponding output terminals 632₀To 632_M.First comparison circuit 210 further includes multiple second input terminals, and these Two input terminals include input terminal 642₀To 642_M、644₀To 644_MAnd 646₀To 646_M.Input terminal 642₀To 642_MThermocouple It is bonded to corresponding row select line 306₀To 306_MCorresponding second end 602₀To 602_M.Equally, input terminal 644₀To 644_MIt is electrically coupled To corresponding reset line 308₀To 308_MCorresponding second end 606₀To 606_M.Finally, input terminal 646₀To 646_MIt is electrically coupled to phase Answer transmission line 310₀To 310_MCorresponding second end 610₀To 61O_M。

During operation, the first comparison circuit 210 determines input terminal 636₀To 636_MLogic state and respective input Son 642₀To 642_MLogic state whether have predetermined corresponding relation, determine input terminal 638₀To 638_MLogic state With respective input 644₀To 644_MLogic state whether correspond to, and determine input terminal 640₀To 640_MLogic shape State and respective input 646₀To 646_MLogic state whether correspond to.If it is not, the wrong output of output line 634 represents figure As the error signal that sensor 100 breaks down.

In control signal wire 300₀To 300_MIn the case that one of them is damaged, the row control on line driver 614 is applied to Signal may inadequately be distributed in all pixels in associated row.Emphasis is it will be understood that via the He of main row decoder 612 Secondary row decoder 624 decodes each group of row control signal instruction simultaneously, then compares lead-out terminal 628,630,632 and believes with control The electricity condition at corresponding second end 602,606,610 of number line 300, it is ensured that carry out the row control signal of row driver 614 suitably It is distributed across row control signal wire 300.On the contrary, imageing sensor of the prior art usually not detects such failure Mode, therefore it more likely exports inaccurate view data to host apparatus.

Fig. 7 is the circuit diagram of the feature for showing the first comparison circuit 210 according to an exemplary embodiment of the present invention.First ratio Include multiple comparison circuits and error signal line 706 compared with circuit 210.In an illustrated embodiment, the comparison circuit can be wrapped Include XOR gate.In other embodiments of the invention, it is possible to use other gates, such as NAND or NOR-gate.If each compares Do not have predetermined relationship compared with two inputs of circuit（For example, matching）, then by output error signal.

In an illustrated embodiment, each group of the comparison circuit includes comparison circuit 700₀To 700_M, comparison circuit 702₀Extremely 702_MAnd comparison circuit 704₀To 704_M.Comparison circuit 700₀To 700_MEach include：Related first input end 708th, the second input terminal 710 and lead-out terminal 712.As illustrated, each comparison circuit 700 and each relevant group First input end 708, the second input terminal 710 and lead-out terminal 712 uniquely represent with the subscript being similar to.For example, Comparison circuit 700₁₀（It is not shown）Including first input end 708₁₀, the second input terminal 710₁₀And lead-out terminal 712₁₀。 First input end 708₀To 708_MIt is electrically coupled to input terminal 636₀To 636_M.Second input terminal 710₀To 710_MRespectively It is electrically coupled to input terminal 642₀To 642_M.All lead-out terminals 712₀To 712_MIt is electrically coupled to error signal line 706.Compare electric Road 702₀To 702_MEach include：Related first input end 714, the second input terminal 716 and lead-out terminal 718.

First input end 714₀To 714_MIt is electrically coupled to input terminal 638₀To 638_M.Second input terminal 716₀Extremely 716_MIt is electrically coupled to input terminal 644₀To 644_M.All lead-out terminals 718₀To 718_MIt is electrically coupled to error signal line 706. Comparison circuit 704₀To 704_MEach include：Related first input end 720, the second input terminal 722 and output end Son 724.First input end 720₀To 720_MIt is electrically coupled to input terminal 640₀To 640_M.Second input terminal 722₀Extremely 722_MIt is electrically coupled to input terminal 646₀To 646_M.All lead-out terminals 724₀To 724_MIt is electrically coupled to error signal line 706.Should , it is realized that when the first and second input terminals of related comparison circuit are not to correspondence the related lead-out terminal will export with The error signal of the form of logic High voltage state.Because the error signal line 706 is connected to all lead-out terminals 712₀Extremely 712_M, lead-out terminal 718₀To 718_MAnd lead-out terminal 724₀To 724_MIf one or more has logic high voltage shape State, then output error signal.In other embodiments of the invention, each group of comparison circuit is coupled to the phase of itself Answer error signal line.For example, the first comparison circuit 210 can include three error signal lines, one of error signal line coupling It is bonded to one group of all lead-out terminal of comparison circuit, comparison circuit 700₀To 700_MLead-out terminal be coupled to the first mistake Holding wire, and comparison circuit 702₀To 702_MAnd comparison circuit 704₀To 704_MSecond and the 3rd mistake can be coupled respectively to Holding wire.In another embodiment of the present invention, a subset of comparison circuit is coupled to the corresponding mistake letter of itself Number line.For example, comparison circuit 700₀To 700_j, comparison circuit 702₀To 702_jAnd comparison circuit 704₀To 704_jLead-out terminal The first error signal line is coupled to, and the lead-out terminal of remaining comparison circuit is coupled to the second error signal line. In one more embodiment of the present invention, of each group of comparison circuit is coupled to the corresponding error signal of itself in collection Line.For example, comparison circuit 700₀To 700_MLead-out terminal be coupled to the first error signal line, and comparison circuit 702_M+1Extremely 702_jLead-out terminal be coupled to the second error signal line.Similarly, the three, the four, the 5th and the 6th error signal line can With coupled to comparison circuit 704₀To 704_M, comparison circuit 704_M+1To 704_j, comparison circuit 706₀To 706_MAnd comparison circuit 706_M+1To 706_jLead-out terminal.

Fig. 8 is to show control circuit 200, pel array 202, the circuit of the comparison circuit 214 of sample circuit 212 and second Figure.Sample circuit 212 obtains the read line 304 from pel array 202₀To 304_NPixel samples, and according to from control circuit The control signal operation of 200 outputs.Therefore, sample circuit 212 is coupled to receive the control signal from control circuit 200. Second comparison circuit 214 is coupled to sample circuit 212 and controls circuit 200 and is operable to when from sample circuit 212 When control signal does not correspond to the control signal of control circuit 200 output certainly, output error signal.

Sample circuit 212 includes：Control signal regulation circuit 800, the first control signal wire 802, the second control signal wire 804th, the 3rd control signal wire 806 and multiple pixel reading circuits 808₀To 808_N。

Control signal regulation circuit 800 is operated to be applied at it from the control signal of the control output of circuit 200 It was conditioned before on first control signal wire 802, the second control signal wire 804, the 3rd control signal wire 806.Control signal is adjusted Economize on electricity road 800 includes：First input end 810, the second input terminal 812, the 3rd input terminal 814, level shift（level shift）Circuit 816, the first buffer circuit 818, the second buffer circuit 820, the 3rd buffer circuit 822, first lead-out terminal 824th, the second lead-out terminal 826 and the 3rd lead-out terminal 828.First input end 810 is coupled to receive from control circuit The amplifier control signal of 200 outputs.Second input terminal 812 is coupled to receive the simulation-number from the control output of circuit 200 Word converter control signal.3rd input terminal 814 is coupled to receive the storage circuit control letter from the control output of circuit 200 Number.Level displacement circuit 816 coupled to first input end 810, the second input terminal 812 and the 3rd input terminal 814 with The control signal that level shift is applied thereto by control circuit 200.First buffer circuit 818 is operable to by level position Buffering is applied to the amplifier control signal on first input end 810 after the level of the displacement of shift circuit 816.By first After buffer circuit 818 is buffered, amplifier control signal is applied on control signal wire 802 from first lead-out terminal 824.The Two buffer circuits 820 are operable to the buffering after by the level of the displacement of level displacement circuit 816 and are applied to the second input Analogue-to-digital converters control signal on son 812.After being buffered by buffer circuit 820, the analogue-to-digital converters Control signal is applied on control signal wire 804 from lead-out terminal 826.3rd buffer circuit 822 is operable to by electricity Buffering is applied to the storage circuit control signal on the 3rd input terminal 814 after the level of the displacement of prosposition shift circuit 816.Logical Cross after the buffering of buffer circuit 822, the storage circuit control signal is applied on control signal wire 806 from lead-out terminal 828.

Control signal wire 802 includes the end 832 of first end 830 and second, and control signal wire 804 includes first end 834 and the Two ends 836, and control signal wire 806 includes the end 840 of first end 838 and second.Control signal wire 802 is amplifier control signal Line, is operable to for amplifier control signal to be supplied to pixel reading circuit 808₀To 808_N.The first end of control signal wire 802 830 and second end 832 be coupled respectively to control signal adjust circuit 800 the comparison circuit 214 of lead-out terminal 824 and second.Control Holding wire processed 804 is analogue-to-digital converters control signal wire, is operable to supply analogue-to-digital converters control signal To pixel reading circuit 808₀To 808_N.The end 836 of first end 834 and second of control signal wire 804 is coupled respectively to control signal Adjust the comparison circuit 214 of lead-out terminal 826 and second of circuit 800.Control signal wire 806 is storage circuit control signal wire, It is operable to for storage circuit control signal to be supplied to pixel reading circuit 808₀To 808_N.The first end of control signal wire 806 838 and second end 840 be coupled respectively to control signal adjust circuit 800 the comparison circuit 214 of lead-out terminal 828 and second.

Pixel reading circuit 808₀To 808_NEach be operable to obtain and represent corresponding read line 304₀To 304_NElectricity The numerical data of state.For example, pixel reading circuit 808_N-1It is operable to obtain and represents read line 304_N-1Electricity condition number Digital data.Pixel reading circuit 808₀To 808_NEach include：Capacitor 842, amplifier 844, analogue-to-digital converters 846 and storage circuit 848.Capacitor 842₀To 842_NEach include the first terminal 850 and Second terminal 852, respectively coupling It is bonded to corresponding read line 304 and amplifier 844.Amplifier 844₀To 844_NEach be operable to amplify corresponding Second terminal 852₀To 852_NElectricity condition.Amplifier 844₀To 844_NEach be coupled to control signal wire 802, and according to from control The amplification control signal of the output of lead-out terminal 824 of circuit for signal conditioning 800（For example, gain control signal）Operation.

Analogue-to-digital converters 846₀To 846_NCoupled to respective amplifier 844₀To 844_NAnd it is operable to digitlization From the amplification signal that it is exported.For example, analogue-to-digital converters 846_NProduce and represent from amplifier 844_NThe amplification voltage of output Binary data word（binary data word）.Analogue-to-digital converters 846₀To 846_NEach coupled to control believe Number line 804 and the analog to digital control signal exported according to the second lead-out terminal 826 from control circuit for signal conditioning 800 Operation.Storage circuit 848₀To 848_NIt is coupled respectively to analogue-to-digital converters 846₀To 846_NAnd it is operable to store from it The binary data word of generation.Storage circuit 848₀To 848_NCoupled to control signal wire 806, therefore adjusted according to from control signal The storage circuit control signal operation that the 3rd lead-out terminal 828 on road 800 that economizes on electricity is exported.Those of ordinary skill in the art will anticipate Know, by reading circuit 808₀To 808_NThe quantity of the data bit of acquisition, the resolution of binary data word will be depending on specific Using.Therefore, resolution（For example, 8 words（8-bit word））It is not an importance of the invention, therefore does not need office It is limited to the data bit of any specific quantity or the analogue-to-digital converters of any particular type（Such as continuous approximation （successive approximate）Register or slope（ramp）Analogue-to-digital converters）.

Second comparison circuit 214 includes：First input end 854, the second input terminal 856, the 3rd input terminal 858, 4th input terminal 860, the 5th input terminal 862, the 6th input terminal 864.First input end 854 be coupled to receive to The identical amplifier control signal that the first input end 810 of control signal regulation circuit is provided.In an illustrated embodiment, The first input end 810 of first input end 854 and control signal the regulation circuit 800 of the second comparison circuit 214 is via biography Defeated line 866 is connected and is therefore coupled to same node point.Second input terminal 856 be coupled to receive from control circuit 200 to Identical simulation-digital controlled signal that second input terminal 812 of control signal regulation circuit 800 is provided.In shown implementation In example, the second input terminal 812 of the second input terminal 856 and control signal the regulation circuit 800 of the second comparison circuit 214 is passed through Connected by transmission line 868 and be therefore coupled to same node point.3rd input terminal 858 is coupled to receive from control circuit The 200 identical storage circuit control signals provided to the 3rd input terminal 814 of control signal regulation circuit 800.Exemplary In embodiment, the 3rd input terminal 858 and control signal of the second comparison circuit 214 adjust the 3rd input terminal of circuit 800 814 connect via transmission line 870 and are therefore coupled to same node point.

Second end 832 of 4th input terminal 860 coupled to control signal wire 802.5th input terminal 862 is coupled to control Second end 836 of holding wire processed 804.Second end 840 of 6th input terminal 864 coupled to control signal wire 806.In the operation phase Between, the second comparison circuit 214 is respectively by first input end 854, the second input terminal 856 and the 3rd input terminal 858 Electricity condition is compared with the electricity condition of the 4th input terminal 860, the 5th input terminal 862 and the 6th input terminal 864.Such as It is defeated that the electricity condition of fruit first input end 854, the second input terminal 856 and the 3rd input terminal 858 does not correspond to the corresponding 4th Enter the electricity condition of terminal 860, the 5th input terminal 862 and the 6th input terminal 864, then comparison circuit output error signal.

Fig. 9 is the circuit diagram of the additional detail for showing the second comparison circuit 214 according to an embodiment of the invention.Second ratio Include multiple gates and error signal lead-out terminal 908 compared with circuit 214.In an illustrated embodiment, the second comparison circuit 214 Including multiple XOR gates and OR.In other embodiments of the invention, it is possible to use other gates, such as XNOR or NOR Door.Using OR, if any one of these input terminals is in logically high, output will be logically high.

Second comparison circuit 214 includes：First XOR gate 900, the second XOR gate 902, the 3rd XOR gate 904, OR 906 with And error signal lead-out terminal 908.First XOR gate 900 includes first input end 910, the second input terminal 912 and output Terminal 914.The input terminal 912 of first input end 910 and second of the first XOR gate 900 is coupled respectively to first input end 854 and the 4th input terminal 860.Therefore, when the input terminal 912 of first input end 910 and second be it is logically high or equal During for logic low, the logic state of lead-out terminal 914 is low, therefore represents the amplifier control letter being applied on control line 802 Number suitably it is distributed in all amplifiers 844₀To 844_N.If adjusting the first input end 810 of circuit 800 to control signal The control signal of offer is inadequately distributed across the input terminal 860 of control line 802 to the 4th, then input terminal 910 will not have Have with the identical logical value of the second input terminal 912 so that lead-out terminal 914 have high logic state.

Second XOR gate 902 includes first input end 916, the second input terminal 918 and lead-out terminal 920.Second The input terminal 918 of first input end 916 and second of XOR gate 902 is coupled respectively to the second input terminal 856 and the 5th input Terminal 862.When the input terminal 918 of first input end 916 and second is logically high or when being logic low, lead-out terminal 920 logic state is low, so as to represent that the analogue-to-digital converters control signal being applied on control line 804 is suitably divided Cloth is to all analogue-to-digital converters 846₀To 846_N.If carried to the second input terminal 812 of control signal regulation circuit 800 The control signal of confession is inadequately distributed across the input terminal 862 of control line 804 to the 5th, then the second input terminal 918 and One input terminal 916 will be mismatched, so that lead-out terminal 920 has high logic state.

3rd XOR gate 904 includes：First input end 922, the second input terminal 924 and lead-out terminal 926.3rd The input terminal 924 of first input end 922 and second of XOR gate 904 is coupled respectively to the 3rd input terminal 858 and the 6th input Terminal 864.When 922 and second input terminal of first input end 924 is matched, the logic state of lead-out terminal 926 be it is low, from And represent that the storage circuit control signal being applied on control line 806 is suitably distributed and obtain all storage circuits 848₀To 848_N。 If inadequately crossing over control line 806 to the control signal that the 3rd input terminal 814 of control signal regulation circuit 800 is provided It is distributed to the 6th input terminal 864, then the second input terminal 924 and first input end 922 will be mismatched, so that output end Son 926 has high logic state.

Include for OR 906：First input end 928, the second input terminal 930, the 3rd input terminal 932 and output end Son 908.First input end 928, the second input terminal 930 and the 3rd input terminal 932 are collected be bonded to lead-out terminal respectively 914、920、926.When the logic state of lead-out terminal 914,920,926 is low, the logic state of lead-out terminal 908 will be It is low.If the logic state of one or more of lead-out terminal 914,920,926 is height, lead-out terminal 908 will be patrolled with height The state of collecting, it represents that some type of failure is already present in sample circuit 212.

In an illustrated embodiment, XOR gate is used.In other embodiments of the invention, it is possible to use other gates, Such as NAND gate or NOR-gate.Using XOR gate, if two inputs are mismatched, will export logically high.

Figure 10 is the 3rd comparison circuit 218 according to one embodiment of the invention（Fig. 2）Circuit diagram.Work as imageing sensor 100 in test pattern when operating, and the 3rd comparison circuit 218 will be by random bit generators 400 via random order supply line 402 The test signal of offer（It also should be by row injection circuit 226₀To 226_NThere is provided to pixel 202 and then by electricity of sampling Sampled from pixel 202 on road 212）It is compared with by the actual numerical data for obtaining of sample circuit 212.In acquired data In the case of not matched with test data, the 3rd comparison circuit 218 is from the output error signal of error signal lead-out terminal 1000. In shown embodiment, the 3rd comparison circuit 218 includes：First verification and（checksum）Circuit 1002, threshold circuit 1004, Second verification and circuit 1006 and comparator 1008.

First verification and circuit 1002 include：Clock input terminal 1010, data bit input terminal 1012 and output end Son 1014.Clock input terminal 1010 and data bit input terminal 1012 are coupled respectively to buffer clock signal line 408 and random Position supply line 402.Buffer 420 is coupled between control circuit 200 and buffer clock signal line 408, to buffer and/or amplify Clock signal from control circuit 200.The clock enabling signal being applied on buffer clock signal line 408 first is verified and circuit 1002 sequentially, is read by random bit generators 400 via input terminal 1012（With reference to Fig. 4）It is sequentially applied to random order confession Answer the data bit for randomly generating on line 402.Because the position for randomly generating is sequentially received by the first verification and circuit 1002, institute Calculated with the first verification and circuit 1002 and exported to the checksum value of comparator 1008 by lead-out terminal 1014.

Threshold circuit 1004 includes：Clock input terminal 1016, DATA IN terminal 1018 and lead-out terminal 1020.When Clock input terminal 1016 is coupled to second clock holding wire 1022, to receive the clock signal from control circuit 200.Data are defeated Enter terminal 1018 coupled to data wire 228 to receive the pixel data obtained by sample circuit 212.The pixel data is processed And provided to terminal 1018 from image processor 216 in the form of binary data word via data wire 228, each word table Show the state of charge of specific pixel.Or, the pixel data can be direct from sample circuit 212 in the form of binary data word Ground is supplied to DATA IN terminal 1018.When data word is downloaded to threshold circuit 1004, export single from terminal 1020 Data bit.If the binary value of the data word received via DATA IN terminal 1018 is less than predetermined threshold, threshold value electricity Road 1004 exports binary zero from lead-out terminal 1020.If the two of the data word received via DATA IN terminal 1018 Hex value is more than or equal to predetermined threshold, then threshold circuit 1004 exports binary one from lead-out terminal 1020.Therefore, whenever Clock cable 1022 is circulated（cycle）When, threshold circuit 1004 receives another data word, and exports corresponding another Data bit.

Second verification and circuit 1006 include：Clock input terminal 1026, data bit input terminal 1028 and output end Son 1030.The clock input terminal 1026 and data bit input terminal 1028 of the second verification and circuit 1006 are coupled respectively to threshold value The second clock holding wire 1022 and lead-out terminal 1020 of circuit 1004.Therefore, when clock cable 1022 is circulated, second Verification and circuit 1006 are received from another data bit of the output of threshold circuit 1004.Because by input terminal 1028 sequentially The position that reception is randomly generated, so the first verification and circuit 1006 are calculated and exported to comparator 1008 by lead-out terminal 1030 Checksum value.

Comparator 1008 includes：First input end 1032, the second input terminal 1034 and lead-out terminal 1036.First The input terminal 1034 of input terminal 1032 and second is coupled to be received from respectively the binary system of the output of lead-out terminal 1014,1030 Checksum value.The lead-out terminal 1036 of comparator 1008 is coupled to error signal lead-out terminal 1000.If by the second input The checksum value that terminal 1034 is received is not equal to the checksum value received by first input end 1032, then lead-out terminal 1036 applying error signals are on error signal lead-out terminal 1000.Can for each row or whole frame calculate verification and, but It is the advantage of the recognizable specific fault row of verification offer of every a line.

Figure 11 is the exemplary timing diagram 1100 of the operation for illustrating imageing sensor 100 in image capture mode.Below Example describe the row 222 when imageing sensor 100 is operated in image capture mode_iControl and sampling.Additionally, this shows Example is illustrated in response to row 222_iControl, pixel 220_i,jVarious elements electricity condition.Although only describing in this example Row 222_iOperation, but sequentially control in the same manner and all rows 222 of sampling₀To 222_M.Also will be referring to figs. 2 to Figure 10 The operation of imageing sensor 100 is described.

Obtaining row 222_i-1View data after, it is following to obtain row 222_iView data.First, circuit 200 is controlled Export one group of row control instruction（For example, the row address of row i）To the first line control unit 206 and the second line control unit 208.In response to Row control instruction, line control unit 206 applies row selection signal 1102 in row select line 306_iOn, so that pixel 220_i,0Extremely 220_i,NRow selecting transistor 324 operate in the on-state.One and such as pixel 220_i,jRow selecting transistor 324 be in Conducting state, then related read line 304_jVoltage status 1104 corresponding to electric charge store（FD）Region 314_i,jElectric charge shape State 1106.

In the present example embodiment, voltage supply line 404 provides reference voltage（Vhi）1110, wherein working as image sensing When device 100 is operated in image capture mode, injection line 302 is kept₀To 302_NIn reference voltage.Electric charge injects reseting signal line 410 high-voltage state makes on-off circuit 502₀To 502_N（Fig. 5）Each coupling high-voltage supply line 404 to corresponding one Electric charge injects line 302.Therefore, all injection lines 302₀To 302_N（That is, to all injection lines of pixel 220 in row i）Coupling is paramount Voltage supply line 404.

When reset signal 1108 is applied on electric charge injection reseting signal line 410, pixel reset signal 1112 is applied to Reset line 308_iOn, so as to order about pixel 220_i,0To 220_i,NEach related reset transistor 318.As it was previously stated, driving Make transistor 318 couple associated charge to store（FD）Region 314 and voltage source terminal 316（Vdd）.Reset signal 1112 keeps applying It is added in reset line 308_iA upper predetermined lasting time, so that it allows appointing in charge storage region 314 prior cumulative enough Meaning electric charge is back to known reset state.

In runback bit line 308_iRemoval（For example, step-down）After reset signal 1112, sample circuit 212 is obtained from reading simultaneously Line taking 304₀To 304_NThe voltage sample of each.The SHR1 being represented by dashed line（Samp1e-Hald-Reset1, sampling keeps Reset 1）Represent the timing for obtaining first voltage sample.After SHR1 soon, transmission signal 1114 is applied to transmission line 310_i On, so as to order about pixel 220_i,0To 220_i,NEach related transmission transistor 320.Ordering about transmission transistor 320 causes It is electrically coupled, therefore, electric charge is transmitted to electric charge storage from optical sensor 312（FD）Region 314.As illustrated, making transmission for example, working as Signal 1114 is applied to transmission line 310_iWhen upper, optical sensor 312_i,jInitial low state of charge 1116 and charge storage region 314_i,jState of charge initial high 1106 respectively simultaneously increase and reduce.Transmission signal 1114 remains applied to transmission line 310_i A upper predetermined lasting time, so that it is allowed by optical sensor 312 enough_i,jAny electric charge for producing is transmitted to electric charge storage Region 314_i,j.From transmission line 310_iAfter removal transmission signal 114, sample circuit 212 is obtained and comes from read line 304 simultaneously₀ To 304_NThe second voltage sample of each.The SHS1 being represented by dashed line（Sample-Hald-Signal1, sampling keeps letter Number 1）Represent the timing for obtaining second voltage sample.Finally, from row select line 306_iRemoval row selection signal 1102, and to row 222_i+1Repeat said process.

Figure 12 is the timing diagram 1200 for illustrating the example that imageing sensor 100 is operated in test pattern.Especially, timing Figure 120 0 shows image capture process（Before SHS1）Test process is then shown（After SHS1）.Following description is explained Row 222_iControl and sampling, and in response to row 222_iControl pixels illustrated 220_i,jVarious elements electricity condition.Although Row 222 is only described in this example_iOperation, but sequentially control in a similar manner and all rows 222 of sampling₀To 222_M. Following description is carried out referring to figs. 2 to Figure 10.

In order to make great efforts to pass on new feature of the invention, imageing sensor 100 to be described as that only there are 24 in a simple manner decoupled Pixel column.However, those of ordinary skill in the art will be it is obvious that in typical applications, imageing sensor 100 will likely With substantial large number of pixel column.However, the present invention can be practiced as pixel column with any practical quantity and/or The imageing sensor 100 of row.

First, control circuit 200 starts to apply the clock signal 1202 of a sequence on clock cable 408.In clock Loop number in signal 1202 is equal to the quantity of the pixel column 224 of imageing sensor 100.Because this particular example describes image Sensor 100 has 24 pixel columns 224, so there is 24 circulations in the clock signal 1202 of shown part.In clock letter At numbers 1202 each falling edge, random bit generators 400 make the position for newly randomly generating be applied on random bit line 402.Cause This, random bit generators 400 make 24 positions for randomly generating of a sequence be applied on random bit line 402.Whenever new random product Raw position is applied to when on random bit line 402, is previously stored in memory element 500_j+1DATA IN terminal 508 at position quilt Transmit to memory element 500_jDATA IN terminal 508.Therefore, 24 bit sequences 1204 are moved to 24 memory elements 500₀ To 500₂₃（Two memory elements 500 are only shown）.With the 1st beginning, with the 24th end, 24 sequences for showing in this example Row 1204 are 110100101011000101010111.

Memory element 500 is moved in first position of bit sequence 1204_jAfterwards, row selection signal 1102 is applied to Row selection signal line 306_iOn, so as to connect pixel 220_i,0To 220_i,23Charge storage region 314 to corresponding read line 304₀ To 304₂₃.Row select line 306 is applied in row selection signal 1102_iAfter upper soon, reset signal 1108 is applied in test On the electric charge injection reseting signal line 410 of injection circuit 204.Electric charge injects the logic high voltage shape of reseting signal line 410 State makes first switch circuit 502₀To 502₂₃Each difference coupled output 518₀To 518₂₃With first input end 514₀To 514₂₃.Therefore, electric charge injection line 302₀To 302₂₃It is all coupled to high voltage supply line 404.In the quilt of reset signal 1108 It is applied to when on electric charge injection reseting signal line 410, pixel reset signal 1112 is applied in reset line 308_iOn, so that electric Lotus storage region 314_i,0To 314_i；23Coupled in pixel 220_i,0To 220_i,23In each related in voltage source terminal 316.In charge storage region 314_i,0To 314_i,23Each be back to after known reset charge state, runback bit line 308_i Removal（Step-down）Reset signal 1112.

In runback bit line 308_iAfter removal reset signal 1112, sample circuit 212 is obtained and comes from read line 304 simultaneously₀Extremely 304₂₃The voltage sample of each.When in image capture mode, first voltage sample is obtained at SHR1（Resetting voltage Sample）.After SHR1 soon, transmission signal 1114 is applied in transmission line 310_iOn, so that respectively from optical sensor 312_i,0 To 312_i,23Transmit electric charge to charge storage region 314_i,0To 314_i,23.Then, from transmission line 310_iRemoval（Step-down）Transmission letter Numbers 1114, and sample circuit 212 obtains and comes from read line 304 simultaneously at SHS1₀To 304₂₃The second voltage of each Sample（Picture signal）.This completes image capture process.

After SHS1 soon, reset signal 1112 is applied in reset line 308 again_iOn, so that reset charge is stored Region 314_i,0To 314_i,NState of charge 1106.In runback bit line 308_iAfter the removal time of reset signal 1,112 second, adopt Sample circuit 212 is obtained and comes from read line 304 simultaneously at SHR2₀To 304₂₃The tertiary voltage sample of each.SHR2 it Afterwards, self charge injection reseting signal line 410 removal reset signal 1108, so that first switch circuit 502₀To 502_NIt is electric respectively Couple the second input terminal 516₀To 516_NWith lead-out terminal 518₀To 518_N.Therefore, used in corresponding controling end 520₀To 520_N It is upper that any one Logic state instruction of effective bit sequence 1204 each test signal injection line 302 occurs₀To 302_N's Voltage 1110.For example, work as being applied to memory element 500_jData bit input terminal 508_jOn the position of bit sequence 1204 be by chance When " 0 ", row injection circuit 226_jSecond switch circuit 504_jIt is electrically coupled terminal 526_jWith 522_j.Coupling terminal 526_jWith 522_jMake Injection line 302_jIndirectly by on-off circuit 502_jWith 504_jCoupled to logic high voltage supply line 404.On the other hand, when It is applied to memory element 500_jData bit input terminal 508_jOn bit sequence 1204 position by chance be " 1 " when, row injection circuit 226_jSecond switch circuit 504_jCoupling terminal 526_jWith 524_j.As coupling terminal 526_jWith 524_jResult, inject line 302_jIndirectly by first switch circuit 502_jWith 504_jCoupled to logic low-voltage line 406.However, in the particular example, Storage is in terminal 508_jIn the 24th of bit sequence 1204 be " 1 " so that when the self charge injection removal of reseting signal line 410 is multiple During the signal 1108 of position, make injection line 302_jVoltage 1110 drop to the logic low-voltage of low-voltage supply line 406.Certainly, such as The 24th of fruit bit sequence 1204 be " 0 " rather than " 1 " when, when self charge injection reseting signal line 410 removal reset signal When 1108, line 302 is injected_jVoltage 1110 will remain in the level of logic high voltage line 404.

It is different when being operated in image capture mode from imageing sensor 100, when imageing sensor 100 is in test pattern During operation, the second transmission signal 1114 is not applied to transmission line 310 after SHR2_jOn.Really, it is not by incident intensity （That is, it is not by optical sensor 312_i,0To 312_i,NThe photogenerated charge of accumulation）Indicate pixel 220_i,0To 220_i,23Electric charge shape State.On the contrary, respectively by injecting line 302₀To 302_jVoltage status indicate pixel 220_i,0To 220_i,23State of charge.Cause It is injection line 302₀To 302_jEach can have two possible voltage status（Vhi or Vlo）In one of only, so From corresponding read line 304 during SHR2₀To 304_jEach of the voltage sample of acquisition can have two probable values in only One of.In fact, sample circuit 212 is by will be from optical sensor 312_i,0To 312_i,NPhotogenerated charge transmit to corresponding electric charge Storage region 314_i,0To 314_i,NThe step of replace with the test signal that will be randomly generated and be injected into charge storage region 314_i,0Extremely 314_i,NThe step of pixel 220 is injected into sample_i,0To 220_i,NSimulation pixel data.

It is unnecessary that a test process is connect after each image capture process.Implement test process（Injection letter Number sampling）Frequency depend on must be with speed detection sensor failure how soon.Generally, can be with per N number of image capture process A test process is connect, wherein N is the integer more than 0.Or, during each frame time（That is, pel array 202 is completed In per a line 222 image capture process time）Can be with the only one subset of test pixel row 222.

Figure 13 is the circuit diagram of the first comparison circuit 210 according to alternative embodiment of the present invention.In this particular example, First comparison circuit 210（Fig. 2）It is configured to according to the control signal selectivity being applied on its extra input terminal 1300 Enable and disable.An advantage for selectively enabling and disabling the first comparison circuit 210 is that the first comparing ought not be used electric During road 210, first comparison circuit 210 can be disabled, so as to reduce the overall power of imageing sensor 100.In some applications In, implementation comparison procedure can be only needed once with per several frames, to realize certain predetermined image data reliability.In this feelings Under condition, during the frame that control signal need not apply, it may be necessary to disable the first comparison circuit 210.

In order to realize selective control, the first comparison circuit 210 is further included：Multiple transistors 1302₀To 1302_M, it is many Individual transistor seconds 1304₀To 1304_M, multiple third transistor 1306₀To 1306_M, enable transistor 1308 and phase inverter 1310.Transistor 1302₀To 1302_MEach include：The first terminal 1312, Second terminal 1314 and third terminal 1316. As illustrated, using the transistor 1302 recognized belonging to it₀To 1302_MThe subscript of related transistor represent the first terminal 1312nd, each of Second terminal 1314 and third terminal 1316.The first terminal 1312₀To 1312_MIt is respectively connecting to output end Son 712₀To 712_M.Respective transistor 1302₀To 1302_MAll Second terminals 1314₀To 1314_MIt is connected to the first comparison circuit 210 ground terminal 1318.Respective transistor 1302₀To 1302_MAll third terminals 1316₀To 1316_MIt is connected to the first ratio Compared with the common supply line 1320 of circuit 210.

Transistor seconds 1304₀To 1304_MEach also include：The first terminal 1322, Second terminal 1324 and the 3rd Terminal 1326.As illustrated, also using the transistor seconds 1304 recognized belonging to it₀To 1304_MRelated transistor subscript come Represent each of the first terminal 1322, Second terminal 1324 and third terminal 1326.The first terminal 1322₀To 1322_MRespectively It is connected to lead-out terminal 718₀To 718_M.Corresponding transistor seconds 1304₀To 1304_MAll Second terminals 1324₀To 1324_MEven It is connected to the ground terminal 1318 of the first comparison circuit 210.Corresponding transistor seconds 1304₀To 1304_MAll third terminals 1326₀To 1326_MIt is connected to the common supply line 1320 of the first comparison circuit 210.

Third transistor 1306₀To 1306_NEach also include：The first terminal 1328, Second terminal 1330 and the 3rd Terminal 1332.As illustrated, also using the third transistor 1306 recognized belonging to it₀To 1306_MRelated transistor subscript come Represent each of the first terminal 1328, Second terminal 1330 and third terminal 1332.The first terminal 1328₀To 1328_MRespectively It is connected to lead-out terminal 724₀To 724_M.Corresponding third transistor 1306₀To 1306_MAll Second terminals 1330₀To 1330_MEven It is connected to the ground terminal 1318 of the first comparison circuit 210.Corresponding third transistor 1306₀All third terminals in 130 1332₀To 1332_MIt is connected to the common supply line 1320 of the first comparison circuit 210.

Enabling transistor 1308 includes：The first terminal 1334, is connected to the input terminal 1300 of the first comparison circuit 210； Second terminal 1336, is connected to common supply line 1320；And third terminal 1338, it is connected to the electricity of the first comparison circuit 210 Potential source 1340.Phase inverter 1310 includes：Input terminal 1342, is connected to common supply line 1320；And lead-out terminal 1344, even It is connected to the error signal output line 706 of the first comparison circuit 210.

Following example describes the operation according to the first comparison circuit 210 in the alternative embodiment.First, input terminal 1300 are in low-voltage state, and transistor 1308 is enabled so as to order about.When order about enable transistor 1308 when, in third terminal Voltage drop, therefore common supply line 1320 and input including phase inverter 1310 are occurred without between 1338 and Second terminal 1336 The voltage status of the node of son 1342 are equal to the high-voltage state of voltage source 1340.Certainly, due to the input of phase inverter 1310 Son 1342 is in high-voltage state, so lead-out terminal 1344 is in low-voltage state.In order to enable the first comparison circuit 210, Signal is enabled to be applied on input terminal 1300 in the form of high-voltage state.This causes to enable transistor 1308 in non-conduction State（" closing "）, so that the common supply line 1320 and input terminal 1342 of phase inverter 1310 do not connect with voltage source 1340 Connect.After closing enables transistor 1308, the common supply line 1320 of phase inverter 1310 and the voltage shape of input terminal 1342 State keeps precharge（precharge）To high-voltage state.If XOR gate 700₀To 700_M、702₀To 702_MAnd/or 704₀Extremely 704_MIt is any one or more with not corresponding input terminal, then related lead-out terminal will with high-voltage state, from And order about（It is in the conduction state）Transistor 1302₀To 1302_M, transistor seconds 1304₀To 1304_MOr third transistor 1306₀Any one to 130 has connected gate pole.Transistor 1302₀To 1302_M, transistor seconds 1304₀Extremely 1304_MOr third transistor 1306₀To 1306_MAny one or more order about the common confession of coupled inverters 1310 Answer line 1320 and input terminal 1342 to ground terminal 1318.Therefore, the input terminal 1342 of phase inverter 1310 makes lead-out terminal 1344（Therefore wrong output signal line 706）With high-voltage state.Certainly, the high-voltage state of error signal line 706 is table Show that one or more control signals are not appropriately distributed in control signal wire 300 also₀To 300_MError signal.

Figure 14 is according to the electricity that sample circuit 1400 and replacement comparison circuit 1402 are replaced in another embodiment of the present invention Lu Tu.It should be appreciated that many features of sample circuit 1400 are substantially similar with sample circuit 212, therefore, with similar attached Icon note is represented.Those essentially similar elements are not described in detail again, to avoid repeating.

In this particular example, sample circuit 1400 includes the first encoder 1404 and second encoder 1406.The One encoder 1404 is respectively connecting to the first control signal wire 802, the second control signal wire 804 and the 3rd control signal wire 806 first end 830,834,838, and it is operable to encode the control signal being applied thereto.First encoder 1404 is wrapped Lead-out terminal 1408 is included, it is connected to provide the coded data of comparison circuit 1402, and the coded data is by being applied to corresponding first Control in the first end 830,834,838 of control signal wire 802, the second control signal wire 804 and the 3rd control signal wire 806 Represented by signal processed.Second encoder 1406 be respectively connecting to the first control signal wire 802, the second control signal wire 804 and Second end 832,836,840 of the 3rd control signal wire 806, and it is operable to encode the control signal being applied thereto.The Two encoders 1406 also include lead-out terminal 1410, and it is connected to provide the coded data of comparison circuit 1402, the coded data By the second end for being applied to corresponding first control signal wire 802, the second control signal wire 804 and the 3rd control signal wire 806 832nd, represented by the control signal on 836,840.

Comparison circuit 1402 includes：First input end 1412, the second input terminal 1414 and error signal output end Son 1416.First input end 1412 is coupled to receive the coded number of the lead-out terminal 1408 from the first encoder 1404 According to.Second input terminal 1414 is coupled to receive the coded data of the lead-out terminal 1410 from second encoder 1406.

During the operation of sample circuit 1400, the first encoder 1404 and second encoder 1406 are encoded and are applied to simultaneously Control signal on first control signal wire 802, the second control signal wire 804 and the 3rd control signal wire 806.More specifically Ground, the first encoder 1404 encodes the control signal from first end 830,834,838, and the coding of second encoder 1406 is from the The control signal at two ends 832,836,840.First encoder 1404 and second encoder 1406 are also exported from defeated simultaneously respectively Go out the coded data of terminal 1408,1410.The input terminal 1412,1414 of comparison circuit 1402 is received from input simultaneously respectively The coded data of the output of son 1408,1410.Then, comparison circuit 1402 determines the coded data received from input terminal 1412 Whether the coded data received from input terminal 1414 is corresponded to.If the coded data received from input terminal 1412 is not The coded data received from input terminal 1414 is suitably corresponded to, then comparison circuit is defeated from error signal lead-out terminal 1416 Error error signal.The error signal is represented and is applied to the first control signal wire 802, the second control signal wire 804 and the 3rd control Control signal on holding wire processed 806 is not distributed in all pixels reading circuit 808 suitably₀To 808_N。

Term " connection " used herein refers to the direct electrical connection between connecting element, without any middle dress Put.Term " coupling " refers to direct electrical connection between connecting element or by one or more passive or active centres Device is indirectly connected with.Term " circuit " refers to linking together providing the active and/or passive single of required function Element or multiple element.Term " signal " refers at least one of electric current, voltage, electric charge, data or other signals.

One or more embodiments include manufacture thing（For example, computer procedures product）, it include machineaccessible and/or Machine-readable medium.The medium can include providing for example to store letter by machineaccessible and/or in the form of can read The mechanism of breath.If machineaccessible and/or machine-readable medium can be provided or storage is performed via machine thereon One or more or a sequence instruction and/or the data structure for just causing or occur and/or make machine to perform in machine execution, To realize one or more or a part of operation shown in accompanying drawing disclosed herein or method or technique.

In one embodiment, machine-readable medium can include tangible non-transitory machine-readable storage medium.Example Such as, tangible non-transitory machine-readable storage medium can include floppy disk, optical storage media, CD, CD-ROM, magnetic sheet, magnetic CD, read-only storage（Read Only Memory, ROM）, programming ROM（Programmable ROM, PROM）, it is erasable Programming ROM（Erasable and Programmable ROM, EPROM）, electrically erasable ROM（Electrically EPROM, EEPROM）, random access memory, static state RAM（Static RAM, SRAM）, dynamic ram（Dynamic RAM, DRAM）, flash memory, phase transformation（Phase-Change）Memory or its combination.Tangible medium can include one or more Solid-state or tangible physical material, for example such as, semi-conducting material, phase-change material, magnetic material etc..The example of appropriate machine Including（But it is not limited to）Digital camera, digital camcorder, mobile phone, computer system, other electronics with pel array Device and it is capable of other electronic installations of capture images.This kind of electronic installation is generally included and one or more other elements （Such as one or more storage devices（Non-transitory machine-readable storage medium））The one or more processors of coupling.Cause This, the storage device of given electronic installation can store the code performed in the one or more processors of the electronic installation And/or data.Or, it is possible to use the different of software, firmware and/or hardware combine one or more portions for implementing the embodiment Point.

The description of the particular embodiment of the present invention is completed now.Without departing from the scope of the invention, many is retouched The feature stated can be replaced, changes or omitted.For example, creative feature can apply to various image sensor types（For example, Front illuminated sensor, back side illuminated sensor etc.）.As another example, many circuit elements and structure（For example, gate, Transistor types, switch etc.）Can using implement substantially like function replacement circuit element and structure replace.Depart from These and other features of shown specific embodiment are it will be apparent that especially existing for those of ordinary skill in the art Content aspect disclosed above.

Claims

1. a kind of image capture apparatus, including：

Multiple pixels, each pixel includes optical sensor, optionally couples to receive the photoelectricity from the optical sensor The charge storage region of stream, coupled to the charge storage region and be operated to provide expression storage the electric charge storage The output end of the output signal of the quantity of electric charge in region and the test signal input coupled to the charge storage region；

Test signal injection circuit, is coupled to provide the test signal input of test signal to the pixel；

Sample circuit, is selectively coupled to receive the output signal of the output end from the pixel；And

Comparison circuit, in response to providing the output received to the test signal of the pixel and from the pixel Signal, and error signal is operated to provide, with the output signal in response to not corresponding to the test signal.

2., according to the image capture apparatus described in claim 1, the wherein test signal injection circuit is coupled to the comparison circuit, So that equally the test signal provided to the pixel is provided to the comparison circuit.

3. according to the image capture apparatus described in claim 1, wherein：

The pixel is arranged as multiple row；And

The image capture apparatus include that a plurality of electric charge injects line, and each electric charge injects line by a corresponding row of the row The test signal input of the pixel is connected to the test signal injection circuit.

4., according to the image capture apparatus described in claim 3, the charge storage region of each of which pixel is via electric capacity Device injects line coupled to a corresponding electric charge.

5., according to the image capture apparatus described in claim 4, the electricity of the pixel is inserted in without switching device Between lotus storage region and electric charge injection line.

6., according to the image capture apparatus described in claim 3, wherein the test signal injection circuit can be described in different Different test signals are provided on electric charge injection line.

7., according to the image capture apparatus described in claim 3, the wherein test signal injection circuit can be existed with different timing Different test signals are provided on electric charge injection line described in identical.

8., according to the image capture apparatus described in claim 3, the wherein test signal injection circuit includes：

Multiple test signal memory elements, each is selectively coupled to corresponding electric charge injection line；And

Measuring signal generator, coupled to the test signal memory element, and is operated to create test signal value and incites somebody to action The test signal value storage is in the test signal memory element.

9. according to the image capture apparatus described in claim 8, wherein：

The measuring signal generator is operated to create digital test signal value；And

Each test signal memory element is single-bit storage element.

10., according to the image capture apparatus described in claim 9, the wherein measuring signal generator includes random bit generators.

11. according to the image capture apparatus described in claim 10, wherein：

The test signal memory element is coupled in series between together；And

Position from the random bit generators is moved in the test signal memory element.

12. according to the image capture apparatus described in claim 3, wherein：

The charge storage region of each pixel is selectively coupled to by the switching device of pixel each described The optical sensor of each pixel；

The image capture apparatus further include controller, are coupled to provide transmission signal to the switch of the pixel and fill Put；

The switching device, in response to the first value of the transmission signal, conducts the optical sensor and the electric charge storage region Photoelectric current between domain, to be easy to image capture；And

The switching device, in response to the second value of the transmission signal, stops the optical sensor and the electric charge storage region Photoelectric current between domain, to be easy to test signal injection.

13. according to the image capture apparatus described in claim 12, wherein：

The image capture apparatus perform multiimage acquisition procedure on continuous frame time, with the frame of capture images data；

The second value of the transmission signal is applied the controller duration of an image capture process, to be easy to during every N frames Between test signal injection, wherein N is the integer more than 1.

14., according to the image capture apparatus described in claim 1, further include：

Controller, is operated to provide control signal；

Driver, in response to the control signal, and is operable to produce drive signal based on the control signal, and this is driven Dynamic signal is applied on the control line of the image capture apparatus；And

Comparator, in response to the first input based on the control signal and the second input based on the drive signal, this compares If device is operable to be easy to the control signal not in a predefined manner corresponding to the drive signal of the applying, a mistake letter is produced Number.

15. directly compare the control signal and the drive according to the image capture apparatus described in claim 14, the wherein comparator Dynamic signal, to determine whether the drive signal corresponds to the control signal.

16. according to the image capture apparatus described in claim 14, wherein：

The image capture apparatus further include image photo sensor array；And

The driver is the row control driver of the image photo sensor array.

17. according to the image capture apparatus described in claim 14, wherein：

The image capture apparatus further include image photo sensor array；

The image capture apparatus further include image data samples circuit, are coupled to receive from the image light sensor array The data row of row；And

The driver is the element of the image data samples circuit.

18. according to the image capture apparatus described in claim 14, wherein：

The image capture apparatus further include the second driver, are coupled to receive the control signal, and be operable to base The second drive signal is produced in the control signal；And

The comparator is operable to compare second drive signal and the drive signal.

19., according to the image capture apparatus described in claim 14, further include：

The a plurality of control line；

First encoder, is coupled to the control line at first point, and is operable to be based on detected on the control line The drive signal for arriving produces the first encoded radio；And

Second encoder, is being coupled to the control line, second coding at the second point at a certain distance from this first point Device is operable to produce one second encoded radio based on the drive signal detected on the control line,

Wherein the comparator is operable to compare first encoded radio and second encoded radio.

The method of the failure in a kind of 20. acquisition equipments for detection image, the method includes：

Offer includes the image capture apparatus of photosensor array；

Image is set to focus on the photosensor array；

Using the frame of the photosensor array repeatedly capture images data, the pictorial data representation focuses on optical sensor battle array The image on row；

Between the repetition of the view data is captured, test data is periodically injected into the photosensor array；

The test data is read from the image capture apparatus；

Compare the test data of the reading and the test data of the injection；And

If the test data of the reading does not correspond to the test data of the injection, error signal is produced.

21., according to the method described in claim 20, further include：

Receive control signal；

Drive signal is produced based on the control signal；

The drive signal is applied on the control line of the image capture apparatus；

Compare the drive signal and the control signal of the applying；And

If the control signal is not drive signal in a predefined manner corresponding to the applying, error signal is produced.

22. according to the method described in claim 21, wherein the drive signal to be applied to the control of the image capture apparatus The step on line includes：The drive signal is applied on the row control line of image photo sensor array.

23. according to the method described in claim 21, wherein the drive signal to be applied to the control of the image capture apparatus The step on line includes：The drive signal is applied on the control line of image data samples circuit.

24. according to the method described in claim 21, wherein comparing the drive signal of the applying and the step of the control signal Including：

Second drive signal is produced based on the control signal；And

Compare second drive signal and the drive signal.

25. according to the method described in claim 21, wherein comparing the drive signal of the applying and the step of the control signal Including：

First encoded radio is produced based on the drive signal at the first point for applying on multiple control lines；

Second encoded radio is produced based on the drive signal at the second point being applied on the control line；And

Compare first encoded radio and second encoded radio.

A kind of 26. image capture apparatus, including：

Multiple pixels, each described pixel includes optical sensor, optionally couples to receive from the optical sensor The charge storage region of photoelectric current, coupled to the charge storage region and be operated to provide expression storage the electric charge storage The output end of the output signal of the quantity of electric charge in region and the test signal input coupled to the charge storage region；

Device, the output received to the test signal of the pixel and from pixel letter is provided for comparing Number, and for providing error signal with the output signal in response to not corresponding to the test signal.

27., according to the image capture apparatus described in claim 26, further include：

Controller, is operated to provide control signal；

Device, for comparing the first input based on the control signal and the second input based on the drive signal, and is used for If the control signal is not in a predefined manner corresponding to the drive signal of the applying, for producing error signal.