JP2009213012A - Solid-state imaging apparatus, method of driving solid-state imaging apparatus, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance an yield caused by a defect by relieving the relevant defect in an analog circuit of a column processing section. <P>SOLUTION: In a column processing section 13A, current sources 32-1 to 32-4 and comparators 33-1 to 33-4, which are portions of an analog circuit, are provided more than the number of pixel columns one by one and in a case where there is a defect in a certain current source or comparator, it is substituted with another normal current source or comparator, namely, the portions in the analog circuit of the column processing section 13A are configured redundantly. On the basis of shift register information in a predetermined shift register 36, a defective portion is substituted with a normal circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a driving method for the solid-state imaging device, and an imaging device, and more particularly, to a so-called column ADC (analog-digital conversion) type solid-state imaging device, a driving method for the solid-state imaging device, and the solid-state imaging device. The present invention relates to an image pickup apparatus.

  As one type of solid-state imaging device, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device, for example, a CMOS type (including MOS type) solid-state imaging device (hereinafter referred to as “CMOS image sensor”) is described. ), An independent column processing unit is provided for each pixel column with respect to a pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and a signal (pixel signal) is provided from each pixel of the pixel array unit. Is sequentially read out for each pixel row, temporarily held in a column processing unit, and a technique called a column method in which pixel signals for one row are sequentially read at a predetermined timing is known.

  Further, in the column processing unit provided for each pixel column of the pixel array unit, the pixel signal is compared with the reference signal of the ramp (RAMP) waveform by the comparator, and thereby the magnitude in the time axis direction corresponding to the magnitude of the pixel signal. A pulse signal having a (pulse width) is generated, a predetermined clock is counted by a counter during the pulse width period of the pulse signal, and the count value is converted into a digital signal corresponding to the magnitude of the pixel signal, thereby performing AD conversion. There is a column ADC type CMOS image sensor configured to perform (see, for example, Patent Document 1).

JP 2005-323331 A

  Incidentally, in recent years, in CMOS image sensors, it has been recommended to reduce the size of peripheral circuits as well as pixels, and accordingly, defects have arisen. Unlike the memory cell of the memory, the defect of the pixel of the image sensor cannot be completely remedied by redundancy because the pixel position is different and the signal information is different even if information from different pixels is used. A defective pixel is a white spot. However, if the pixel defect is small, it is possible to correct the signal information of the defective pixel based on the information of neighboring pixels.

  Also, the digital circuit of each column, the counter in the case of the column ADC system, and the like need only handle binary signal levels, and so high accuracy is not necessary. However, very high accuracy is required for the analog circuit of each column. For example, the comparator in the case of the column ADC system requires multistage determination, for example, determination of the signal level in 4096 stages. In addition, when the number of pixels in the horizontal direction (horizontal direction) is, for example, 6000, all of the 6000 analog circuits need to operate correctly.

  However, conventionally, since the method of making the analog circuit of the column ADC type image sensor redundant is not adopted, a chip cannot be shipped for an image sensor in which all analog circuits do not operate with high accuracy. , Which was one of the causes of reduced yield.

  Therefore, the present invention provides a column ADC type solid-state imaging device that can remedy a defect in an analog circuit by improving the yield due to the defect by adopting a method in which the analog circuit of the column processing unit has a redundant configuration, An object of the present invention is to provide a driving method of the solid-state imaging device and an imaging device using the solid-state imaging device.

The solid-state imaging device according to the present invention is
A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A column processing unit having a larger number of analog circuits than the number corresponding to the pixel columns of the pixel array unit, and processing an analog signal output from the unit pixel through a vertical signal line for each pixel column;
The column processing unit
Pass / fail information storage means for storing information on pass / fail of each analog circuit;
Selection means for selecting a normal analog circuit instead of a defective analog circuit among the analog circuits based on information stored in the pass / fail information storage means.

  The solid-state imaging device having the above configuration is used as an imaging device (imaging device) in a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone.

  In the solid-state imaging device having the above-described configuration or an imaging device using the solid-state imaging device, when a column processing unit including an analog circuit is provided with more analog circuits than the number of pixel columns and there is a defect in one analog circuit By adopting a so-called redundant configuration that substitutes for another normal analog circuit, it is possible to remedy a defect in the analog circuit and improve the yield due to the defect.

A driving method of a solid-state imaging device according to the present invention includes:
A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A solid-state device having a number of analog circuits greater than the number corresponding to the pixel columns of the pixel array unit, and a column processing unit that processes analog signals output from the unit pixels through vertical signal lines for each pixel column A method for driving an imaging apparatus,
A normal analog circuit is selected and used instead of a defective analog circuit among the analog circuits based on information on the quality of each analog circuit stored in advance.

  In a column processing unit having a redundant configuration, when a certain analog circuit is defective, it can be replaced with another normal analog circuit to relieve the analog circuit defect and improve the yield due to the defect. .

  According to the present invention, the analog circuit portion of the column processing unit is configured in a redundant configuration, and the defective portion is replaced with a normal circuit on the basis of predetermined information (good or bad information). Can be saved and the yield resulting from the defect can be improved, so that the manufacturing cost can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[System configuration]
FIG. 1 is a system configuration diagram showing an outline of the configuration of a solid-state imaging device to which the present invention is applied, for example, a CMOS image sensor.

  As shown in FIG. 1, a CMOS image sensor 10 according to this application example is integrated on a pixel array unit 11 formed on a semiconductor substrate (chip) (not shown) and the same semiconductor substrate as the pixel array unit 11. The peripheral circuit section, that is, the vertical drive section 12, the column processing section 13, the horizontal drive section 14, and the system control section 15 are provided.

  In the pixel array unit 11, unit pixels (not shown) including a photoelectric conversion element that photoelectrically converts incident visible light into a charge amount corresponding to the amount of light (hereinafter may be simply referred to as “pixel”) are arranged in a matrix. Are two-dimensionally arranged. A specific configuration of the unit pixel will be described later.

  The pixel array unit 11 further includes pixel drive lines 16 for each row in the matrix-like pixel arrangement along the horizontal direction of the drawing (pixel arrangement direction of the pixel rows), and vertical signal lines 17 for each column. Are formed along the vertical direction of the figure (pixel arrangement direction of the pixel column). In FIG. 1, the pixel drive line 16 is shown as one line, but the number is not limited to one. One end of the pixel drive line 16 is connected to an output end corresponding to each row of the vertical drive unit 12.

  The vertical drive unit 12 is configured by a shift register, an address decoder, and the like, and a specific configuration thereof is omitted, but a reading scanning system for performing selective scanning sequentially for each unit pixel for reading a signal, Unnecessary charges are swept out (reset) from the photoelectric conversion elements of the unit pixels of the readout row prior to the readout row by the time of the shutter speed with respect to the readout row in which readout scanning is performed by the readout scanning system. It has a configuration having a sweep scanning system for performing sweep scanning.

  A so-called electronic shutter operation is performed by sweeping (reset) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and a new exposure is started (photocharge accumulation is started).

  The signal read by the reading operation by the reading scanning system corresponds to the amount of light incident after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the previous read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photocharge accumulation time (exposure time) in the unit pixel.

  A signal output from each unit pixel in the pixel row selectively scanned by the vertical driving unit 12 is supplied to the column processing unit 13 through each of the vertical signal lines 17. The column processing unit 13 is a signal reading circuit unit that reads, for each pixel column of the pixel array unit 11, an analog signal output from each pixel 20 in the selected row while converting the analog signal into a digital signal. The detailed circuit configuration and circuit operation of the column processing unit 13 will be described later.

  The horizontal drive unit 14 includes a shift register, an address decoder, and the like, and selects the column processing unit 13 in order. By this selective scanning by the horizontal drive unit 14, pixel signals digitized by the column processing unit 13 are sequentially output.

  The system control unit 15 includes a timing generator that generates various timing signals, and the vertical driving unit 12, the column processing unit 13, the horizontal driving unit 14, and the like based on the various timing signals generated by the timing generator. Drive control is performed.

(Circuit configuration of unit pixel)
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the unit pixel 20. As shown in FIG. 2, the unit pixel 20 according to this circuit example includes a photoelectric conversion element, for example, a photodiode 21, and four transistors, for example, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25. It has a configuration.

  Here, as the four transistors 22 to 25, for example, N-channel MOS transistors are used. However, the conductivity type combinations of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 illustrated here are merely examples, and are not limited to these combinations.

  For this unit pixel 20, as the pixel drive line 16, for example, three drive lines of a transfer line 161, a reset line 162, and a selection line 163 are provided in common for each pixel in the same pixel row. One end of each of the transfer line 161, the reset line 162, and the selection line 163 is connected to an output end corresponding to each pixel row of the vertical drive unit 12 in units of pixel rows.

  The photodiode 21 has an anode electrode connected to a negative power source (for example, ground), and photoelectrically converts received light into photocharge (here, photoelectrons) having a charge amount corresponding to the light amount. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 through the transfer transistor 22. A node 26 electrically connected to the gate electrode of the amplification transistor 24 is referred to as an FD (floating diffusion) portion.

  The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the FD unit 26, and a transfer pulse φTRF having a high level (for example, Vdd level) is active (hereinafter referred to as “High active”) is transferred to the transfer line. By being applied to the gate electrode via 161, it is turned on, and the photoelectric charge photoelectrically converted by the photodiode 21 is transferred to the FD portion 26.

  The reset transistor 23 is turned on when the drain electrode is connected to the pixel power source Vdd, the source electrode is connected to the FD unit 26, and a high active reset pulse φRST is applied to the gate electrode via the reset line 162, and the photodiode is turned on. Prior to the transfer of signal charges from the FD unit 26 to the FD unit 26, the FD unit 26 is reset by discarding the charges of the FD unit 26 to the pixel power supply Vdd.

  The amplification transistor 24 has a gate electrode connected to the FD unit 26 and a drain electrode connected to the pixel power supply Vdd, and outputs the potential of the FD unit 26 after being reset by the reset transistor 23 as a reset signal (reset level) Vreset. The potential of the FD unit 26 after the transfer of the signal charge by the transfer transistor 22 is output as a light accumulation signal (signal level) Vsig.

  For example, the selection transistor 25 is turned on when the drain electrode is connected to the source of the amplification transistor 24, the source electrode is connected to the vertical signal line 17, and a high active selection pulse φSEL is applied to the gate via the selection line 163. Thus, the unit pixel 20 is selected and the signal output from the amplification transistor 24 is relayed to the vertical signal line 17.

  Note that the selection transistor 25 may have a circuit configuration connected between the pixel power supply Vdd and the drain of the amplification transistor 24.

  In addition, the unit pixel 20 is not limited to the pixel configuration including the four transistors having the above-described configuration. For example, the unit pixel 20 includes a pixel configuration including three transistors that serve as the amplification transistor 24 and the selection transistor 25. The configuration of the pixel circuit is not limited.

  In the CMOS image sensor 10 configured as described above, the present invention is characterized by the circuit configuration and circuit operation of the column processing unit 13. A specific example of the column processing unit 13 will be described below.

[Example 1]
FIG. 3 is a circuit diagram illustrating the column processing unit 13A according to the first embodiment of the present invention. Here, in order to simplify the drawing, the number of pixel columns (the number of pixels in the horizontal direction) x is set to x = 3.

  As illustrated in FIG. 3, the column processing unit 13A according to the first embodiment includes a first switch circuit 31, current sources 32-1 to 32-4, comparators 33-1 to 33-4, and a second switch circuit. 34, counters 35-1 to 35-3, and a circuit configuration including, for example, a shift register 36 as pass / fail information storage means. That is, the column processing unit 13A according to the first embodiment has a configuration in which (x + 1) current sources 32 and comparators 33 are provided and x counters 35 are provided for x pixel columns.

  The first switch circuit 31 includes six (= 2x) switch elements SW11 to SW16. As the switch elements SW11 to SW16, for example, analog switches using CMOS transmission gates are used. Each of the switch elements SW11 to SW16 has an input terminal connected to one end of each of the vertical signal lines 17-1, 17-2, 17-3 in pairs.

  The current sources 32-1 to 32-4 are configured by, for example, three MOS transistors (load MOS transistors) connected in series. As the current sources 32-1 to 32-4, simple resistance elements can be used instead of the load MOS transistors.

  Among the current sources 32-1 to 32-4, the current sources 32-1 and 32-4 at both ends are respectively between the output terminals of the switch elements SW 11 and SW 16 at both ends and a reference potential node (for example, ground). It is connected. Of the remaining current sources 32-2 and 32-3, the current source 32-2 is connected between the output terminals of the switch elements SW12 and SW13 and the reference potential node. The switch elements SW14 and SW15 are connected between the output terminals and the reference potential node.

  The comparators 33-1 to 33-4 have one input terminals connected to the output terminals of the switch elements SW11 to SW16 in a relationship corresponding to the current sources 32-1 to 32-4. That is, one input terminal of each of the comparators 33-1 and 33-4 on both sides is connected to the output terminal of the switch elements SW11 and SW16 on both ends, and one input terminal of the comparator 33-2 is connected to each of the switch elements SW12 and SW13. Connected to the output terminal, one input terminal of the comparator 33-3 is connected to each output terminal of the switch elements SW14 and SW15.

  A ramp (RAMP) waveform generated by a reference signal generation source (not shown), that is, a reference signal REF having an inclined waveform is commonly input to the other input ends of the comparators 33-1 to 33-4. . The comparators 33-1 to 33-4 compare an analog pixel signal input from the vertical signal lines 17-1, 17-2, and 17-3 through the first switch circuit 31 with a reference signal REF having a ramp waveform. Thus, a pulse signal having a magnitude (pulse width) in the time axis direction corresponding to the magnitude of the pixel signal is output.

  Due to the connection relationship between the switch elements SW11 to SW16, the current sources 32-1 to 32-4, and the comparators 33-1 to 33-4, the first switch circuit 31 includes the vertical signal lines 17-1, 17-2, For each of 17-3, the current source 32-1 to 32-4 and the current source of the comparators 33-1 to 33-4 and the comparator to be connected are selected.

  The second switch circuit 34 includes six (= 2x) switch elements SW21 to SW26. As the switch elements SW21 to SW26, analog switches using, for example, CMOS transmission gates are used, similarly to the switch elements SW11 to SW16. Each of the switch elements SW21 to SW26 is connected to each output terminal of the comparators 33-1 to 33-4 in pairs, each having two input terminals.

  In the counters 35-1 to 35-3, two adjacent comparators 33-1 to 33-4 are paired, and each input terminal is connected to each output terminal of the pair. That is, the input of the counter 35-1 is connected to each input terminal of the comparators 33-1, 33-2, the input of the counter 35-2 is connected to each input terminal of the comparators 33-2, 33-3, and the counter 35 -3 input is connected to each input terminal of the comparators 33-3 and 33-4.

  The counters 35-1 to 35-3 count a predetermined clock CK during the period of the pulse width of the pulse signal output from the comparators 33-1 to 33-4, thereby obtaining the count value of the pixel signal. Digital signal according to That is, the AD converter is configured by the reference signal generation source that generates the reference signal REF, the comparators 33-1 to 33-4, the counters 35-1 to 35-3, and the like.

  Due to the connection relationship between the second switch circuit 34 and the comparators 33-1 to 33-4 and the counters 35-1 to 35-3, the second switch circuit 34 is connected to each of the counters 35-1 to 35-3. Thus, the current source 32-1 to 32-4 and the comparator 33-1 to 33-4 are selected to be connected to the current source.

  The shift register 36 has a configuration in which a number of transfer stages (shift stages) corresponding to the number x of pixel columns (three in this example) are connected in cascade, and switch control of opposite phases from each transfer stage. Output a signal. Specifically, switch control signals CSEL0 and XCSEL0 are transmitted from the first transfer stage, switch control signals CSEL1 and XCSEL1 are transferred from the second transfer stage, and switch control signals CSEL2 and CSEL2 are transferred from the third transfer stage. XCSEL2 is output.

  The switch control signals CSEL0, XCSEL0 to CSEL2, and XCSEL2 perform on / off control of the switch elements of the first and second switch circuits 31 and 34. Specifically, switch control signals CSEL0 and XCSEL0 turn on / off control of switch elements SW11 and SW12 and switch elements SW21 and SW22, and switch control signals CSEL1 and XCSEL1 turn on switch elements SW13 and SW14 and switch elements SW23 and SW24. The switch control signals CSEL2 and XCSEL2 perform on / off control of the switch elements SW15 and SW16 and the switch elements SW25 and SW26.

  The current sources 32-1 to 32-4 and the comparators 33-1 to 33-33 are controlled by on / off control of the switch elements of the first and second switch circuits 31 and 34 by the switch control signals CSEL0, XSEL0 to CSEL2 and XCSEL2. 4, the combination of the adjacent current source and the comparator is not selected at the same time, and only one of the combinations is selected.

  Here, the current sources 32-1 to 32-4 and the comparators 33-1 to 33-4 are respectively connected to the vertical signal lines 17-1, 17-2, and 17-3 by the selection by the first switch circuit 31. The current sources 32-1 to 32-4 and the comparator 33-1 are selected for each of the counters 35-1 to 35-3 according to which of the current sources is connected to the comparator and the selection by the second switch circuit 34. The current source of any of .about.33-4 and the comparator are connected is determined by the information stored in the shift register 36. FIG.

  The information in the shift register 36 is hereinafter referred to as shift register information. The shift register information is determined by a test system or a camera system, and details thereof will be described later.

  In the column processing unit 13 according to the first embodiment described above, the current sources 32-1 to 32-4 and the comparators 33-1 to 33-4 are portions of analog circuits that handle analog signals when performing AD conversion of pixel signals. The counters 35-1 to 35-3 are digital circuit parts that handle digital signals.

  In general, an analog circuit is more likely to malfunction and malfunction than a digital circuit. In view of this point, the column processing unit 13A according to the first embodiment is provided with a larger number of analog circuits than the number corresponding to the pixel columns of the pixel array unit 11. More specifically, the current sources 32-1 to 32-4 and the comparators 33-1 to 33-4, which are parts of the analog circuit, are provided more than the number of pixel columns (one more in this example), When a certain current source or comparator is defective, a so-called redundant configuration is adopted in which the other normal current source or comparator is substituted.

  Information on the quality of each analog circuit, that is, whether the current source or the comparator is good or bad is stored in advance in the shift register 36 as shift register information. That is, the shift register 36 functions as a pass / fail information storage unit that stores individual pass / fail information of the analog circuit. However, the pass / fail information storage means is not limited to the shift register 36, and any configuration can be used as long as it can store individual pass / fail information of the analog circuit.

  Here, an actual operation example in the column processing unit 13A according to the first embodiment will be described with reference to FIG. Here, a case where the third comparator 33-3 from the left in FIG. 4 is defective is taken as an example.

  Since the third comparator 33-3 is defective in the shift register 36, the first, second, and fourth current sources 32-1, 32-2, and 32-4, and the comparator 33-1. , 33-2, 33-4 are pre-stored as shift register information. Based on the shift register information, the switch control signals CSEL0, CSEL1, and XCSEL2 output from the shift register 36 are set to the “H” level, and the switch control signals XCSEL0, VCSEL1, and CSEL2 are set to the “L” level.

  As a result, the switch elements SW11, SW13, SW16 of the first switch circuit 31 and the switch elements SW21, SW23, SW26 of the second switch circuit 34 are turned on. As a result, instead of the analog path including the defective comparator 33-3, the adjacent analog path including the normal comparator 33-3 becomes valid, and the comparison result of the comparator 33-4 is given to the counter 35-3. Will be.

  In this way, the analog circuit part of the column processing unit 13A is made redundant, and the defective part of the analog circuit is remedied by replacing the defective part with a normal circuit based on the predetermined shift register information. Since the yield resulting from the defect can be improved, the manufacturing cost can be reduced.

  In the first embodiment, the number of all pixel columns in the pixel array unit 11 is x, and x + 1 analog circuit portions are provided for the x pixel columns. This is for ease of understanding. It is only an example and is not limited to this. Specifically, all the pixel columns of the pixel array unit 11 are blocked in units of x pixel columns, and each block (hereinafter sometimes referred to as “main column unit”) is divided into x pixel columns. On the other hand, x + 1 analog circuit portions may be provided. In this case, the number x can be arbitrarily set.

  FIG. 5 shows a part of the pixel array unit 11 and the layout of the column processing unit 13A when x = 8 when the pixel processing unit 13A according to the first embodiment blocks x pixel columns. An example is shown.

  Since x = 8, there are x + 1 current sources (load MOS) 32 and comparators 33 and x counters 35 for each main column portion. Since the number of the current sources 32 and the comparators 33 is larger than that of the counter 35, the width of the layout of the portion of the analog circuit becomes narrow as is apparent from FIG.

  Here, the counter 35 is laid out closer to the comparator 34 than the shift register 36, but the positional relationship is arbitrary, and the shift register 36 is closer to the comparator 34 than the counter 35. Of course, the configuration may be laid out.

[Example 2]
FIG. 6 is a circuit diagram showing the column processing unit 13B according to the second embodiment of the present invention. In FIG. 6, the same parts as those in FIG. Here, the case where x = 3 is shown as an example.

  In the column processing unit 13A according to the first embodiment, the current source 32 and the comparator 33 in the analog circuit are redundantly configured, whereas in the column processing unit 13B according to the second embodiment, only the comparator 33 is provided. Have a redundant configuration.

  Specifically, as illustrated in FIG. 6, the column processing unit 13B according to the second embodiment includes x current sources 32 and x counters 35 with respect to x pixel columns, and (x + 1) comparators 33. It has a configuration in which pieces are provided. The three current sources 32-1 to 32-3 are configured except that they are connected between one end of each of the vertical signal lines 17-1 to 17-3 and a reference potential node (for example, ground). This is basically the same as the column processing unit 13A according to the first embodiment.

  In the column processing unit 13B configured as described above, the first switch circuit 31 is connected to the vertical signal line by the switch control signals CSEL0, XSEL0 to CSEL2, and XCSEL2 output from the shift register 36 based on the shift register information in the shift register 36. For each of 17-1, 17-2, 17-3, which of the comparators 33-1 to 33-4 is to be connected is selected, and the second switch circuit 34 includes a counter 35-1 to 35-3. For each of 35-3, an operation is performed to select which of the comparators 33-1 to 33-4 is connected.

  Here, an actual operation example in the column processing unit 13B according to the second embodiment will be described with reference to FIG. Here, a case where the third comparator 33-3 from the left in FIG. 7 is defective is taken as an example.

  Since the third comparator 33-3 is defective in the shift register 36, information for instructing the use of the first, second, fourth comparators 33-1, 33-2, 33-4. Are previously stored as shift register information. Based on the shift register information, the switch control signals CSEL0, CSEL1, and XCSEL2 output from the shift register 36 are set to the “H” level, and the switch control signals XCSEL0, XCSEL1, and CSEL2 are set to the “L” level.

  As a result, the switch elements SW11, SW13, SW16 of the first switch circuit 31 and the switch elements SW21, SW23, SW26 of the second switch circuit 34 are turned on. As a result, instead of the analog path including the defective comparator 33-3, the adjacent analog path including the normal comparator 33-3 becomes valid, and the comparison result of the comparator 33-4 is given to the counter 35-3. Will be.

  In this way, the analog circuit part of the column processing unit 13A is made redundant, and the defective part of the analog circuit is remedied by replacing the defective part with a normal circuit based on the predetermined shift register information. Since the yield resulting from the defect can be improved, the manufacturing cost can be reduced.

  In particular, in the column processing unit 13B according to the second embodiment, the switch elements SW11 to SW16 are interposed in a path including the current source 32 through which a direct current flows by excluding the current source 32 from the portion of the analog circuit having a redundant configuration. Therefore, it is preferable in terms of image quality as compared with the column processing unit 13A according to the first embodiment that employs a configuration in which the switch elements SW11 to SW16 are interposed in a path including the current source 32 through which a direct current flows.

  In the second embodiment, as in the first embodiment, all the pixel columns of the pixel array unit 11 are blocked in units of x pixel columns, and x pixel columns for each block. It is also possible to adopt a configuration in which x + 1 analog circuit portions are provided.

  FIG. 8 shows a part of the pixel array unit 11 and the layout of the column processing unit 13A when x = 8 when the pixel processing unit 13B according to the second embodiment blocks x pixel columns. An example is shown.

  Since x = 8, there are x + 1 current sources (load MOS) 32 and comparators 33 and x counters 35 for each main column portion. Since the number of the current sources 32 and the comparators 33 is larger than that of the counter 35, the width of the layout of the portion of the analog circuit becomes narrow as is apparent from FIG.

  Here, the counter 35 is laid out closer to the comparator 33 than the shift register 36, but the positional relationship is arbitrary, and the shift register 36 is closer to the comparator 33 than the counter 35. Of course, the configuration may be laid out.

  In the second embodiment, among the analog circuit portions of the column processing unit 13B, the current source 32 is excluded from the redundant configuration, and only the comparator 33 is configured as a redundant configuration. However, the comparator 33 is configured as a redundant configuration. It is also possible to adopt a configuration in which only the current source 32 is made redundant.

[Example 3]
FIG. 9 is a circuit diagram showing the column processing unit 13C according to the third embodiment of the present invention. In FIG. 9, the same parts as those in FIG. Here, the case where x = 3 is shown as an example.

  As illustrated in FIG. 9, the column processing unit 13 </ b> C according to the third embodiment includes a column processing unit 13 </ b> C-a disposed on the upper side of the pixel array unit 11 and a column processing unit 13 </ b> C disposed on the lower side. The column processing unit 13C-a is configured to process, for example, odd-numbered pixel signals, and the column processing unit 13C-b is configured to process even-numbered pixel signals.

  As described above, column processing units 13C-a and 13C-b are provided above and below the pixel array unit 11, and a signal from each pixel 20 is read out above and below the pixel array unit 11, thereby reading out only to one side. Compared to the first and second embodiments, the pixel signal readout speed can be increased, or the comparators 33a and 33b and the counters 35a and 35b can be laid out with a wider pitch.

  As in the case of the column processing unit 13A according to the first embodiment, each of the column processing units 13C-a and 13C-b has a redundant configuration of both the current sources 32a and 32b and the comparators 33a and 33b in the analog circuit portion. The structure which was made is taken. Note that the redundant configuration of both the current sources 32a and 32b and the comparators 33a and 33b is an example, and it is possible to adopt a configuration in which only the current sources 32a and 32b or only the comparators 33a and 33b are configured redundantly. It is.

  As described above, the analog circuit portions of the column processing units 13C-a and 13C-b are configured redundantly, and the defective portion is replaced with a normal circuit based on the predetermined shift register information. The manufacturing cost can be reduced because the defect can be remedied and the yield due to the defect can be improved.

  FIG. 10 shows a part of the pixel array unit 11 and the layout of the column processing unit 13A when x = 8 when the pixel processing unit 13C according to the third embodiment blocks x pixel columns. An example is shown.

  Since x = 8, there are x + 1 current sources (load MOS) 32 and comparators 33 and x counters 35 for each main column portion. Since the number of the current sources 32 and the comparators 33 is larger than that of the counter 35, the horizontal width of the layout of the analog circuit portion is narrowed.

  Further, it is apparent from FIG. 10 that column processing units 13C-a and 13C-b are provided above and below the pixel array unit 11 and a signal from each pixel 20 is read up and down the pixel array unit 11. As described above, the comparators 33a and 33b and the counters 35a and 35b can be laid out at a wide pitch, specifically, at a pitch approximately twice the pixel pitch.

[Generation method of shift register information]
Next, a specific generation method for generating shift register information stored in advance in the shift register 36 (36a, 36b) will be described.
(Generation method 1)
Generation method 1 relates to a method of generating shift register information by a test system focusing on linearity. The shift register information is determined by a test system in a pre-shipment test and is stored in a non-volatile memory. When a digital camera using a CMOS image sensor is used, shift register information is written from the nonvolatile memory to the shift register 36 (36a, 36b) by serial input every time it is activated.

  FIG. 11 is a flowchart illustrating a procedure for generating shift register information by the generation method 1.

  First, a subject such as paper of a color determined with a predetermined illuminance is photographed according to m places in the vertical direction of the pixel, n ways of temperature, and p ways of color (step S11). Here, the p colors are preferably p colors that gradually change from gray close to black to gradually close gray.

Next, a linear approximate expression and a residual sum of squares of a relationship between actual theoretically calculated luminance information and detected luminance of each comparator are calculated. When the theoretical luminance of the k-th color is x _k , the detected luminance is A _k , and the linear approximation is A = ax + b, the residual sum of squares is (A _k −ax _k −b) ² . This is the sum for all colors k.

で表わすことができる。 In other words, the residual sum of squares S is

It can be expressed as

This residual sum of squares S can be regarded as an index of linearity error. The larger the residual sum of squares S, the worse the linearity. This residual sum of squares S is calculated in m vertical positions (i = 1 to m) and n temperatures (j = 1 to n) in the vertical direction of the pixel, and S _{i, j} is calculated as in the following equation. (Step S12).

Then all i, S in j _i, and calculates the sum T of _j. The total T of the residual sum of squares S is expressed by the following equation.

  The sum T of the residual square sums S is calculated for each current source (hereinafter referred to as “load MOS”) and comparators, and the residual sum of squares is the largest among the main column units which are constituent units considering a redundant configuration. An external memory flag corresponding to the sub-redundant column with a large total T is set (step S13).

  Here, as shown in FIG. 5 and the like, the main column portion is a structural unit that considers a redundant unit. In FIG. 5, it is a unit in the horizontal direction corresponding to eight pixels. A sub-redundant column is a path that passes through a redundant portion in the main column portion.

  Thereafter, shift register information is generated from the flag of the external memory as follows (step S14). The “H” level (hereinafter simply described as “H”) is written on the left side of the flagged column in the main column portion, and the “L” level (hereinafter simply described as “L”) is written otherwise. Finally, the shift register information is written in the external nonvolatile memory (step S15).

  The residual sum of squares increases when the linearity is poor, but becomes an extremely large value when the operation is obviously defective. Therefore, the T value of the sub-redundant column that is clearly performing a bad operation is increased and a flag is set. As a result, the shift register information can be configured so as not to use the load MOS and comparator of the sub-redundant column that is clearly performing a defective operation. When such a sub-redundant column does not exist in the main column portion, the shift register information can be configured so that a portion with poor linearity is not used.

FIG. 12 shows how the shift register information is generated by the generation method 1. As shown in FIG. 12, two reading operations are required to extract detection values for one vertical location, one temperature, and one color. This is because, for example, there are nine load MOSs and comparators which are redundant parts, but there are fewer pixels and counters, for example, only eight, so different load MOSs and comparators are used using the same pixels and counters. This is because the detected value must be calculated.
(Generation method 2)
Generation method 2 relates to a method of generating shift register information by a test system focusing on the amount of noise. The shift register information is determined by a test system in a pre-shipment test and is stored in a non-volatile memory. When a digital camera using a CMOS image sensor is used, shift register information is written from the nonvolatile memory to the shift register 36 (36a, 36b) by serial input every time it is activated.

  FIG. 13 is a flowchart showing a procedure for generating shift register information by the generation method 2.

を算出する。 First, a subject such as paper of a predetermined color is photographed with a predetermined illuminance. Then, the luminance information of all pixels or a large number of pixels is read (step S21), and then the variance σ ² that is an index of variation is calculated for each sub-redundant column (step S22). This operation is performed for m different temperatures and n different colors. And the total variance

Is calculated.

  An external memory flag corresponding to the sub-redundant column having the maximum variance T in each main column portion is set (step S23). Then, shift register information is generated from the flag of the external memory as follows. That is, H is written on the left side of the flagged column in the main column section, and L is written otherwise (step S24). Finally, the shift register information is written into the external nonvolatile memory (step S25).

The value of the variance σ ² increases when there is a lot of noise, but becomes extremely large when the operation is clearly defective. Accordingly, the value of the total dispersion T of the sub-redundant columns that are clearly performing bad operation is increased and a flag is set. As a result, shift register information can be configured so as not to use load MOSs and comparators of sub-redundant columns that are clearly performing defective operations, and if such sub-redundant columns do not exist in the main column section, variations will occur. The shift register information can be configured so that bad parts are not used.

  FIG. 14 shows how the shift register information is generated by the generation method 2. As shown in FIG. 14, two readout operations are required to extract detection values for one vertical location, one temperature, and one color. This is because, for example, there are nine load MOSs and comparators which are redundant parts, but there are fewer pixels and counters, for example, only eight, so different load MOSs and comparators are used using the same pixels and counters. This is because the detected value must be calculated.

(Generation method 3)
Generation method 3 relates to a method of generating shift register information by a camera system focusing on linearity. The shift register information is determined by the camera system during a start-up test, and is used after being written into the shift register 36 (36a, 36b) during start-up.

  FIG. 15 is a circuit diagram showing a column processing unit 13D having a generation function based on the generation method 3. In the figure, the same parts as those in FIG.

  As shown in FIG. 15, test circuits 40-1, 40-2, 40-3 are connected to the vertical signal lines 17-1, 17-2, 17-3, respectively. The generation function according to the generation method 3 is realized by 40-2 and 40-3. The test circuit 40 (40-1, 40-2, 40-3) includes a pair of a source follower transistor 41 and a selection transistor 42.

  At the time of testing, the test enable signal FD_TEST_EN is set to H, the selection transistor 42 in the test circuit 40 is turned on, and an analog corresponding to a predetermined potential with respect to the gate of the source follower transistor 41, for example, the FD (floating diffusion) potential of the pixel 20 Apply potential TEST_V_IN.

  By carrying out like this, it can test by giving the same FD electric potential to all the columns. The input potential of the comparator is determined by the source follower and the load MOS in the test circuit 40. As a result, a failure of the load MOS can be detected in the test of the analog portion of the column, and the test is less affected by the pixel.

  Reading is performed with a plurality of analog potentials TEST_V_IN, for example, five, and a residual sum of squares S that is an index of linearity is calculated. Shift register information is generated so as not to use the load MOS and comparator of the sub-redundant column having the maximum residual square sum S in the main column portion.

  Since the test circuit 40 is used to reduce the influence of pixels, one of the test circuits 40 may be read. Of course, a plurality of test circuits 40 may be provided, and read results of the plurality of test circuits 40 may be used. In addition, since the test is performed every time when the camera system is started instead of the test system, it is considered that there is little change in temperature between the actual use and the test, and only one test temperature is required. Of course, paying attention to noise, the same test circuit 40 may be read a plurality of times to generate shift register information from the distribution.

  The shift register information generation method according to the generation method 3 requires less test machine time than the shift register information generation method according to the generation method 1. On the other hand, it is necessary to cope with the camera system generating shift register information by a test. That is, it is necessary to incorporate such a function into a DSP (Digital Signal Processor) which is a camera signal processing circuit.

(Generation method 4)
Generation method 4 relates to a method of generating shift register information by a camera system focusing on linearity. The shift register information is determined by the camera system during a start-up test, and is used after being written into the shift register 36 (36a, 36b) during start-up.

  FIG. 16 is a circuit diagram showing the column processing unit 13E having a generation function based on the generation method 4. In FIG. 16, the same parts as those in FIG. 3 are denoted by the same reference numerals.

  As shown in FIG. 16, a potential input circuit 43-1 that directly inputs a predetermined potential, for example, an analog potential TEST_V_IN corresponding to the FD potential, to each of the vertical signal lines 17-1, 17-2, 17-3. The generation function by the generation method 4 is realized by 43-2 and 43-3. The potential input circuit 43 (43-1, 43-2, 43-3) is constituted by, for example, an analog switch using a CMOS transmission gate.

  During the test, the test enable signals EQ_EN = H and XEQ_EN = L are set, and the analog potential TEST_V_IN is applied to the vertical signal lines 17 (17-1, 17-2, 17-3) from the outside. Further, the load MOS is turned off.

  Reading is performed with a plurality of analog potentials TEST_V_IN, for example, five, and a residual sum of squares S that is an index of linearity is calculated. Shift register information is generated so as not to use the load MOS and comparator of the sub-redundant column having the maximum residual square sum S in the main column portion.

  The generation method of the shift register information by the generation method 4 uses an external potential so as not to be affected by the pixels. In addition, since the test is performed every time when the camera system is started instead of the test system, it is considered that there is little change in temperature between the actual use and the test, and only one test temperature is required. Of course, paying attention to noise, the same external potential may be read a plurality of times to generate shift register information from dispersion.

  The shift register information generation method according to the generation method 4 requires less machine time for the test as the shift register information generation method according to the generation method 3. On the other hand, it is necessary to cope with the camera system generating shift register information by a test. That is, it is necessary to incorporate such a function into the DSP.

  However, unlike the shift register information generation method according to the generation method 3, the shift register information generation method according to the generation method 4 cannot repair the failure of the load MOS.

[Modification]
In the above embodiment, the case where the present invention is applied to a CMOS image sensor in which unit pixels that detect signal charges corresponding to the amount of visible light as physical quantities are arranged in a matrix has been described as an example. The present invention is not limited to application to a CMOS image sensor, but can be applied to all column-type solid-state imaging devices in which a column processing unit is arranged for each pixel column of a pixel array unit.

  Furthermore, the present invention is not limited to a solid-state imaging device that sequentially scans each unit pixel of the pixel array unit in units of rows and reads out a pixel signal from each unit pixel. The present invention is also applicable to an XY address type solid-state imaging device that reads out signals in units of pixels.

  The solid-state imaging device may be formed as a single chip, or may be in a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.

  In addition, the present invention is not limited to application to a solid-state imaging device, but can also be applied to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device.

[Imaging device]
FIG. 17 is a block diagram illustrating an example of the configuration of the imaging apparatus according to the present invention. As shown in FIG. 17, an imaging apparatus 100 according to the present invention includes an optical system including a lens group 101 and the like, an imaging element 102, a DSP circuit 103 that is a camera signal processing circuit, a frame memory 104, a display device 105, and a recording device 106. A configuration in which an operation system 107, a power supply system 108, and the like are connected, and a DSP circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, and a power supply system 108 are connected to each other via a bus line 109. It has become.

  The lens group 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 102. The imaging element 102 converts the amount of incident light imaged on the imaging surface by the lens group 101 into an electrical signal in units of pixels and outputs the electrical signal. As the image sensor 102, a CMOS image sensor having the column processing unit according to the first to third embodiments described above is used.

  The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 102. The recording device 106 records a moving image or a still image captured by the image sensor 102 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation system 107 issues operation commands for various functions of the imaging apparatus under operation by the user. The power supply system 108 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

1 is a system configuration diagram showing an outline of a configuration of a CMOS image sensor to which the present invention is applied. It is a circuit diagram which shows an example of the circuit structure of a unit pixel. It is a circuit diagram which shows the column process part which concerns on Example 1 of this invention. FIG. 6 is an explanatory diagram of an actual operation example in the column processing unit according to the first embodiment. FIG. 6 is a diagram illustrating an example of a part of a pixel array unit and a layout of a column processing unit when x = 8 when the pixel processing unit according to the first embodiment blocks x pixel columns as a unit. . It is a circuit diagram which shows the column process part which concerns on Example 2 of this invention. FIG. 10 is an explanatory diagram of an actual operation example in the column processing unit according to the second embodiment. FIG. 10 is a diagram illustrating an example of a part of a pixel array unit and a layout of a column processing unit when x = 8 when a pixel processing unit according to a second embodiment blocks x pixel columns. . It is a circuit diagram which shows the column process part which concerns on Example 3 of this invention. FIG. 11 is a diagram illustrating an example of a part of a pixel array unit and a layout of a column processing unit when x = 8 when the pixel processing unit according to the third embodiment blocks x pixel columns as a unit. . 10 is a flowchart illustrating a procedure for generating shift register information by a generation method 1; It is a figure which shows a mode that shift register information is produced | generated by the production | generation method 1. FIG. 10 is a flowchart illustrating a procedure for generating shift register information by a generation method 2; It is a figure which shows a mode that shift register information is produced | generated by the production | generation method 2. FIG. 12 is a circuit diagram illustrating a column processing unit having a generation function according to a generation method 3. FIG. FIG. 10 is a circuit diagram showing a column processing unit having a generation function according to generation method 4; It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... CMOS image sensor, 11 ... Pixel array part, 12 ... Vertical drive part, 13 (13A-13E) ... Column processing part, 14 ... Horizontal drive part, 15 ... System control part, 16 ... Pixel drive line, 17 (17 -1, 17-2, 17-3) ... vertical signal line, 20 ... unit pixel, 31 ... first switch circuit, 32 (32-1 to 32-4) ... current source, 33 (33-1 to 33-) 4) ... Comparator 34 ... Second switch circuit 35 (35-1 to 35-3) ... Counter 36 (36a, 36b) Shift register

Claims (12)

A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A column processing unit having a larger number of analog circuits than the number corresponding to the pixel columns of the pixel array unit, and processing an analog signal output from the unit pixel through a vertical signal line for each pixel column;
The column processing unit
Pass / fail information storage means for storing information on pass / fail of each analog circuit;
A solid-state imaging device comprising: selection means for selecting a normal analog circuit in place of a defective analog circuit among the analog circuits based on information stored in the pass / fail information storage means. The solid-state imaging device according to claim 1, wherein the analog circuit is a current source connected between one end of the vertical signal line and a reference potential node. The analog circuit outputs a pulse signal having a magnitude in the time axis direction corresponding to the magnitude of the pixel signal by comparing the analog pixel signal outputted from the unit pixel with a reference signal having a sloped waveform. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is a comparator. The column processing unit
A counter that counts the clock in the period of the pulse width of the pulse signal output from the comparator and converts the count value to a digital signal corresponding to the magnitude of the pixel signal corresponds to the pixel column of the pixel array unit The solid-state imaging device according to claim 3, wherein the solid-state imaging device has the same number. The analog circuit includes a current source connected between one end of the vertical signal line and a reference potential node, and compares the analog pixel signal output from the unit pixel with a reference signal having an inclined waveform. The solid-state imaging device according to claim 1, wherein the comparator outputs a pulse signal having a magnitude in the time axis direction corresponding to the magnitude of the pixel signal. The column processing unit
A counter that counts the clock in the period of the pulse width of the pulse signal output from the comparator and converts the count value to a digital signal corresponding to the magnitude of the pixel signal corresponds to the pixel column of the pixel array unit The solid-state imaging device according to claim 5, wherein the solid-state imaging device has the same number. 2. The solid state according to claim 1, wherein all pixel columns of the pixel array unit are divided into units of x pixel columns, and x + 1 analog circuits are provided for the x pixel columns for each block. Imaging device. The solid-state imaging device according to claim 1, wherein the quality information stored in the quality information storage unit is input from an external storage device when a system in which the solid-state imaging device is mounted is activated. For each pixel column of the pixel array unit, a test circuit that includes a source follower transistor and a selection transistor and is connected to the vertical signal line,
At the time of the test for generating the pass / fail information stored in the pass / fail information storing means using the test circuit and the current source, a predetermined potential is input from the test circuit to the vertical signal line. 6. The solid-state imaging device according to claim 3, wherein the quality information obtained based on the comparison result of the comparator is stored in the quality information storage unit. A potential input circuit that inputs a predetermined potential to the vertical signal line for each pixel column of the pixel array unit;
In the test for generating the pass / fail information stored in the pass / fail information storage means, the predetermined potential is input to the vertical signal line from the potential input circuit, and based on the comparison result of the comparator at this time 6. The solid-state imaging device according to claim 2, wherein the obtained quality information is stored in the quality information storage unit. A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A solid-state device having a number of analog circuits greater than the number corresponding to the pixel columns of the pixel array unit, and a column processing unit that processes analog signals output from the unit pixels through vertical signal lines for each pixel column A method for driving an imaging apparatus,
A method for driving a solid-state imaging device, wherein a normal analog circuit is selected and used instead of a defective analog circuit among the analog circuits based on information on the quality of each analog circuit stored in advance. A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A solid-state device having a number of analog circuits greater than the number corresponding to the pixel columns of the pixel array unit, and a column processing unit that processes analog signals output from the unit pixels through vertical signal lines for each pixel column An imaging device;
An imaging apparatus comprising: an optical system that forms an image of incident light on an imaging surface of the solid-state imaging apparatus;
The column processing unit
Pass / fail information storage means for storing information on pass / fail of each analog circuit;
An imaging apparatus comprising: selection means for selecting a normal analog circuit in place of a defective analog circuit among the analog circuits based on information stored in the pass / fail information storage means.

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