JP2011188036A - Solid-state image sensor and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image sensor, along with an imaging apparatus, capable of creating a comparator groups which concurrently operate and comparator groups which operate after the concurrent operation. <P>SOLUTION: The solid-state image sensor includes: a pixel array part 11 in which unit pixels 20 including photoelectric conversion elements are arranged like a matrix; a plurality of comparators 31 which are provided according to pixel columns of the pixel array part 11 and compare analog signals to be output from the unit pixels 20 through a vertical signal line 21 with a reference signal Vramp whose level gradually changes; a plurality of counters 32 which are provided for every comparator 31 and perform count operations on the basis of comparison results of the comparators 31; and a voltage supply part 19 which applies two or more kinds of voltage to the vertical signal line 21 provided according to the pixel columns of the pixel array part 11. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging device, and more particularly to a solid-state imaging device represented by a CMOS image sensor and an imaging device including the same.

  In recent years, a CMOS image sensor has attracted attention as a solid-state imaging device that replaces a CCD image sensor. This is because the CCD image sensor requires a dedicated process, requires a plurality of power supply voltages for its operation, and needs to be operated in combination with a plurality of peripheral ICs. This is because the CMOS image sensor overcomes this problem.

  That is, a CMOS image sensor can be manufactured by using a manufacturing process similar to that of a general CMOS integrated circuit, and can be driven by a single power source. Furthermore, since the CMOS image sensor can mix analog circuits and logic circuits using a CMOS process in the same chip, the number of peripheral ICs can be reduced. As described above, the CMOS image sensor has a plurality of great advantages as compared with the CCD image sensor.

  The output circuit of a CCD image sensor is mainly a 1-channel (ch) output using an FD amplifier having a floating diffusion layer (FD: Floating Diffusion). On the other hand, the CMOS image sensor has an FD amplifier for each unit pixel, and its output is a column parallel output type in which one row in the pixel array unit is selected and read out in the column direction at the same time. Is the mainstream. This is because it is difficult to obtain a sufficient driving capability with an FD amplifier arranged in a unit pixel, and therefore it is necessary to lower the data rate, and parallel processing is advantageous.

  Various pixel signal readout circuits for this column parallel output type CMOS image sensor have been proposed. One of the most advanced forms is an analog-digital converter (hereinafter referred to as an ADC (Analog digital converter) for each column. )), And a pixel signal is extracted as a digital signal (see, for example, Patent Document 1).

  An example of a CMOS image sensor equipped with such a column-parallel ADC is shown in FIG.

  As shown in FIG. 7, the solid-state imaging device 100 includes a pixel array unit 110 serving as an imaging unit, a column signal processing unit group 130, a RAMP signal generation circuit 140, an amplifier circuit (S / A) 150, and a signal processing circuit 160. Have.

  The pixel array unit 110 includes unit pixels 111 including photodiodes and in-pixel amplifiers arranged in a matrix (matrix). In the solid-state imaging device 100, as a control circuit for sequentially reading signals from the unit pixels 111, a timing control circuit 170 that generates an internal clock, a vertical scanning unit 180 that controls row addresses and row scanning, a column address and column A horizontal scanning unit 190 that controls scanning is arranged.

  In the column signal processing unit group 130, ADCs 131 including a comparator 132, a counter 133, and a latch 134 are arranged for each vertical signal line 144, and each ADC 131 has an n-bit digital signal conversion function. Note that the vertical signal lines 144 are provided in units of pixel columns of the pixel array unit 110.

  The RAMP signal generation circuit 140 outputs a reference signal Vramp that is a ramp waveform (a slope waveform in which the voltage level gradually changes linearly with a certain slope) in which the voltage level is changed stepwise. The comparator 132 compares the voltage of the reference signal Vramp with the voltage Vsl of the analog signal obtained from the unit pixel via the vertical signal line 144 for each row line. At this time, the counter 133 disposed for each pixel column is operating similarly to the comparator 132, and the reference signal Vramp, which is a ramp waveform, and the counter value change while taking a one-to-one correspondence, thereby causing the vertical signal line 144 to change. The voltage (analog signal) Vsl is converted into a digital signal.

  The change in the reference signal Vramp is to convert a change in voltage into a change in time, and to convert the change into a digital value by counting the time in a certain period (clock). When the analog signal voltage Vsl and the reference signal Vramp voltage cross, the output of the comparator 132 is inverted, the input clock of the counter 133 is stopped, and AD conversion is completed. After the above AD conversion period, the data held in each latch 134 is input to the signal processing circuit 160 through the horizontal transfer line 145 and the amplifier circuit 150 by the horizontal scanning unit 190, and a two-dimensional image is generated. In this way, column parallel output processing is performed. The horizontal transfer line 145 is, for example, a transfer bus having a 2n-bit width, and 2n amplifier circuits 150 are provided corresponding to the horizontal transfer lines 145.

JP-A-2005-278135

  However, the comparator of the conventional CMOS image sensor compares the common reference signal Vramp and the voltage Vsl of the signal from the unit pixel of each pixel column, and the value of the analog signal voltage Vsl Comparator may operate all at once. At this time, the analog power supply fluctuation due to the IR drop becomes large, and there is a possibility that the adjacent comparator or the operating comparator itself may malfunction due to noise via the power supply.

  In order to confirm the influence of such comparator malfunctions, conventionally, a CMOS image sensor picks up a predetermined image, and among the comparators of the column signal processing unit group, a first comparator group whose outputs are simultaneously inverted Thereafter, a second comparator group whose output is inverted is created. Then, the operation effect of the first comparator group that performs the inverting operation all at once is confirmed through the imaging result at that time to affect the second comparator group that performs the inverting operation thereafter.

  For example, an imaging image 200 as shown in FIG. The imaging image 200 is provided with an image region for performing a reversal operation all at once and an image region for confirming the influence of the simultaneous reversal operation by performing a reversal operation thereafter. As shown in FIG. 8B, the imaging image 200 is superimposed on the pixel portion of the CMOS image sensor and is imaged by the CMOS image sensor. Then, the influence of malfunction is confirmed based on the imaging result when the CMOS image sensor is used. When the imaging result at this time is, for example, as shown in FIG. 8C, a partial region is an image different from the imaging image 200, the operation result of the first comparator group is the second comparator group. It will have an influence on. This is because the comparator of the second comparator group performing the comparison operation malfunctions due to noise generated when the outputs of the comparators 132 of the first comparator group are simultaneously inverted.

  When comparing this effect between CMOS image sensors, in order to perform a strict effect comparison, the first comparator group and the second comparator group must be the same between CMOS image sensors. The same can be said about the reproducibility of measurement.

  However, since the pixel portion has been downsized, the interval between the pixels is extremely narrow, and it is difficult to align the CMOS image sensor with a precision in units of pixel columns on a predetermined image.

  Accordingly, an object of the present invention is to provide a solid-state imaging device and an imaging device capable of creating a group of comparators that operate simultaneously and a group of comparators that operate thereafter.

  In order to achieve the above object, the invention according to claim 1 is provided corresponding to a pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix, and a pixel column of the pixel array unit, A plurality of comparators that compare an analog signal output from the unit pixel through a vertical signal line with a reference signal whose voltage level gradually changes, and a plurality of comparators that are provided for each of the comparators and that perform a counting operation based on the comparison result of the comparator And a voltage supply unit that applies two or more kinds of voltages to the vertical signal lines provided corresponding to the pixel columns of the pixel array unit.

  According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the voltage supply unit selectively applies the two or more types of voltages for each of the vertical signal lines. And

  The invention according to claim 3 is the solid-state imaging device according to claim 2, wherein the voltage supply unit can switch the voltage applied to each of the vertical signal lines every predetermined period. To do.

  The invention according to claim 4 includes a solid-state image sensor, and the solid-state image sensor includes a pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix, and a pixel column of the pixel array unit. Correspondingly provided, a plurality of comparators for comparing analog signals output from the unit pixels through vertical signal lines with reference signals whose levels gradually change, and provided for each comparator, based on the comparison result of the comparators The imaging device includes a plurality of counters that perform a counting operation and a voltage supply unit that applies two or more types of voltages to the vertical signal lines provided corresponding to the pixel columns of the pixel array unit.

  According to the present invention, by applying two or more kinds of voltages from the voltage supply unit to the vertical signal line, it is possible to create a comparator group that operates simultaneously and a comparator group that operates thereafter. Therefore, compared with the case where a predetermined image is prepared and captured, the accuracy and reproducibility can be improved in measuring the simultaneous operation effect of the comparator.

It is a figure which shows the structure of the imaging device which concerns on one Embodiment of this invention. It is a figure which shows the structure of the solid-state image sensor which concerns on one Embodiment of this invention. It is explanatory drawing of AD conversion processing. It is a figure which shows the specific structure of the voltage supply part shown in FIG. It is a figure which shows the timing of inspection mode. It is a figure which shows the example of the output image of test | inspection mode. It is a figure which shows the structure of the conventional solid-state image sensor. It is a figure for demonstrating the measuring method of the simultaneous operation influence of the conventional comparator.

Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described. The description will be given in the following order.
1. Overall overview 2. Configuration of imaging device Configuration and operation of solid-state image sensor

[1. Overall overview]
The imaging apparatus according to the present embodiment includes a solid-state imaging device. In the solid-state imaging device, unit pixels including photoelectric conversion elements that convert incident light into signal charges are arranged in a matrix, and a predetermined number of pixel columns. This is a CMOS image sensor having a pixel array section in which vertical signal lines are respectively wired.

  This solid-state image sensor is a CMOS image sensor equipped with a column parallel ADC, and is provided for each of a plurality of comparators for comparing an analog signal output from a unit pixel through a vertical signal line with a reference signal whose level gradually changes. And a plurality of counters that perform a counting operation based on the comparison result of the comparator.

  A voltage supply unit that applies two or more kinds of voltages to the vertical signal lines provided corresponding to the pixel columns of the pixel array unit is provided.

  As described above, in the solid-state imaging device according to the present embodiment, by applying two or more kinds of voltages from the voltage supply unit to the vertical signal line, the first comparator group that operates simultaneously and the other comparator groups are created. be able to. Therefore, compared with the case where a predetermined image is prepared and captured, the accuracy and reproducibility can be improved in measuring the simultaneous operation effect of the comparator.

  Further, the voltage supply unit is configured so that two or more kinds of voltages can be selectively applied to each vertical signal line, so that the first comparator group that operates simultaneously and the other second comparator group. Can be freely created, and the degree of freedom in setting the situation can be improved for the measurement of the simultaneous operation effect of the comparator.

  The voltage supply unit is configured so that the voltage applied to each vertical signal line can be switched every predetermined period, so that the first comparator group and the second comparator group can be sequentially changed, and the situation setting is continuously changed. Thus, the simultaneous operation effect of the comparator can be measured.

  Hereinafter, specific examples of the imaging device and the solid-state imaging device in the present embodiment will be described with reference to the drawings.

[2. Configuration and operation of imaging equipment]
First, the configuration of the imaging device in the present embodiment will be described with reference to the drawings.

  As shown in FIG. 1, the imaging device 1 includes a solid-state imaging device 2, a signal processing circuit 3, a system controller 4, an input unit 5, and an optical block 6. The imaging device 1 is provided with a driver 7 for driving a mechanism in the optical block 6, a timing generator (TG) 8 for driving the solid-state imaging device 2, and the like. The solid-state image sensor 2 is a CMOS image sensor.

  The optical block 6 includes a lens for condensing light from the subject onto the solid-state imaging device 2, a drive mechanism for moving the lens to perform focusing and zooming, a mechanical shutter, a diaphragm, and the like. The driver 7 controls the driving of the mechanism in the optical block 6 in accordance with a control signal from the system controller 4.

  The solid-state imaging device 2 is driven based on the timing signal output from the TG 8 and converts incident light from the subject into an electrical signal. The TG 8 outputs a timing signal under the control of the system controller 4.

  The signal processing circuit 3 executes various camera signal processing such as AF (Auto Focus), AE (Auto Exposure), detection processing and correction processing of defective pixels, white balance adjustment, matrix processing, etc. on the digital signal from the solid-state imaging device 2. To do.

  The system controller 4 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The CPU executes the programs stored in the ROM, thereby controlling the respective units of the imaging device 1 in an integrated manner and executing various calculations for the control. The input unit 5 includes operation keys, dials, levers, and the like that receive user operation inputs, and outputs a control signal corresponding to the operation inputs to the system controller 4.

  The image data output from the signal processing circuit 3 is supplied to a graphic interface circuit (not shown) and converted into a display image signal, whereby a camera-through image is displayed on a monitor (not shown). When the system controller 4 is instructed to record an image by a user input operation to the input unit 5 or the like, the image data from the signal processing circuit 3 is supplied to a CODEC (enCOder, DEcoder) and compressed and encoded. The processing is performed and recorded on the recording medium. When recording a still image, the signal processing circuit 3 supplies one frame of image data to the CODEC, and when recording a moving image, the processed image data is continuously supplied to the CODEC. .

[3. Configuration of solid-state imaging device 2]
Next, the configuration of the solid-state imaging device 2 according to the present embodiment will be described with reference to the drawings.

  As shown in FIG. 2, the solid-state imaging device 2 includes a pixel array unit 11, a vertical scanning unit 12, a column signal processing unit group 13, a horizontal scanning unit 14, an output unit 15, a timing control circuit 16, and a RAMP. The signal generation circuit 17 and the signal processing circuit 18 are included. The semiconductor substrate 10 is made of, for example, a silicon substrate. The vertical scanning unit 12, the horizontal scanning unit 14, and the timing control circuit 16 function as a control unit that controls the pixel array unit 11 and the column signal processing unit group 13.

The pixel array unit 11 constitutes an imaging region, unit pixels 20 including photoelectric conversion units that convert incident light into signal charges are arranged in a matrix (m rows × n columns), and a vertical signal line 21 for each pixel column. _{1 to} 21 _n are wired.

  The timing control circuit 16 is controlled by a control device outside the solid-state image pickup device 2 to generate a clock signal, a control signal, and the like that serve as a reference for operations of the vertical scanning unit 12, the column signal processing unit group 13, the horizontal scanning unit 14, and the like. To do. The timing control circuit 16 inputs the control signal thus generated to the vertical scanning unit 12, the column signal processing unit group 13, the horizontal scanning unit 14, and the like.

The vertical scanning unit 12 is configured by a shift register, for example. The vertical scanning unit 12 outputs row transfer signals φTRG1 to φTRGm and row selection signals φSEL1 to φSELm to selectively scan each unit pixel 20 of the pixel array unit 11 in the vertical direction sequentially in units of rows. As a result, pixel signals based on signal charges generated in accordance with the amount of received light in the photoelectric conversion units of the unit pixels 20 are supplied to the column signal processing unit group 13 through the vertical signal lines 21 _{1 to} 21 _n . Further, the vertical scanning unit 12 resets the unit pixels 20 by supplying row reset signals φRST1 to φRSTm that are commonly applied to the unit pixels 20 of each row. A constant current source 26 is connected between the vertical signal lines 21 _{1 to} 21 _n and the ground.

The column signal processing unit group 13 includes a plurality of column signal processing units 30 ₁ to 30 _n arranged corresponding to the pixel columns (for each column) of the pixel array unit 11. Each of the column signal processing units 30 ₁ to 30 _n outputs a digital signal corresponding to the voltage of the signal output from each unit pixel 20. Specifically, the column signal processing units 30 ₁ to 30 _n convert the analog output of the pixel array unit 11 into digital signals by performing APGA-compatible integral AD conversion and digital CDS using the reference signal Vramp. Output.

  The horizontal scanning unit 14 is configured by, for example, a shift register, and sequentially outputs column scanning pulses to output a signal subjected to signal processing by the column signal processing unit group 13 from the column signal processing unit group 13 to the horizontal signal line 40. . The output unit 15 performs predetermined signal processing and outputs the signals sequentially supplied from the column signal processing unit group 13 through the horizontal signal line 40.

As shown in FIG. 2, the column signal processing units 30 ₁ to 30 _n include a comparator 31, a counter 32, and a latch 33. The comparator 31 compares the signal output from the unit pixel 20 of the pixel array unit 11 with the reference signal Vramp whose value changes stepwise, and inverts the output when the magnitude relationship is switched. The reference signal Vramp is a ramp signal having a slope waveform that changes in level and changes linearly with a certain slope, and is generated by the RAMP signal generation circuit 17. The counter 32 counts a comparison time that is an amount of time for which the magnitude relationship between the signal output from the pixel array unit 11 and the reference signal Vramp is switched. The counter 32 and the latch 33 constitute analog-digital conversion means. The latch 33 holds the count result of the comparison time by the counter 32. The output of each latch 33 is connected to the horizontal signal line 40, and the signal output from each latch 33 is subjected to predetermined signal processing and output from the signal processing circuit 18.

The signals read from the unit pixels 20 on the vertical signal lines 21 _{1 to} 21 _n provided for each column of the pixel array unit 11 are compared with the reference signal Vramp by the comparator 31. At this time, the counter 32 arranged for each column is operating similarly to the comparator 31, and the vertical signal line 21 ₁ is changed by changing the voltage of the reference signal Vramp and the counter value of the counter 32 in a one-to-one correspondence. The signal read out to 21 _n is digitally converted. That is, the change in the voltage of the reference signal Vramp is to convert the change in voltage into a change in time, and the time is counted by a counter 32 at a certain period (clock), and converted into a digital value. When the signals read out to the vertical signal lines 21 _{1 to} 21 _n intersect with the reference signal Vramp, as shown in FIG. 3, the output of the comparator 31 is inverted, the input clock of the counter 32 is stopped, and the counter The count value of 32 is held in the latch 33. Thereby, analog-digital conversion is completed.

  After the above analog-digital conversion period is completed, the data held in each latch 33 is transferred to the horizontal signal line 40 by the horizontal scanning unit 14 and input to the signal processing circuit 18 via the output unit 15. The signal processing circuit 18 performs predetermined signal processing on the output of the output unit 15 to generate a two-dimensional image. In this case, the signal processing circuit 18 performs, for example, digital signal processing such as correction of vertical line defects and point defects, signal clamping, parallel-serial conversion, compression, encoding, addition, averaging, intermittent operation, and the like. Can do.

  The solid-state imaging device 2 according to the present embodiment further includes a voltage supply unit 19 that applies two or more kinds of voltages to the vertical signal lines 21 provided corresponding to the pixel columns of the pixel array unit 11.

  The voltage supply unit 19 includes a first power supply 41 that generates the first voltage V1 and a second power supply 42 that generates the second voltage V2. The first power supply 41 determines the voltage value of the first voltage V1. The second power source 42 is configured to be able to change the voltage value of the second voltage V2.

The vertical signal lines 21 _{1 to} 21 _n are connected to first output circuits 43 ₁ to 43 _n that output the first voltage V1 and second output circuits 44 _{1 to} 44 _n that output the second voltage V2. ing. The voltage supply unit 19 applies the first voltage V1 or the second voltage V2 to the vertical signal lines 21 _{1 to} 21 _n based on the output signals Vsel _{1 to} Vsel _n from the horizontal scanning unit 14. Selection circuits 45 _{1 to} 45 _n are provided for selecting whether or not. The vertical signal lines 21 _{1 to} 21 _n are collectively referred to as the vertical signal line 21, the first output circuits 43 ₁ to 43 _n are collectively referred to as the first output circuit 43, and the second output circuits 44 _{1 to} 44 _n are In some cases, the second output circuit 44 is collectively referred to, and the selection circuits 45 _{1 to} 45 _n are collectively referred to as the selection circuit 45. Further, the output signals Vsel _{1 to} Vsel _n may be collectively referred to as an output signal Vsel.

  The selection circuit 45 is in a non-selection operation state in which a voltage to be applied to the vertical signal line 21 is not selected or a selection operation state in which a voltage to be applied to the vertical signal line 21 is selected according to the control signal Psel output from the vertical scanning unit 12. , Either state. That is, an inspection mode in which the vertical scanning unit 12 applies the first or second voltage V1, V2 to the vertical signal line 21, and a pixel on the vertical signal line 21 without applying the first or second voltage V1, V2. One of the normal mode for outputting a signal from the unit pixel 20 of the array unit 11 is selected.

  Here, a specific configuration of the voltage supply unit 19 is shown in FIG. Note that some of the first output circuit 43, the second output circuit 44, and the selection circuit 45 are illustrated in the drawing configuration.

  As shown in FIG. 4, the first output circuit 43 includes cascode-connected MOS transistors Tr1 and Tr2, and the first voltage V1 is input from the first power supply 41 to the gate of the MOS transistor Tr1. The gate of the MOS transistor Tr2 is connected to the selection circuit 45, and the ON / OFF of the MOS transistor Tr2 is controlled by the selection circuit 45. The source of the MOS transistor Tr2 is connected to the vertical signal line 21, and when the MOS transistor Tr2 is turned on, the first output circuit 43 applies the first voltage V1 to the vertical signal line 21 as a source follower circuit.

  The second output circuit 44 includes cascode-connected MOS transistors Tr3 and Tr4, and the second voltage V2 is input from the second power supply 42 to the gate of the MOS transistor Tr3. The gate of the MOS transistor Tr4 is connected to the selection circuit 45, and the ON / OFF of the MOS transistor Tr4 is controlled by the selection circuit 45. The source of the MOS transistor Tr4 is connected to the vertical signal line 21, and when the MOS transistor Tr4 is turned on, the second output circuit 44 applies the second voltage V2 to the vertical signal line 21 as a source follower circuit.

  The selection circuit 45 includes two AND circuits and one inverter circuit. A control signal Psel output from the power supply selection circuit 50 of the vertical scanning unit 12 is input to one input of the two AND circuits. The other input of one AND circuit receives the output signal Vsel from the FF of the horizontal scanning unit 14, and the output is connected to the gate of the MOS transistor Tr 2 of the first output circuit 43. Further, the RAMP signal generation circuit 17 is connected to the other input of the other AND circuit and the reference signal Vramp is input, and the gate of the MOS transistor Tr4 of the second output circuit 44 is connected to the output.

  When the control signal Psel is in an active state (H level voltage) and the output signal Vsel is at the H level, the first voltage V1 is applied from the first output circuit 43 to the vertical signal line 21. On the other hand, when the control signal Psel is active and the output signal Vsel is at the L level, the second voltage V2 is applied from the second output circuit 44 to the vertical signal line 21. When the control signal Psel is in an inactive state (L level voltage), the first voltage V1 and the second voltage V2 are not applied to the vertical signal line 21 from the first and second output circuits 43 and 44.

  As described above, the voltage supply unit 19 includes two source follower circuits for each vertical signal line 21, and the first power supply 41 and the second power supply 42 generate the first voltage V <b> 1 and the second voltage V <b> 2. One of the two source follower circuits is connected to the vertical signal line 21 so that the first voltage V1 or the second voltage V2 can be applied to the vertical signal line 21 independently. Further, the selection by the selection circuit 45 is disabled by the control signal Psel output from the vertical scanning unit 12, and the two source follower circuits can be prevented from being connected to the vertical signal line 21.

  The horizontal scanning unit 14 is composed of n flip-flops FF connected in series. The output signal Vsel output from the horizontal scanning unit 14 can select whether to apply the first voltage V1 or the second voltage V2 to the vertical signal line 21 as described above. . In this way, the voltage applied to the vertical signal line 21 can be selected using the n flip-flops FF of the horizontal scanning unit 14 used when reading the signal from the unit pixel 20. Suppressing the increase in scale.

  An operation in the inspection mode of the solid-state imaging device 2 configured as described above will be specifically described with reference to a timing chart of FIG.

  As shown in FIG. 5, in the inspection mode, the image signal for one line is output from the solid-state imaging device 2 with three horizontal synchronization timings as one cycle. That is, (A) horizontal scanning unit FF setting period, (B) AD conversion period by source follower setting, (C) one row AD conversion result output period is set as one cycle, and image signals for one line are output. An image for one frame is output by executing the processing for each frame of the one frame.

First, during timing t1 to t2, a signal for setting the output of each flip-flop FF of the horizontal scanning unit 14 is output from the timing control circuit 16 to shift the value of each flip-flop FF. Thus, the output of the flip-flop FF is set to either the H level or the L level. Thus, the selection circuits 45 _{1 to} 45 _n can be controlled to a predetermined state by the output signals Vsel _{1 to} Vsel _n .

  Next, by activating the control signal Psel output from the vertical scanning unit 12 between timings t <b> 2 and t <b> 3, a voltage corresponding to each output signal Vsel (first voltage V <b> 1 or A second voltage V2) is applied to the vertical signal line 21. The comparator 31 compares the voltage applied to the vertical signal line 21 with the reference signal Vramp. At this time, the counter 32 arranged for each column is operating similarly to the comparator 31, and the vertical signal line 21 is changed by changing the voltage of the reference signal Vramp and the counter value of the counter 32 in a one-to-one correspondence. Digitally convert the read signal. When the signal read to the vertical signal line 21 and the reference signal Vramp intersect, the output of the comparator 31 is inverted, the input clock of the counter 32 is stopped, and the count value of the counter 32 is held in the latch 33. Complete analog-to-digital conversion.

  Next, between the timings t3 and t4, the data held in each latch 33 is input to the signal processing circuit 18 via the horizontal signal line 40 and the output unit 15, and subjected to predetermined signal processing to perform signal processing. It is output from the circuit 18 as an image signal for one line.

  Thereafter, processing similar to the processing from timing t4 to timing t1 to t4 is repeatedly performed, and an image for one frame is output.

  In the above “(B) AD conversion period by source follower setting”, the voltage settings of some of the source follower circuits are set so that the AD conversion result is at a low level (pixels have low luminance), and the remaining source follower circuits Is set so that the AD conversion result is at a high level (pixels have high luminance). By making the first voltage V1 higher than the second voltage V2 and applying the first voltage V1 from the first output circuit 43 to the vertical signal line 21, the AD conversion result becomes a high level. At this time, the second voltage V2 is lower than the first voltage V1, and by applying the second voltage V2 from the output circuit 43 to the vertical signal line 21, the AD conversion result becomes a low level.

  For example, as shown in FIG. 6A, it is set so that the center pixel has a low luminance and the surrounding luminance is high, or as shown in FIG. Can be set so as to produce an image with a low brightness and other high brightness. At this time, the outputs of the comparators 31 connected to the vertical signal line 21 to which the voltage at which the AD conversion result is at a low level are applied are simultaneously inverted. Thereafter, the output of the comparator 31 connected to the vertical signal line 21 to which a voltage at which the AD conversion result is at a high level is applied is output. At this time, if the output of the comparator 31 connected to the vertical signal line 21 to which the voltage at which the AD conversion result is at a high level is applied does not become a value corresponding to the voltage applied to the vertical signal line 21, It can be determined that there is an influence from the comparators 31 operating simultaneously.

  Further, as shown in FIG. 6 (c), it is set so that the center pixel has a high luminance and the surrounding luminance is low, or as shown in FIG. The image may be set so as to be an image with a high brightness and other low brightness.

  The voltage supply unit 19 is configured to be able to switch the voltage applied to each vertical signal line 21 every predetermined period, and various images other than the images shown in FIGS. 6A to 6D. It is possible to measure the influence of simultaneous operation with higher accuracy.

  As described above, in the solid-state imaging device 2, it is possible to create the first comparator group that operates simultaneously in units of pixel columns and the comparator group that operates thereafter. Therefore, compared with the case where a predetermined image is prepared and captured, the accuracy and reproducibility can be improved in measuring the simultaneous operation effect of the comparator.

  Although some of the embodiments of the present invention have been described in detail with reference to the drawings, these are exemplifications, and the present invention is implemented in other forms with various modifications and improvements based on the knowledge of those skilled in the art. Is possible.

DESCRIPTION OF SYMBOLS 1 Imaging device 2 Solid-state image sensor 11 Pixel array part 12 Vertical scanning part 13 Column signal processing part group 14 Horizontal scanning part 19 Voltage supply part 41 1st power supply 42 2nd power supply 43 1st output circuit 44 2nd output circuit 45 Selection circuit Tr1-Tr4 MOS transistors

Claims (4)

A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A plurality of comparators that are provided corresponding to the pixel columns of the pixel array unit and that compare analog signals output from the unit pixels through vertical signal lines with reference signals whose voltage levels gradually change;
A plurality of counters provided for each of the comparators, and performing a counting operation based on a comparison result of the comparators;
A solid-state imaging device comprising: a voltage supply unit that applies two or more kinds of voltages to the vertical signal lines provided corresponding to the pixel columns of the pixel array unit. The solid-state imaging device according to claim 1, wherein the voltage supply unit selectively applies the two or more types of voltages for each of the vertical signal lines.   The solid-state imaging device according to claim 2, wherein the voltage supply unit can switch a voltage applied to each of the vertical signal lines every predetermined period. Equipped with a solid-state image sensor,
The solid-state imaging device is
A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A plurality of comparators that are provided corresponding to the pixel columns of the pixel array unit and that compare analog signals output from the unit pixels through vertical signal lines with reference signals whose levels gradually change;
A plurality of counters provided for each of the comparators, and performing a counting operation based on a comparison result of the comparators;
An imaging apparatus comprising: a voltage supply unit that applies two or more types of voltages to the vertical signal lines provided corresponding to the pixel columns of the pixel array unit.