CN103985789B - A kind of preparation method of efficient P type crystalline silicon grooving and grid burying battery - Google Patents

A kind of preparation method of efficient P type crystalline silicon grooving and grid burying battery Download PDF

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CN103985789B
CN103985789B CN201410219780.9A CN201410219780A CN103985789B CN 103985789 B CN103985789 B CN 103985789B CN 201410219780 A CN201410219780 A CN 201410219780A CN 103985789 B CN103985789 B CN 103985789B
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battery
silicon
film
silicon nitride
composite membrane
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CN103985789A (en
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孙海平
高艳涛
邢国强
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Altusvia Energy Taicang Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441Electrode arrangements specially adapted for back-contact solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
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    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
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Abstract

The invention discloses a kind of preparation method of efficient P type crystalline silicon grooving and grid burying battery, its technological process comprises: P type silicon substrate monocrystalline silicon lbg, making herbs into wool to its cleaning, front diffuses to form PN junction, selective emitter forms and goes back of the body knot and phosphorosilicate glass, double-sided coating, back side regional area is opened film and electrode fabrication, this preparation method is by adopting grooving and grid burying to add selective emitter junction, when improving front light-receiving area, reduce the contact resistance of metal material, back side employing thin film passivation technology replaces full aluminium back surface field and has fully reduced the compound of the back side and improved back side transmitting, triplicity has reduced by two surperficial optics and electricity loss effectively, and this preparation method has not only overcome the caducous problem of prior art electrode, also high with current enterprise production line compatibility, fully reduce equipment investment.

Description

A kind of preparation method of efficient P type crystalline silicon grooving and grid burying battery
Technical field
The present invention relates to solar cell and manufacture field, specifically the grooving and grid burying technology of the positive low surface concentration of crystal silicon solar energy battery and back of the body passivating technique.
Background technology
Modernization solar cell industryization is produced towards high efficiency, low cost future development, and front selective emitter junction adds grooving and grid burying technology and combines as the representative of high efficiency, low cost developing direction with back of the body passivating technique, it is advantageous that:
(1) to have metal grid lines shading-area little for this technology of grooving and grid burying, and high current is collected area;
(2) selective emitter junction technology has reduced the contact resistance of metal grid lines and silicon substrate material effectively, and the absorption of the light area (non-metallic region) of having improved battery to short-wave band light;
(3) superior passivating back technology: because the good passivation of back side deielectric-coating reduces the recombination velocity of back surface field, meanwhile, the interior back reflection effect of back side deielectric-coating, increases the absorption of cell backside to longwave optical.
(4) electrode has on the basis of high electrical conductivity, has good adhesion with material, meets the reliability testing requirement in practical application
The present invention is based on grooving and grid burying technology, selective emitter junction technology and back of the body passivating technique have been proposed to the high-efficiency crystal silicon method for manufacturing solar battery in conjunction with three kinds of technology.
Summary of the invention
Goal of the invention: for the problems referred to above, the object of the invention is can volume production grooving and grid burying to add for low cost the crystal silicon solar batteries preparation method's that selective emitter junction is combined with back of the body passivating technique shortage, the preparation method who proposes a kind of efficient P type crystalline silicon grooving and grid burying battery, has solved technological gap.
Technical scheme: the preparation method of a kind of efficient P type crystalline silicon grooving and grid burying battery of the present invention, concrete steps comprise:
(a): the one-side gaining of P type silicon substrate monocrystalline silicon laser
Selecting resistivity is the P type silicon chip of 0.3 cm ~ 10 cm, and the pulse energy of laser is at 0.05uJ ~ 0.8uJ, and frequency is under the condition of 50KHz ~ 5000KHz, adopt ns laser instrument at substrate one side fluting, groove width is 5um ~ 50um, is 5um ~ 100um deeply, and distance between centers of tracks is 0.5mm ~ 1.5mm;
(b): making herbs into wool to its cleaning
The sodium hydroxide solution that is 0.5% ~ 2% by concentration carries out chemical attack to p type single crystal silicon surface in the time of 75 DEG C ~ 80 DEG C, prepare leg-of-mutton light trapping structure matte, then the hydrochloric acid that is 10% ~ 12% by concentration and concentration are after 8% ~ 10% hydrofluoric acid mixes, matte to be cleaned, and remove surface impurity;
(c): front diffuses to form PN junction
In temperature is the diffusion furnace of 600-900 DEG C, adopt POCl3Carry out phosphorus diffusion, the diffusingsurface sheet resistance that makes P type crystalline silicon is 20-90ohm/sq; Or first injecting phosphorus source at cutting face, is that 15keV, Implantation amount are 105cm at ion beam energy-2After, then anneal in temperature is the annealing furnace of 800-1000 DEG C, the P type crystalline silicon sheet resistance after annealing is 20-90ohm/sq;
(d): selective emitter forms and go back of the body knot and phosphorosilicate glass
Spraying width with shower nozzle at fluting position is 5 μ m ~ 70 μ m masks, again in the equipment of one side etching, the hydrofluoric acid that is 8% ~ 10% by concentration and concentration are after 35% ~ 40% nitric acid mixes, the back side of etching silicon wafer and side at normal temperatures, then the hydrofluoric acid that is 7% ~ 12% by concentration and concentration are that 35% ~ 40% nitric acid mixed solution corrodes the cutting face of silicon chip in the time that temperature is 2 DEG C ~ 10 DEG C, making without the sheet resistance of mask regions is 70 ~ 150ohm/sq, then remove mask and surperficial phosphorosilicate glass, finally dry again;
(e) double-sided coating
Front plates the silicon nitride film that thickness is 50nm ~ 100nm, and the back side plates the composite membrane that thickness is 50nm ~ 100nm;
(f) back side regional area is opened film
Adopt laser means to open film to the back side, remove composite film, the figure of opening film is that aperture is the circle of 50um ~ 400um, or the width line that is 20 ~ 200um, and opening film rate is 50% ~ 90%, after opening film and completing to its cleaning oven dry; Or print overleaf Merck BES slurry and remove the method for the composite film in this region and open film, the figure of opening film is that aperture is the circle of 50um ~ 400um, or the width line that is 20 ~ 200um, opening film rate is 50% ~ 90%, after completing to its cleaning oven dry;
(g) electrode fabrication
The method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 5um ~ 60um, height is the negative pole that the 17F of the Du Pont slurry of 5um ~ 100um or the 18A of Du Pont slurry form battery, then in temperature is the sintering furnace of 400 DEG C ~ 800 DEG C, carries out common burning; Or the method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 5um ~ 60um, height is the negative pole that the nickel dam of 1um ~ 100um forms battery, in temperature is the sintering furnace of 400 DEG C ~ 800 DEG C, carry out common burning, after sintering, paste with conducting resinl the copper strips that one deck width is 5um ~ 200um in negative terminal surface again; Or the method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 5um ~ 60um, height is the negative pole that the nickel dam of 1um ~ 100um forms battery, in being the sintering furnace of 400 DEG C ~ 800 DEG C, temperature carries out common burning, after sintering, cell piece is plated one deck and is risen the copper layer of electric action on nickel dam by the mode of electroplating, or play the copper layer of electric action by method spray printing one deck on nickel dam of inkjet printing, the thickness of copper layer is 5um ~ 30um, and width is 5um ~ 90um.
Diffusingsurface described in step c and cutting face are positioned at the same side.
The width of the mask described in steps d is more than or equal to the width of PN junction one side groove.
Composite membrane described in step e and step f is silica and silicon nitride composite membrane, aluminium oxide and silicon nitride composite membrane, any one in silica, aluminium oxide and silicon nitride composite membrane, described silica and silicon nitride composite membrane are on the basis of silicon oxide film, grow one deck silicon nitride film formation silica and silicon nitride composite membrane; Aluminium oxide and silicon nitride composite membrane are on the basis of pellumina, grow one deck silicon nitride film formation aluminium oxide and silicon nitride composite membrane; Aluminium oxide, silica and silicon nitride composite membrane are one deck silicon oxide film of growing on the basis of pellumina, and then one deck silicon nitride film of growing on the basis of silicon oxide film forms aluminium oxide, silica and silicon nitride composite membrane.
In step g, the width of the pattern of inkjet printing is consistent with cutting width, and the height of the pattern of inkjet printing is more than or equal to the degree of depth of cutting.
Beneficial effect: compared with prior art, the preparation method of a kind of efficient P type crystalline silicon grooving and grid burying battery of the present invention, the positive grooving and grid burying that adopts adds selective emitter junction, when improving front light-receiving area, reduce the contact resistance of metal material, back side employing thin film passivation technology replaces full aluminium back surface field and has fully reduced the compound of the back side and improved back side transmitting, triplicity has reduced by two surperficial optics and electricity loss effectively, and improve the preparation method of electrode, make electrode greatly improve its adhesion having on higher electric conductivity basis, and high with current enterprise production line compatibility, fully reduce equipment investment.
Detailed description of the invention
The preparation method of a kind of efficient P type crystalline silicon grooving and grid burying battery that the present invention proposes, the step of its technological process comprises: the one-side gaining of P type silicon substrate monocrystalline silicon laser, making herbs into wool and to its clean, front diffuses to form PN junction, selective emitter forms and remove to carry on the back knot and phosphorosilicate glass, double-sided coating, back side regional area are opened film and electrode fabrication.
Embodiment 1
Selecting resistivity is the P type silicon chip of 0.3 cm, and the pulse energy of laser is at 0.05uJ, and frequency, under the condition of 50KHz, adopts ns laser instrument to slot according to negative electrode figure in substrate one side, and groove width is 5um, is 5um deeply, and distance between centers of tracks is 0.5mm.
The sodium hydroxide solution that is 0.5% by concentration carries out chemical attack to p type single crystal silicon surface in the time of 75 DEG C, prepare leg-of-mutton light trapping structure matte, then the hydrochloric acid that is 10% by concentration and concentration are after 8% hydrofluoric acid mixes, matte to be cleaned, and remove surface impurity.
Then in temperature is the diffusion furnace of 600 DEG C, adopt POCl3Carry out phosphorus diffusion, the diffusingsurface sheet resistance that makes P type crystalline silicon is 20ohm/sq, and described diffusingsurface and cutting face are positioned at the same side
Spraying width with shower nozzle at fluting position is 5 μ m masks, again in the equipment of one side etching, the hydrofluoric acid that is 8% by concentration and concentration are after 35% nitric acid mixes, the back side of etching silicon wafer and side at normal temperatures, then the hydrofluoric acid that is 7% by concentration and concentration are in the time that temperature is 2 DEG C, the cutting face of silicon chip to be corroded after 35% nitric acid mixes, making without the sheet resistance of mask regions is 70ohm/sq, then removes mask and surperficial phosphorosilicate glass, finally dries again.
Front plates silica and the silicon nitride composite membrane that thickness is 50nm, and the back side plates silica and the silicon nitride composite membrane that thickness is 50nm.
Adopt laser means to open film to the back side, remove silica and silicon nitride composite film, the figure of opening film is that aperture is the circle of 100um, and opening film rate is 50%, after opening film and completing to its cleaning oven dry.
The method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 5um, height is that the 17F of the Du Pont slurry of 5um forms the negative pole of battery, then in temperature is the sintering furnace of 400 DEG C, carries out common burning.
Embodiment 2
Selecting resistivity is the P type silicon chip of 1.5 cm, and the pulse energy of laser is at 0.5uJ, and frequency, under the condition of 3000KHz, adopts ns laser instrument to slot according to negative electrode figure in substrate one side, and groove width is 30um, is 50um deeply, and distance between centers of tracks is 1mm.
Sodium hydroxide solution with 0.55% carries out chemical attack to p type single crystal silicon surface in the time of 78 DEG C, prepares leg-of-mutton light trapping structure matte, then, by after 11% hydrochloric acid and the mixing of 9% hydrofluoric acid, matte being cleaned, removes surface impurity.
In temperature is the diffusion furnace of 800 DEG C, adopt POCl3Carry out phosphorus diffusion, the diffusingsurface sheet resistance that makes P type crystalline silicon is 40ohm/sq, and described diffusingsurface and cutting face are positioned at the same side
Spraying width with shower nozzle at fluting position is 10 μ m masks, again in the equipment of one side etching, after the nitric acid of 8.5% hydrofluoric acid and 36% is mixed, the back side of etching silicon wafer and side at normal temperatures, then after the nitric acid of 8% hydrofluoric acid and 36 being mixed, in the time that temperature is 4 DEG C, the cutting face of silicon chip is corroded, making without the sheet resistance of mask regions is 80ohm/sq, obtains N layer, then remove mask and surperficial phosphorosilicate glass, finally dry again
Front plates the silicon nitride film that thickness is 80nm, and the back side plates aluminium oxide and the silicon nitride composite membrane that thickness is 80nm.
Adopt laser means to open film to the back side, remove composite film, the figure of opening film is that width is the line of 50um, and opening film rate is 60%, after opening film and completing to its cleaning oven dry.
The method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 30um, height is that the 18A of the Du Pont slurry of 55um forms the negative pole of battery, then in temperature is the sintering furnace of 500 DEG C, carries out common burning.
Embodiment 3
Selecting resistivity is the P type silicon chip of 1.8 cm, and the pulse energy of laser is at 0.4uJ, and frequency, under the condition of 3500KHz, adopts ns laser instrument to slot according to negative electrode figure in substrate one side, and groove width is 35um, is 60um deeply, and distance between centers of tracks is 1.2mm.
Sodium hydroxide solution with 0.58% carries out chemical attack to p type single crystal silicon surface in the time of 79 DEG C, prepares leg-of-mutton light trapping structure matte, then, by after 11.5% hydrochloric acid and the mixing of 8.5% hydrofluoric acid, matte being cleaned, removes surface impurity.
Injecting phosphorus source at cutting face, is that 15keV, Implantation amount are 105cm at ion beam energy-2After, then anneal in temperature is the annealing furnace of 900 DEG C, the P type crystalline silicon sheet resistance after annealing is 40ohm/sq, described diffusingsurface and cutting face are positioned at the same side.
Spraying width with shower nozzle at fluting position is 30 μ m masks, again in the equipment of one side etching, after the nitric acid of 9% hydrofluoric acid and 35% ~ 40% is mixed, the back side of etching silicon wafer and side at normal temperatures, then after the nitric acid of 7% ~ 12% hydrofluoric acid and 38% being mixed, in the time that temperature is 9 DEG C, the cutting face of silicon chip is corroded, making without the sheet resistance of mask regions is 120ohm/sq, obtains N layer, then remove mask and surperficial phosphorosilicate glass, finally dry again
Front plates the silicon nitride film that thickness is 95nm, and the back side plates silica and the silicon nitride composite membrane that thickness is 80nm.
Print overleaf Merck BES slurry and remove the method for the composite film in this region and open film, the figure of opening film is that aperture is the circle of 100um, and opening film rate is 70%, after completing to its cleaning oven dry.
The method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 35um, height is the negative pole that the nickel dam of 61um forms battery, in being the sintering furnace of 700 DEG C, temperature carries out common burning, after sintering, pasting one deck width again in negative terminal surface with conducting resinl is 35um, the copper strips that thickness is 25um.
Embodiment 4
Selecting resistivity is the P type silicon chip of 10 cm, and the pulse energy of laser is at 0.8uJ, and frequency, under the condition of 5000KHz, adopts ns laser instrument to slot according to negative electrode figure in substrate one side, and groove width is 50um, is 100um deeply, and distance between centers of tracks is 1.5mm.
Sodium hydroxide solution with 2% carries out chemical attack to p type single crystal silicon surface in the time of 80 DEG C, prepares leg-of-mutton light trapping structure matte, then, by after 12% hydrochloric acid and the mixing of 10% hydrofluoric acid, matte being cleaned, removes surface impurity.
In temperature is the diffusion furnace of 900 DEG C, adopt POCl3Carry out phosphorus diffusion, the diffusingsurface sheet resistance that makes P type crystalline silicon is 60ohm/sq, and described diffusingsurface and cutting face are positioned at the same side
Spraying width with shower nozzle at fluting position is 70 μ m masks, again in the equipment of one side etching, after the nitric acid of 10% hydrofluoric acid and 40% is mixed, the back side of etching silicon wafer and side at normal temperatures, then after the nitric acid of 12% hydrofluoric acid and 40% being mixed, in the time that temperature is 10 DEG C, the cutting face of silicon chip is corroded, making without the sheet resistance of mask regions is 150ohm/sq, obtains N layer, then remove mask and surperficial phosphorosilicate glass, finally dry again.
Front plates the silicon nitride film that thickness is 100nm, and the back side plates silica/alumina and the silicon nitride composite membrane that thickness is 100nm.
Print overleaf Merck BES slurry and remove the method for the composite film in this region and open film, the figure of opening film is that width is the line of 200um, and opening film rate is 80%, after completing to its cleaning oven dry.
The method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 50um, height is the negative pole that the nickel dam of 100um forms battery, in being the sintering furnace of 800 DEG C, temperature carries out common burning, after sintering, cell piece is plated one deck and is risen the copper layer of electric action on nickel dam by the mode of electroplating, the thickness of copper layer is 30um, and width is 50um.
Above-described embodiment is only explanation technical conceive of the present invention and feature, its objective is to allow to be familiar with these those skilled in the art and can to understand content of the present invention enforcement according to this, can not limit the scope of the invention with this. All equivalents that Spirit Essence is made according to the present invention or modification, within all should being encompassed in protection scope of the present invention.

Claims (6)

1. a preparation method for efficient P type crystalline silicon grooving and grid burying battery, is characterized in that: its technological process comprises: the monocrystalline silicon lbg-making herbs into wool of P type silicon substrate also diffuses to form the formation of PN junction-selective emitter and goes back of the body knot and phosphorosilicate glass-double-sided coating-back side regional area to open membrane-electrode and make its cleaning-front;
Concrete steps comprise:
(a): the one-side gaining of P type silicon substrate monocrystalline silicon laser
Selecting resistivity is the P type silicon chip of 0.3 cm ~ 10 cm, and the pulse energy of laser is at 0.05uJ ~ 0.8uJ, and frequency is under the condition of 50KHz ~ 5000KHz, adopt ns laser instrument at substrate one side fluting, groove width is 5um ~ 50um, is 5um ~ 100um deeply, and distance between centers of tracks is 0.5mm ~ 1.5mm;
(b): making herbs into wool to its cleaning
The sodium hydroxide solution that is 0.5% ~ 2% by concentration carries out chemical attack to p type single crystal silicon surface in the time of 75 DEG C ~ 80 DEG C, prepare leg-of-mutton light trapping structure matte, then the hydrochloric acid that is 10% ~ 12% by concentration and concentration are after 8% ~ 10% hydrofluoric acid mixes, matte to be cleaned, and remove surface impurity;
(c): front diffuses to form PN junction
In temperature is the diffusion furnace of 600-900 DEG C, adopt POCl3Carry out phosphorus diffusion, the diffusingsurface sheet resistance that makes P type crystalline silicon is 20-90ohm/sq; Or first injecting phosphorus source at cutting face, is that 15keV, Implantation amount are 105cm at ion beam energy-2After, then anneal in temperature is the annealing furnace of 800-1000 DEG C, the P type crystalline silicon sheet resistance after annealing is 20-90ohm/sq;
(d): selective emitter forms and go back of the body knot and phosphorosilicate glass
Spraying width with shower nozzle at fluting position is 5 μ m ~ 70 μ m masks, again in the equipment of one side etching, the hydrofluoric acid that is 8% ~ 10% by concentration and concentration are after 35% ~ 40% nitric acid mixes, the back side of etching silicon wafer and side at normal temperatures, then the hydrofluoric acid that is 7% ~ 12% by concentration and concentration are that 35% ~ 40% nitric acid mixed solution corrodes the cutting face of silicon chip in the time that temperature is 2 DEG C ~ 10 DEG C, making without the sheet resistance of mask regions is 70 ~ 150ohm/sq, then remove mask and surperficial phosphorosilicate glass, finally dry again;
(e) double-sided coating
Front plates the silicon nitride film that thickness is 50nm ~ 100nm, and the back side plates the composite membrane that thickness is 50nm ~ 100nm;
(f) back side regional area is opened film
Adopt laser means to open film to the back side, remove composite film, the figure of opening film is that aperture is the circle of 50um ~ 400um, or the width line that is 20 ~ 200um, and opening film rate is 50% ~ 90%, after opening film and completing to its cleaning oven dry; Or print overleaf Merck BES slurry and remove the method for the composite film in this region and open film, the figure of opening film is that aperture is the circle of 50um ~ 400um, or the width line that is 20 ~ 200um, opening film rate is 50% ~ 90%, after completing to its cleaning oven dry;
(g) electrode fabrication
The method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 5um ~ 60um, height is the negative pole that the 17F of the Du Pont slurry of 5um ~ 100um or the 18A of Du Pont slurry form battery, then in temperature is the sintering furnace of 400 DEG C ~ 800 DEG C, carries out common burning; Or the method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 5um ~ 60um, height is the negative pole that the nickel dam of 1um ~ 100um forms battery, in temperature is the sintering furnace of 400 DEG C ~ 800 DEG C, carry out common burning, after sintering, paste with conducting resinl the copper strips that one deck width is 5um ~ 200um in negative terminal surface again; Or the method that adopts serigraphy forms the positive pole of battery at the back up silver aluminium paste of battery, adopting the method for inkjet printing wide at fluting place, the front of battery spray printing is 5um ~ 60um, height is the negative pole that the nickel dam of 1um ~ 100um forms battery, in being the sintering furnace of 400 DEG C ~ 800 DEG C, temperature carries out common burning, after sintering, cell piece is plated one deck and is risen the copper layer of electric action on nickel dam by the mode of electroplating, or play the copper layer of electric action by method spray printing one deck on nickel dam of inkjet printing, the thickness of copper layer is 5um ~ 30um, and width is 5um ~ 90um.
2. the preparation method of a kind of efficient P type crystalline silicon grooving and grid burying battery according to claim 1, is characterized in that: the diffusingsurface described in step c and cutting face are positioned at the same side.
3. the preparation method of a kind of efficient P type crystalline silicon grooving and grid burying battery according to claim 1, is characterized in that: the width of the mask described in steps d is more than or equal to the width of PN junction one side groove.
4. the preparation method of a kind of efficient P type crystalline silicon grooving and grid burying battery according to claim 1, it is characterized in that: the composite membrane described in step e and step f is silica and silicon nitride composite membrane, aluminium oxide and silicon nitride composite membrane, any one in silica, aluminium oxide and silicon nitride composite membrane.
5. the preparation method of a kind of efficient P type crystalline silicon grooving and grid burying battery according to claim 4, is characterized in that: described silica and silicon nitride composite membrane are on the basis of silicon oxide film, grow one deck silicon nitride film formation silica and silicon nitride composite membrane; Aluminium oxide and silicon nitride composite membrane are on the basis of pellumina, grow one deck silicon nitride film formation aluminium oxide and silicon nitride composite membrane; Aluminium oxide, silica and silicon nitride composite membrane are one deck silicon oxide film of growing on the basis of pellumina, and then one deck silicon nitride film of growing on the basis of silicon oxide film forms aluminium oxide, silica and silicon nitride composite membrane.
6. the preparation method of a kind of efficient P type crystalline silicon grooving and grid burying battery according to claim 1, is characterized in that: in step g, the width of the pattern of inkjet printing is consistent with cutting width, and the height of the pattern of inkjet printing is more than or equal to the degree of depth of cutting.
CN201410219780.9A 2014-05-22 2014-05-22 A kind of preparation method of efficient P type crystalline silicon grooving and grid burying battery Expired - Fee Related CN103985789B (en)

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CN102361040A (en) * 2011-11-08 2012-02-22 天威新能源控股有限公司 Solar cell and preparation method thereof
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