CN103972200B - Lead frame structure - Google Patents

Abstract

A lead frame structure comprises a plastic package layer, an insulation layer and pin structures, wherein the plastic package layer is provided with a plurality of supporting areas; the supporting areas are internally provided with a plurality of first openings penetrating through the plastic package layer; the plastic package layer is provided with a first surface and a second surface opposite to the first surface; the insulation layer is located on the first surface of the plastic package layer; the insulation layer is internally provided with second openings exposing the first openings; the second openings are greater than the first openings in size; the second openings further expose part of the surface, around the first openings in the supporting areas, of the plastic package layer; the pin structures are located in the first openings and the second openings; the insulation layer exposes the first surfaces of the pin structures; the plastic package layer exposes the second surfaces of the pin structures. The shape and the electric connection performance of the lead frame are improved.

Description

Lead frame structure

Technical field

The present invention relates to technical field of manufacturing semiconductors, more particularly, to a kind of lead frame structure.

Background technology

Towards miniaturization, portable, the ultrathin with electronic product such as mobile phone, notebook computer etc., multimedization and The inexpensive direction meeting public demand is developed, the packing forms of high density, high-performance, high reliability and low cost and its assembling Technology has obtained quick development.Compared with the packing forms such as expensive BGA (Ball Grid Array), in recent years soon The novel encapsulated technology of speed development, such as four flat non-pins (QFN, Quad Flat No-leadPackage) encapsulation, due to it There is good hot property and electrical property, size be little, low cost and high production rate etc. are numerous, caused microelectronics envelope One new revolution of dress technical field.

Fig. 1 is a kind of cross-sectional view of encapsulating structure embodiment, and described encapsulating structure includes：Lead frame, institute State lead frame and include first surface 101 and the second surface 102 relative with first surface 101, described lead frame has Some load bearing units 103 and being located between load bearing unit 103 for fixing the middle muscle 104 of load bearing unit 103, each carrying Unit 103 has some discrete pins 105, has opening (not shown) between adjacent leads 105；Some semiconductor chips 107, described semiconductor chip 107 surface has some pads 108, and described pad 108 has metal coupling 109；Described half Conductor chip 107 upside-down mounting is on the first surface 101 of lead frame and corresponding with load bearing unit 103, described semiconductor chip Metal coupling 109 on 107 is welded together with the pin 105 of load bearing unit 103, forms some encapsulation units, described encapsulation Unit includes a load bearing unit and semiconductor chip；The plastic packaging layer 110 of opening between the full adjacent leads 105 of filling, described moulds Sealing also fills up space between semiconductor chip 107 and first surface 101, and is covered in described nead frame 100 and partly leads Body chip 107 surface, described plastic packaging layer 110 exposes pin 105 second surface 102.The follow-up corresponding position along described middle muscle 104 Put the described plastic packaging layer 110 of cutting and nead frame 100, so that some encapsulation units is separated.

However, in described encapsulating structure, the process costs of the described lead frame of formation are higher, technology difficulty is larger, and And the pattern of described lead frame is bad, is unfavorable for the electric connection of semiconductor chip.

Content of the invention

The problem that the present invention solves is to provide a kind of lead frame structure, and described lead frame appearance structure is improved, is electrically connected Connect performance improvement.

For solving the above problems, the present invention provides a kind of lead frame structure, including：

Plastic packaging layer, described plastic packaging layer has some supporting regions, has and some run through described plastic packaging layer in described supporting region First opening, described plastic packaging layer has first surface and the second surface relative with first surface；

Positioned at the insulating barrier of the first surface of described plastic packaging layer, have in described insulating barrier and expose the second of the first opening Opening, the size of described second opening is more than the size of the first opening, and described second opening also exposes in supporting region First parameatal part plastic packaging layer surface；

Pin configuration in described first opening and the second opening, described insulating layer exposing goes out the first of pin configuration Surface, described plastic packaging layer exposes the second surface of pin configuration.

Optionally, described plastic packaging layer also includes the cutting area between supporting region.

Optionally, described insulating barrier includes：Positioned at the first insulating sublayer layer of plastic packaging layer surface and positioned at the first insulating sublayer Second insulating sublayer layer of layer surface, has the second opening in described first insulating sublayer layer, have in described second insulating sublayer layer with 3rd opening of the second opening insertion, described 3rd opening is located in the correspondence position of plastic packaging layer supporting region；Described pin configuration In described first opening, the second opening and the 3rd opening.

Optionally, the material of described first insulating sublayer layer is solder resist material, and the material of described second insulating sublayer layer is welding resistance Material.

Optionally, the material of described first insulating sublayer layer is photic solder resist material.

Optionally, the material of described plastic packaging layer is resin；The material of described insulating barrier is solder resist material；Described conductive material Alloy for tin or tin.

Optionally, described resin includes epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles tree Fat, polybutylene terephthalate, Merlon, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, poly- ammonia Ester, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.

Optionally, described solder resist material includes green oil, polybenzoxazoles or polyimides.

Optionally, described supporting region is arranged in arrays.

Compared with prior art, technical scheme has advantages below：

In the lead frame structure of the present invention, described plastic packaging layer has supporting region, and described supporting region is used in subsequent technique Middle flip chip structure.Wherein, in the supporting region of described plastic packaging layer, there is the first opening.Have first in described plastic packaging layer surface Insulating sublayer layer, has the second opening in described first insulating sublayer layer, described second opening is located in supporting region.Due to described first Pin layer is located in the first opening and the second opening, and the first opening and the second opening are located in supporting region so that the first pin Layer has part plastic packaging layer and the first insulating sublayer layer is isolated between carrying area edge, is being subsequently formed thus ensure that In the independent structure for encapsulation, the sidewall surfaces of described first pin layer still have part plastic packaging layer and the first insulating sublayer Layer protection, and described first pin layer only exposes first surface and second surface is used for electrically connecting, it can be avoided that described pin Structure is polluted by external environment condition, and the electrical property of described pin configuration is more stable.

Further, described insulating barrier includes：Positioned at the first insulating sublayer layer of plastic packaging layer surface and positioned at the first insulating sublayer Second insulating sublayer layer of layer surface, has the second opening in described first insulating sublayer layer, have in described second insulating sublayer layer with 3rd opening of the second opening insertion, described pin configuration is located in the first opening, the second opening and the 3rd opening.Described 3rd Part pin configuration in opening is used for carrying out layout so that insulating layer exposing goes out to the part pin configuration in the second opening again The position of pin configuration first surface be suitable to be connected with the connection end of the chip structure of follow-up upside-down mounting.

Brief description

Fig. 1 is a kind of cross-sectional view of encapsulating structure embodiment；

Fig. 2 to Fig. 5 is the cross-sectional view of the forming process of the lead frame structure of the embodiment of the present invention；

Fig. 6 to Fig. 7 is the cross-sectional view of the forming process of another kind of lead frame structure of the embodiment of the present invention；

Fig. 8 to Figure 12 is a kind of cross-sectional view of method for packing of the embodiment of the present invention；

Figure 13 is the cross-sectional view of another kind of method for packing of the embodiment of the present invention.

Specific embodiment

As stated in the Background Art, in described encapsulating structure, the process costs of the described lead frame of formation are higher, technique is difficult Degree is larger, and the pattern of described lead frame is bad, is unfavorable for the electric connection of semiconductor chip.

Find through research, because lead frame as shown in Figure 1 passes through to perform etching it to the metal substrate being provided After formed, therefore the usage amount for metal material larger so that lead frame process costs improve.It is additionally, since to metal The difficulty that substrate performs etching is larger, hence in so that the technology difficulty of lead frame improves.Additionally, by etching Metal Substrate plate shape The lead frame pattern becoming is bad, and the electric connection stability of semiconductor chip is had adverse effect.

Specifically, in one embodiment, the formation process of described lead frame includes：Metal substrate, described metal are provided Substrate has first surface and the second surface relative with first surface；Described metal substrate is performed etching, formation runs through The opening of described metal substrate.During in order to avoid subsequently filling plastic packaging material in described opening, plastic packaging material can be let out from described opening Dew, after etching metal substrate and forming opening, adheres to adhesive film in the second surface of described metal substrate, in described opening After interior filling plastic packaging material, remove described adhesive film.However, described adhesive film can damage the pin surface being formed by metal substrate Pattern, leads to the electrical connection stability of pin to be deteriorated.

In order to avoid using described adhesive film, in another embodiment, the formation process of described lead frame includes：There is provided Metal substrate, described metal substrate has first surface and the second surface relative with first surface；To described metal substrate First surface perform etching, form the first opening in described metal substrate, the non-through described Metal Substrate of described first opening Plate；Full plastic packaging layer is filled in described first opening；The second surface of described metal substrate is performed etching, in described Metal Substrate Form the second opening, described second opening and the first opening insertion in plate, and described second opening exposes in the first opening Plastic packaging layer.

Due to described first opening and all non-through described metal substrate of the second opening, and when forming the second opening, It is filled with plastic packaging layer, when therefore subsequently filling capsulation material in described second opening, capsulation material will not be from first opening First opening is revealed, thus avoid adhering to adhesive film in metallic substrate surfaces.However, due to described plastic packaging layer material and metal The expansion coefficient difference of baseplate material is larger, and the etching technics etching the second opening is carried out in high temperature environments, is therefore carving During losing the second opening, easily expand different from shrinkage stress between described plastic packaging layer and metal substrate, and cause institute The lead frame warped being formed.Therefore, the lead frame pattern being formed is bad, leads to follow-up and semiconductor chip electrical connection Unstable properties.

In order to solve the above problems, the present invention proposes a kind of lead frame structure.Wherein, have in the supporting region of plastic packaging layer First opening, described plastic packaging layer surface has the first insulating sublayer layer, has the second opening in described first insulating sublayer layer, and described Two openings are located in supporting region.Because described first pin layer is located in the first opening and the second opening, and the first opening and the Two openings are located in supporting region so that the first pin layer has part plastic packaging layer and the first insulating sublayer layer between carrying area edge Isolated, it can be avoided that described pin configuration is polluted by external environment condition, the electrical property of described pin configuration is more stable.

Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 2 to Fig. 5 is the cross-sectional view of the forming process of the lead frame structure of the embodiment of the present invention.

Refer to Fig. 2, the plastic packaging layer 200 of the mould with cavity, the appearance structure of described cavity and required formation is provided Appearance structure identical；To the cavity injection capsulation material in mould, until described cavity is filled full, form plastic packaging layer 200.

In the present embodiment, described plastic packaging layer 200 passes through the injection capsulation material into the mould have cavity and is formed.Another In embodiment, described plastic packaging layer 200 passes through the plastic sealed board etching being provided is formed.

There is in described mould cavity, described cavity defines the structure of plastic packaging layer 200 and the pattern of required formation, passes through Inject capsulation material and solidify in described cavity, described plastic packaging layer 200 can be formed, after forming plastic packaging layer 200, remove Described mould can carry out follow-up technique.The material of described mould be exotic material, and will not in high temperature environments with mould There is chemical reaction in the material of sealing 200.

In the present embodiment, described mould includes having reeded first Die and mould plate 400 and the second Die and mould plate, works as institute When stating the first Die and mould plate 400 and having reeded one side and be mutually closed with the second Die and mould plate, the table of described groove and the second Die and mould plate Face can constitute the cavity in described mould.

The technique forming plastic packaging layer 200 in described mould includes：The injection fluid into the groove of the first Die and mould plate 400 Capsulation material, until the full described groove of capsulation material filling, the surface of described capsulation material is higher than or is flush to described first mould The surface of tool plate 400；After injection capsulation material, make the second Die and mould plate have reeded one side with the first Die and mould plate 400 and close Close, so that the surface of groove and the second Die and mould plate constitutes cavity；After the second Die and mould plate and the first Die and mould plate 400 close, make Capsulation material solidification in cavity, forms plastic packaging layer 200.Subsequently through described first Die and mould plate 400 of separation and the second Die and mould plate, Described plastic packaging layer 200 can be taken out.Form the process is simple of described plastic packaging layer 200, and described first Die and mould plate 400 and Two molds plate can reuse.

Wherein, in described first Die and mould plate 400, described groove defines the structure of plastic packaging layer 200, and adjacent grooves it Between the figure i.e. required plastic packaging layer 200 being formed of the first Die and mould plate 400 in the first opening figure, and described first opening Inside it is subsequently used for forming the outer pin of pin configuration, therefore, between described groove, the graphic definition of the first Die and mould plate 400 is required The outer pin of the pin configuration being formed.

Secondly, the surface of described second Die and mould plate is flat, and after the second Die and mould plate and the first Die and mould plate 400 are closed, institute The surface stating the second Die and mould plate can have reeded surface with the first Die and mould plate 400 and contacts, so that the depth of described groove The thickness of i.e. the formed plastic packaging layer 200 of degree, and it is formed at the plastic packaging layer 200 described in the first opening insertion in plastic packaging layer 200, make Described first opening can be used in forming the outer pin of pin configuration.

In another embodiment, described mould is the container with cavity, and described cavity passes through through hole and ft connection, By injecting the capsulation material of fluid into described through hole, the full capsulation material of filling in described cavity can be made；In described cavity After filling is full, described capsulation material is solidified, form plastic packaging layer in described cavity.Subsequently through the described mould of destruction Described plastic packaging layer can be taken out.

The material of described plastic packaging layer 200 is resin, and described resin is epoxy resin, polyimide resin, benzocyclobutene Resin or polybenzoxazoles resin；Described resin can also be polybutylene terephthalate, Merlon, poly terephthalic acid Glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethyl vinyl acetate Ethylene copolymer or polyvinyl alcohol.Described plastic packaging layer 200 can also be other suitable capsulation materials.

Refer to Fig. 3, after forming plastic packaging layer 200, remove described mould, described plastic packaging layer 200 has some carryings Area 201 and be located at cutting area 202 between supporting region 201, has in described supporting region 201 and some runs through described plastic packaging layer The first opening 203, described plastic packaging layer 200 has first surface 204 and the second surface relative with first surface 204 205.

In the present embodiment, described plastic packaging layer 200 is formed in the cavity of mould, therefore, capsulation material in cavity After solidifying to form plastic packaging layer 200, need to remove described mould.And, in the present embodiment, described mould is by being mutually closed One Die and mould plate 400 and the second Die and mould plate are formed, after described capsulation material solidifies, can make described first Die and mould plate 400 with Second Die and mould plate separates, to remove described mould.

Additionally, when described mould is overall structure, and when there is the container with the cavity of ft connection, by into cavity After injection capsulation material is to form plastic packaging layer 200, mould described in external damage, to remove described mould and to mould described in taking out Sealing 200, for example, break into pieces described mould.

In another embodiment, described plastic packaging layer 200 can also be formed by punching to plastic packaging version.Specifically, described mould The formation process of sealing 200 includes：Plastic sealed board is provided；Described plastic sealed board is carried out with drilling technology, formed plastic packaging layer 200 and Run through the first opening 203 of described plastic packaging layer 200.

For solid-state and surface is flat for described plastic sealed board, and material is resin, and described resin is epoxy resin, polyimides tree Fat, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, poly terephthalic acid second two Alcohol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethene-vinyl acetate Copolymer, polyvinyl alcohol or other suitable capsulation materials；

Described drilling technology is laser boring technique or water knife technique, and described laser boring technique or water knife technique being capable of essences Really navigate to the position needing to be formed the first opening 203 described plastic sealed board is punched, the first formed opening can be made 203 positions and dimensions are accurately easily-controllable；And, described drilling technology can be accurately positioned, thus without to needing to form first Plastic sealed board beyond opening 203 causes pyrolytic damage, can make that formed plastic packaging layer 200 is flat and pattern is good；Additionally, it is described Drilling technology need not be additionally formed mask layer or patterned photoresist layer, the technique of formation the first opening 203 can be made to simplify, Easily operated.

Described drilling technology can also include：Form mask layer in plastic packaging plate surface, described mask layer exposes and needs shape Become the plastic packaging plate surface of the first opening 203；With described mask layer as mask, etch described plastic sealed board to form described first opening 203, until plastic sealed board described in the insertion of described first opening 203.Described mask layer is patterned photoresist layer, described photoresist The formation process of layer includes：In plastic packaging plate surface spin coating photoresist film；Described photoresist film is exposed with development with graphical.

The plastic packaging layer 200 being formed has some supporting regions 201, and described supporting region 201 can be arranged in arrays, described The surface of supporting region 201 is subsequently used for flip chip structure；Cutting area 202 between adjacent supporting region 201 is as subsequently carrying out The region of cutting technique, so that some supporting regions 201 and upside-down mounting chip structure on supporting region 201 is separated from each other, with Form independent encapsulating structure.

First opening 203 of described insertion plastic packaging layer 200 is used for forming the outer pin of pin configuration, and therefore described first opens Mouthfuls 203 are formed in supporting region 201, to ensure that follow-up cutting technique will not damage the outer pin in described first opening 203. Being additionally, since the outer pin that described plastic packaging layer 200 second surface 205 exposes subsequently needs to be connected or shape with external circuit Become soldered ball, be short-circuited in order to avoid between adjacent outer pin, described first opening 203 is parallel to plastic packaging layer 200 surface direction Size less so that the distance between adjacent first opening 203 is larger, avoid subsequently adjacent outer pin that short circuit occurs with this.

Refer to Fig. 4, the first insulating sublayer layer 206 formed on the first surface 204 of described plastic packaging layer 200, described first There is in insulating sublayer layer 206 the second opening 207 exposing the first opening 203, the size of described second opening 207 is more than first The size of opening 203, the part that described second opening 207 also exposes around the first opening 203 in supporting region 201 is moulded Sealing 200 surface.

In the present embodiment, the i.e. required insulating barrier of described first insulating sublayer layer 206.In another embodiment, described first Insulating sublayer layer collectively forms the insulating barrier of required formation with being subsequently formed in the second insulating sublayer layer of the first insulating sublayer layer surface.

In the present embodiment, the material of described first insulating sublayer layer 206 is solder resist material, and described solder resist material includes green oil (green paint), polybenzoxazoles (PBO), polyimides (PI).Additionally, described first insulating sublayer layer 206 can also be using other exhausted Edge material.

In the present embodiment, the material of described first insulating sublayer layer 206 is photic solder resist material, described photic solder resist material Development can be exposed, and directly graphically form the second opening 207.The formation process of described first insulating sublayer layer 206 includes： First dielectric film is formed in the first surface 204 of plastic packaging layer 200 using spraying or spin coating proceeding；Described first dielectric film is carried out Exposure imaging, needs to be formed part first dielectric film of the second opening 207 to remove, expose part plastic packaging layer 200 surface and First opening 203, forms the first insulating sublayer layer 206.

Forming the first insulating sublayer layer 206 using photic solder resist material can make the formation process letter of the first insulating sublayer layer 206 Change, the mask layer for etching need not be additionally formed；Secondly, it is to avoid the first dielectric film is performed etching, thus to plastic packaging layer The damage on 200 surfaces is less；Again, directly the first dielectric film is exposed developing, the size of the second opening 207 being formed More accurately easily-controllable with structure.

In another embodiment, the formation process of described first insulating sublayer layer 206 includes：Using spraying, spin coating or deposition Technique forms the first dielectric film in the first surface 203 of plastic packaging layer 200；Form mask layer, institute in described first insulating film surface State mask layer and expose part first insulating film surface needing to be formed the second opening 207；With described mask layer as mask, etching Described first dielectric film, till exposing plastic packaging layer 200 surface and the first opening 203, forms the first insulating sublayer layer 206. The material of described first insulating sublayer layer 206 is different from the material of plastic packaging layer 200, makes described first dielectric film with respect to plastic packaging layer 200 have Etch selectivity.The technique etching described first dielectric film is anisotropic dry etch process, makes to be formed The side wall of the second opening 207 is vertical with respect to the first insulating sublayer layer 206 surface.

Described second opening 207 is used for being formed interior pin, and described interior pin is subsequently used for being connected with the chip of chip structure End electrical connection, therefore described second opening 207 is formed in the corresponding region of supporting region 201, it is to avoid follow-up cutting technique is to the Pin configuration in two openings 207 causes to damage.The size of described second opening 207 is more than the size of the first opening 203, therefore Described second opening 207 exposes part plastic packaging layer 200 surface around the first opening 203.In the present embodiment, described second opens The mouth 207 side walls near supporting region 201 edge are flushed with the side wall of the first opening 203, and the second opening 207 exposes close holding Carry part plastic packaging floor 200 surface at area 201 center, described second opening 207 is used for forming interior pin, therefore described interior pin to The center of supporting region 201 extends.

Described second opening 207 is used for forming the interior pin of pin configuration, and described interior pin is used for follow-up upside-down mounting in moulding Chip structure electrical connection on sealing 200 first surface 203.Described second opening 207 is parallel to the first insulating sublayer layer 206 surface The size in direction is more than the size of the first opening 203, and exposes part plastic packaging layer 200 surface around the first opening 203.By Larger in the interior pin area being formed in the second opening 207, therefore, subsequently make the chip connection end of chip structure with described The difficulty of described welding procedure when interior pin is welded, can be simplified, make chip connection end more steady with the electrical connection of interior pin Fixed.

Additionally, after follow-up formation pin configuration in the first opening 203 and the second opening 207, due to the second opening 207 More than the first opening 203 so that the interior pin size in the second opening 207 is more than the outer pin size in the first opening 203, institute State pin configuration to be difficult to come off in the first opening 203 and the second opening 207；And, the pin configuration being formed and plastic packaging layer 200 and first contacts area between insulating sublayer layer 206 are larger, same it can be avoided that the coming off of pin configuration.

In another embodiment, described first insulating sublayer layer is exhausted with the second son being subsequently formed in the first insulating sublayer layer surface Edge layer collectively forms insulating barrier, has the 3rd opening in described second insulating sublayer layer, and the part being formed in described 3rd opening is drawn Leg structure is used for the interior pin in the second opening being connected up again, to be more beneficial for flip-chip.

Refer to Fig. 5, fill in described first opening 203 (as shown in Figure 4) and the second opening 207 (as shown in Figure 4) Full conductive material, forms the first pin layer 208 in described first opening 203 and the second opening 204.

In the present embodiment, described first insulating sublayer layer 206 is formed insulating barrier, and described first pin layer 208 is The pin configuration being formed, described first insulating sublayer layer 206 exposes the first surface 209 of pin configuration, described plastic packaging layer 200 Expose the second surface 210 of pin configuration.The first surface 209 of described pin configuration is neat with the first insulating sublayer layer 206 surface Flat, the second surface 210 of described pin configuration is flushed with the second surface 205 of plastic packaging layer 200.

Due to being initially formed the first insulating sublayer layer 206 of plastic packaging layer 200 and plastic packaging layer 200 first surface 204, and institute State and there is in plastic packaging layer 200 first opening 203, in described first insulating sublayer layer 206, there is the second opening 207, by described Conductive material is filled to form the first sub- pin layer 208, using as pin configuration, energy in first opening 203 and the second opening 207 Enough avoid because of the thermal expansion coefficient difference between capsulation material or insulating materials and conductive material, and cause formed pin to tie The problems such as there is warped deformation in structure；And, in the first opening 203 and the second opening 207, the conductive material of filling is less, can Avoid the waste to conductive material, so that technique is simplified, cost reduces.

Wherein, for forming the outer pin of pin configuration in described first opening 203, described outer pin is used for making subsequently to fall The chip structure being loaded on pin configuration second surface 210 is electrically connected with external circuit；Draw for formation in described second opening 207 The interior pin of leg structure, described interior pin passes through welding with chip structure connection end and realizes electrically connecting.Therefore, described pin configuration First surface 209 be interior pin surface, the second surface 210 of described pin configuration is the surface of outer pin.Described pin First surface 209 area of structure is more than first surface 209, is conducive to making first surface 209 be connected with follow-up chip structure End is welded to each other；The area of the second surface 210 of described pin configuration is less, it can be avoided that occurring short between adjacent outer pin Road.And, it is formed at the outer pin size that interior pin size in the second opening 207 is more than in the first opening 203 so that first Pin layer 208 is difficult to come off in the first opening 203 and the second opening 207.

The formation process of described conductive material is silk-screen printing technique, and described conductive material is the alloy of tin or tin, described Tin alloy is tin silver, tin-lead, SAC, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, in the silver-colored antimony of tin One or more combinations.Additionally, described first pin layer 208 can also be using other conductive materials.

The alloy of described tin or tin has good ductility it is easy to be packed into the first opening 203 and the second opening 207 Interior, and can be good with the contact of plastic packaging layer 200 and the first insulating sublayer layer 206, formed the first pin layer 208 shape can be made Looks are good and interior solid is uniform.And, the alloy of described tin or tin has larger surface tension, in the first opening 203 He In second opening 207, the conductive material of filling is difficult to flow out at the first opening of plastic packaging layer second surface, it is to avoid conduction material The loss of material.

In one embodiment, when the conductive material surface filled is higher than the first insulating sublayer layer 206 surface or plastic packaging layer 200 second surface 205, can lead to the part higher than the first insulating sublayer layer 206 surface or plastic packaging layer 200 second surface 205 Electric material carries out flatening process, makes formed the first pin layer 208 surface and the first insulating sublayer layer 206 surface and plastic packaging layer 200 second surfaces 205 flush.

In the present embodiment, the plastic packaging layer being formed has supporting region and cutting area, and described supporting region is used in subsequent technique Middle flip chip structure, described cutting area is cut in subsequent technique to be removed, and wherein, has in the plastic packaging layer of described supporting region First opening.Form the first insulating sublayer layer with the second opening in described plastic packaging layer surface, and described second opening exposes First opening and the first parameatal part plastic packaging layer surface, by filling in described first opening and the second opening Conductive material is to form the first pin layer.Because the first pin layer passes through to fill conductive material in the first opening and the second opening Formed, thus decreasing the consumption of metal material, process costs can be reduced with this, and filling the technique letter of conductive material Single.And, by the first opening and the second opening filling conductive material formed the first pin layer, make described first opening and Second opening can define pattern and the structure of described first pin layer, thus ensure formed pin configuration appearance good, Electrical connection properties are stable.Further, since the size of described second opening is more than the size of the first opening, in described first opening and In second opening during filling metal material, metal material is difficult to overflow from the first opening of plastic packaging layer second surface and causes to damage Lose, and the first pin layer being formed is difficult to come off from the first opening and the second opening.

Accordingly, the present invention also provides the lead frame structure that a kind of employing said method is formed, please continue to refer to figure 5, including：

Plastic packaging layer 200, described plastic packaging layer 200 has some supporting regions 201 and is located at the cutting between supporting region 201 Area 202, has some the first opening (not shown) running through described plastic packaging layer 200, described plastic packaging layer in described supporting region 201 200 have first surface 204 and the second surface 205 relative with first surface 204；

Positioned at the insulating barrier of the first surface 204 of described plastic packaging layer 200, have in described insulating barrier and expose the first opening The second opening (not shown), the size of described second opening is more than the size of the first opening, and described second opening also exposes In supporting region 201 first parameatal part plastic packaging layer 200 surface；

Pin configuration in described first opening and the second opening, described insulating layer exposing goes out the first of pin configuration Surface 209, described plastic packaging layer exposes the second surface 210 of pin configuration.

Hereinafter said structure will be described in detail.

In the present embodiment, described insulating barrier is the first insulating sublayer layer 206, and described pin configuration is the first pin layer 208.Institute State the first surface 209 that the first insulating sublayer layer 206 exposes pin configuration, described plastic packaging layer 200 exposes the of pin configuration Two surfaces 210.The first surface 209 of described pin configuration is flushed with the first insulating sublayer layer 206 surface, and the of described pin configuration Two surfaces 210 are flushed with the second surface 205 of plastic packaging layer 200.

The material of described plastic packaging layer 200 is resin, and described resin is epoxy resin, polyimide resin, benzocyclobutene Resin or polybenzoxazoles resin；Described resin can also be polybutylene terephthalate, Merlon, poly terephthalic acid Glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethyl vinyl acetate Ethylene copolymer or polyvinyl alcohol.Described plastic packaging layer 200 can also be other suitable capsulation materials.

The plastic packaging layer 200 being formed has some supporting regions 201, and described supporting region 201 can be arranged in arrays, described The surface of supporting region 201 is subsequently used for flip chip structure；Cutting area 202 between adjacent supporting region 201 is as subsequently carrying out The region of cutting technique, so that some supporting regions 201 and upside-down mounting chip structure on supporting region 201 is separated from each other, with Form independent encapsulating structure.

There is in described first opening the outer pin of pin configuration, described first opening is located in supporting region 201；Described There is in two openings the outer pin of pin configuration, described second opening is located in supporting region 201.Described plastic packaging layer 200 second table The outer pin that face 205 exposes subsequently is needed to be connected with external circuit or forms soldered ball；Described interior pin is subsequently used for and core The chip connection end electrical connection of chip architecture.In the present embodiment, described second opening is near the side wall and first at supporting region 201 edge The side wall of opening flushes, and the second opening exposes part plastic packaging layer 200 surface near supporting region 201 center, positioned at second Interior pin in opening extends to the center of supporting region 201.

The material of described first insulating sublayer layer 206 is solder resist material, and described solder resist material includes green oil (green paint), polyphenyl simultaneously Oxazole (PBO), polyimides (PI)；Additionally, described solder resist material can also be other insulating materials.In the present embodiment, institute The material stating the first insulating sublayer layer 206 is photic solder resist material

The material of described pin configuration is the alloy of tin or tin, described tin alloy is tin silver, tin-lead, SAC, tin silver-colored zinc, One of tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, tin silver antimony or multiple combination.Additionally, described pin knot Structure can also be using other conductive materials.

In the present embodiment, described plastic packaging layer has supporting region and cutting area, and described supporting region is used for falling in subsequent technique Cored chip architecture, described cutting area is cut in subsequent technique to be removed.Wherein, have first in the supporting region of described plastic packaging layer Opening.In described plastic packaging layer surface, there is the first insulating sublayer layer, there is in described first insulating sublayer layer the second opening, described second Opening is located in supporting region.Because described first pin layer is located in the first opening and the second opening, and the first opening and second Opening be located in supporting region so that there is between the first pin layer and cutting area part plastic packaging layer and the first insulating sublayer layer carry out every From, thus ensure that after the described cutting area of follow-up cutting, in the independent structure for encapsulation being formed, described first The sidewall surfaces of pin layer still have part plastic packaging layer and the protection of the first insulating sublayer layer, and described first pin layer only exposes First surface and second surface are used for electrically connecting, it can be avoided that described pin configuration is polluted by external environment condition, described pin The electrical property of structure is more stable.

Embodiments of the invention additionally provide the forming method of another kind of lead frame structure, on the basis of Fig. 5, please continue Continuous reference Fig. 6 and Fig. 7.

Refer to Fig. 6, after forming the first pin layer 208, form the second insulating sublayer on the first insulating sublayer layer 206 surface Layer 211, has the 3rd opening 212 with the second opening 207 (as shown in Figure 4) insertion in described second insulating sublayer layer 211, described 3rd opening 212 is located in the correspondence position of plastic packaging layer 200 supporting region 201.

In the present embodiment, described second insulating sublayer layer 211 and the first insulating sublayer layer 206 constitute the required insulation being formed Layer.

In the present embodiment, the material of described second insulating sublayer layer 211 is solder resist material, and described solder resist material includes green oil (green paint), polybenzoxazoles (PBO), polyimides (PI).Additionally, described second insulating sublayer layer 211 can also be using other exhausted Edge material.The material of described second insulating sublayer layer 211 is identical or different with the material of the first insulating sublayer layer 206.

In the present embodiment, the material of described second insulating sublayer layer 211 is photic solder resist material, described photic solder resist material Development can be exposed, and directly graphically form the 3rd opening 212.The formation process of described second insulating sublayer layer 211 includes： Second dielectric film is formed in the first insulating sublayer layer 206 and the first pin layer 208 surface using spraying or spin coating proceeding；To described Two dielectric films are exposed developing, and need to be formed part second dielectric film of the 3rd opening 212 to remove, expose part first Insulating sublayer layer 206 and the first pin layer 208 surface, form the second insulating sublayer layer 211.

Forming the second insulating sublayer layer 211 using photic solder resist material can make the formation process letter of the second insulating sublayer layer 211 Change, the mask layer for etching need not be additionally formed；Secondly, it is to avoid the second dielectric film is performed etching, thus drawing to first The damage on pin layer 208 and the first insulating sublayer layer 206 surface is less；Again, directly the second dielectric film is exposed developing, institute's shape The size of the 3rd opening 212 becoming and structure are more accurately easily-controllable.

In another embodiment, the formation process of described second insulating sublayer layer 211 includes：Using spraying, spin coating or deposition Technique forms the second dielectric film in the first insulating sublayer layer 206 and the first pin layer 208 surface；In described second insulating film surface shape Become mask layer, described mask layer exposes part second insulating film surface needing to be formed the 3rd opening 212；With described mask layer For mask, etch described second dielectric film, till exposing the first insulating sublayer layer 206 and the first pin layer 208 surface, shape Become the second insulating sublayer layer 211.The material of described second insulating sublayer layer 211 is different from the material of the first insulating sublayer layer 206, makes described Second dielectric film has Etch selectivity with respect to the first insulating sublayer layer 206.Etch described second dielectric film technique be each to The dry etch process of the opposite sex, makes the side wall of the 3rd formed opening 212 vertical with respect to the second insulating sublayer layer 211 surface.

Described 3rd opening 212 is used for being formed at the first opening 203 (as shown in Figure 4) and the second opening 207 (as Fig. 4 Shown) in the first pin layer 208 connected up again, make to be subsequently formed the position of the second pin layer in the 3rd opening 212 It is adapted with the chip connection end of the chip structure of follow-up upside-down mounting, to meet the package requirements of small-size chips physical dimension.

Described 3rd opening 212 is formed in the corresponding region of supporting region 201, it is to avoid follow-up cutting technique is to being formed at the Second pin layer in three openings 212 causes to damage.In the present embodiment, described 3rd opening 212 exposes in supporting region Part the first pin layer 208 of the heart and part the first insulating sublayer layer 206 surface near supporting region 201 center, are subsequently formed Second pin layer in the 3rd opening 212 can extend the phase so that in same supporting region 201 to the center of supporting region 201 Distance between second pin layer is reduced, even if the chip structure size of follow-up upside-down mounting is less, the distance between chip connection end Less, the position of described second pin layer still can be corresponding with chip connection end, thus meeting the envelope of small-size chips structure Dress demand.

Refer to Fig. 7, fill full conductive material in described 3rd opening 212 (as shown in Figure 6), form second pin layer 213, described second pin layer 213 and the first pin layer 208 constitute pin configuration.

Described second pin layer 213 is flushed with the second insulating sublayer layer 211 surface.Described second pin layer 213 surface is follow-up Realize the electrical interconnection and chip structure connection end between by welding.Because described 3rd opening 212 exposes near supporting region Part the first pin layer 208 at center and part the first insulating sublayer layer 206 surface near supporting region 201 center, are formed Second pin layer 213 extend to the center of supporting region 201, and be formed at the relative second pin layer in same supporting region 201 Between 213, distance is less, disclosure satisfy that the package requirements of small-size chips structure.

The formation process of described conductive material is silk-screen printing technique, and described conductive material is the alloy of tin or tin, described Tin alloy is tin silver, tin-lead, SAC, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, in the silver-colored antimony of tin One or more combinations.Additionally, described second pin layer 213 can also be using other conductive materials.

The alloy of described tin or tin has good ductility it is easy to be packed in the 3rd opening 212, and can be with second The contact of insulating sublayer layer 211 is good, and second pin layer 213 pattern being formed is good, interior solid is uniform.

In one embodiment, when the conductive material surface filled is higher than the second insulating sublayer layer 211 surface, to higher than the The partially electronically conductive material on two insulating sublayer layer 211 surface carries out flatening process, makes formed second pin layer 213 surface and the Two insulating sublayer layer 211 surface flushes.

In the present embodiment, form the second insulating sublayer layer, described second son in the first insulating sublayer layer and the first pin layer surface There is in insulating barrier the 3rd opening exposing part the first insulating sublayer layer and the first pin layer, described 3rd opening is used for being formed Second pin layer, described second pin layer and the first pin layer constitute pin configuration.Described second pin layer is used for drawing to first Pin layer is connected up the chip knot so that the position of second pin layer surface that exposes of the second insulating sublayer layer and follow-up upside-down mounting again The chip connection end of structure is corresponding, to meet undersized chip structure package requirements.

Accordingly, the present invention also provides the lead frame structure that a kind of employing said method is formed, please continue to refer to figure 7, including：

Plastic packaging layer 200, described plastic packaging layer 200 has some supporting regions 201 and is located at the cutting between supporting region 201 Area 202, has some the first opening (not shown) running through described plastic packaging layer 200, described plastic packaging layer in described supporting region 201 200 have first surface 204 and the second surface 205 relative with first surface 204；

In the first insulating sublayer layer 206 of the first surface 204 of described plastic packaging layer 200, described first insulating sublayer layer 206 There is the second opening (not shown) exposing the first opening, the size of described second opening is more than the size of the first opening, institute State the second opening and also expose the first parameatal part plastic packaging layer 200 surface in supporting region 201；

The first pin layer 208 in described first opening and the second opening；

Have in the second insulating sublayer layer 211 on the first insulating sublayer layer 206 surface, described second insulating sublayer layer 211 with 3rd opening (not shown) of the second opening insertion, described 3rd opening is located at the correspondence position of plastic packaging layer 200 supporting region 201 Interior；

Second pin layer 213 in described 3rd opening, described second pin layer 213 and the first pin layer 208 structure Become pin configuration.

Hereinafter said structure will be described in detail.

Described second insulating sublayer layer 211 and the first insulating sublayer layer 206 constitute the required insulating barrier being formed.Described second son is absolutely The material of edge layer 211 is solder resist material, and described solder resist material includes green oil (green paint), polybenzoxazoles (PBO), polyimides (PI).Additionally, described second insulating sublayer layer 211 can also be using other insulating materials.The material of described second insulating sublayer layer 211 Identical or different with the material of the first insulating sublayer layer 206.In the present embodiment, the material of described second insulating sublayer layer 211 is light Cause solder resist material, described photic solder resist material can be exposed development.

Described 3rd opening 212 is located in the corresponding region of supporting region 201, it is to avoid follow-up cutting technique is to second pin layer 213 cause to damage.In the present embodiment, described 3rd opening 212 exposes part the first pin layer near supporting region 201 center 208 and part the first insulating sublayer layer 206 surface near supporting region 201 center, second in the 3rd opening 212 draw Pin layer extends to the center of supporting region 201 so that distance reduces between relative second pin layer in same supporting region 201, energy Enough meet the package requirements of small-size chips structure.

The formation process of described conductive material is silk-screen printing technique, and described conductive material is the alloy of tin or tin, described Tin alloy is tin silver, tin-lead, SAC, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, in the silver-colored antimony of tin One or more combinations.Additionally, described second pin layer 213 can also be using other conductive materials.

In the present embodiment, described second pin layer and the first pin layer constitute pin configuration, and described second pin layer is used for First pin layer is connected up again so that the position of second pin layer surface that exposes of the second insulating sublayer layer and follow-up upside-down mounting Chip structure chip connection end corresponding, meet undersized chip structure package requirements.

Accordingly, the embodiment of the present invention also provides a kind of method for packing, on the basis of Fig. 5, please continue to refer to Fig. 8 to figure 11, including：

Lead frame structure as shown in Figure 5 is provided.

The forming process of described lead frame structure, as described in the embodiment of Fig. 2 to Fig. 5, will not be described here.

Refer to Fig. 8, chip structure 300 is provided, described chip structure 300 surface has some chip connection ends 301.

Described chip structure 300 is formed through cutting by wafer, have in described chip structure 300 by semiconductor devices and The integrated circuit that electric interconnection structure is constituted.Described chip connection end 301 is used for and external electrical connections.

In the present embodiment, described chip connection end 301 includes：Some weld pads 310 positioned at chip structure surface；Positioned at institute State the conductive projection 311 on weld pad 310 surface；Soldered ball 312 positioned at described conductive projection 311 surface.Wherein, described weld pad 310 Electrically connect with the integrated circuit within chip structure so that described weld pad 310 can be used as integrated circuit and external electrical connections Port.

In the present embodiment, described chip structure 300 surface has separation layer (sign), and described separation layer has and exposes The opening on weld pad 310 surface, described conductive projection 311 is formed in the surface that weld pad 310 exposes and described separation layer and opens The sidewall surfaces of mouth, and the surface of described conductive projection 311 is higher than described insulation surface.

The material of described separation layer is insulating materials, and described separation layer is used for protecting chip structure table in subsequent technique Face；Described conductive projection 311 is cylinder, and the material of described conductive projection 311 is aluminium, nickel, tungsten, platinum, copper, titanium, chromium, tantalum, tin, tin Alloy, golden or silver-colored；The material of described soldered ball 312 is tin or tin alloy, and described tin alloy is tin silver, tin-lead, SAC, Xi Yin Zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, tin silver one of antimony or multiple.

In other embodiments, described weld pad 310 surface can also only have conductive projection or soldered ball, and described chip connects End is made up of weld pad 310 and conductive projection or has weld pad 310 and soldered ball to constitute.

In another embodiment, before weld pad 310 surface forms conductive projection 311 or soldered ball 312, in described weld pad The sidewall surfaces of 310 surfaces exposing and described separation layer inner opening form convex lower conductiving layer, described conductive projection 311 Or soldered ball 312 is formed at described convex lower conductiving layer surface.Described convex lower conductiving layer is used for strengthening conductive projection 311 or soldered ball 312 Bond strength and weld pad 310 between.

Refer to Fig. 9, by the upside-down mounting of described chip structure 300 on the insulating barrier on plastic packaging layer 200 supporting region 201 surface, make Described chip connection end 300 is electrically connected with the pin configuration first surface 209 in lead frame structure.

Described chip structure 300 is corresponded with supporting region 201 so that each chip structure 300 upside-down mounting is held in one Carry in area 201, because described chip structure 300, the first pin layer 208 are respectively positioned in supporting region 201, subsequently carrying out cutting work After skill, the side wall of described chip structure 300 or the first pin layer 208 will not be exposed so that chip structure 300 and first draws Pin layer 208 is protected.

In the present embodiment, described insulating barrier is the first insulating sublayer layer 206, and described pin configuration is the first pin layer 208, institute The first surface 209 stating pin configuration is the first pin layer 208 surface that described first insulating sublayer layer 206 exposes.

In the present embodiment, make the method that described chip connection end 300 is electrically connected with the pin configuration in lead frame structure For：After described soldered ball 212 is contacted with the surface of the first pin layer 208, by reflux technique, make described conductive projection 211 Weld together with the first pin layer 208 via soldered ball 212.

Refer to Figure 10, form the envelope bed of material in surface of insulating layer, chip structure 300 surface, pin configuration first surface 209 400, the described envelope bed of material 400 wraps up described chip structure 300 and fills the space between full insulating barrier and chip structure 300.

The described envelope bed of material 400 is used for electrically insulating, to realize the encapsulation to chip structure 300.In the present embodiment, described envelope material The full space between first insulating sublayer layer 206 and chip structure 300 of layer 400 filling, surrounds described chip connection end 300, and It is covered in the first insulating sublayer layer 206 surface.

The material of the described envelope bed of material 400 is resin, and described resin can be epoxy resin, polyimide resin, benzo ring Butene resins or polybenzoxazoles resin；Described resin can also be polybutylene terephthalate, Merlon, gather to benzene two Formic acid glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethene- Acetate ethylene copolymer or polyvinyl alcohol；The described envelope bed of material 400 can also be using other suitable capsulation materials.

The formation process of the described envelope bed of material 400 be Shooting Technique (injection molding) or turn mould technique (transfer molding).The described envelope bed of material 400 can also be formed using other suitable techniques.

Refer to Figure 11, along described plastic packaging layer 200 cutting area 202 (as shown in Figure 10) to the described envelope bed of material 400, insulation Layer and plastic packaging layer 200 are cut, and form encapsulating structure, and the pin configuration sidewall surfaces in described encapsulating structure have insulating barrier Cover with plastic packaging layer 200.

Because described first pin layer 208 and chip structure 300 are formed in the corresponding region of supporting region 201, Jing Guosuo State after cutting area 202 cut, described first pin layer 208 still has the first son near the sidewall surfaces of cutting area 202 Insulating barrier 206 and plastic packaging layer 200 cover, and described first pin layer 208 only exposes first surface 209 and second surface 210.

The encapsulating structure being formed can by the second surface 210 of the first pin layer 208 and external electrical connections, for example with PCB connects, or electrically connects with other encapsulating structures or chip structure.

In another embodiment, refer to Figure 12, after forming the envelope bed of material 400, before carrying out cutting technique, described The second surface 210 of pin configuration forms soldered ball 214；After forming described soldered ball 214, carry out cutting technique, and form envelope Assembling structure.The material of described soldered ball 214 is tin or tin alloy.

In the present embodiment, by described chip structure upside-down mounting on the insulating barrier on plastic packaging layer supporting region surface, make described chip Connection end is electrically connected with the pin configuration first surface in lead frame structure, after forming the envelope bed of material, along described plastic packaging layer Cutting area the described envelope bed of material, insulating barrier and plastic packaging layer are cut, to form encapsulating structure.Due to described first opening and Second opening is formed in the corresponding region of plastic packaging layer supporting region, that is, the pin configuration being formed is formed at plastic packaging layer supporting region In corresponding region, and described chip structure upside-down mounting, on the insulating barrier on plastic packaging layer supporting region surface, therefore, is carrying out cutting it Afterwards, described pin configuration sidewall surfaces still have insulating barrier and plastic packaging layer and cover so that in the encapsulating structure that formed, pin is tied Structure in addition to exposing the first surface being electrically connected and second surface, other surfaces of pin configuration all by plastic packaging layer and Insulating barrier covering protection.Surface therefore, it is possible to reduce pin configuration is subject to outside contamination infringement it is ensured that the electricity of pin configuration Stable performance.

Accordingly, the embodiment of the present invention also provides a kind of encapsulating structure, please continue to refer to Figure 11, including：

Lead frame structure as shown in Figure 5；

Chip structure 300, described chip structure 300 surface has some chip connection ends 301；

The upside-down mounting of described chip structure 300, on the insulating barrier on plastic packaging layer 200 supporting region 201 surface, makes described chip connect End 301 is electrically connected with the pin configuration first surface 209 in lead frame structure；

Positioned at surface of insulating layer, chip structure 300 surface, pin configuration first surface 209 the envelope bed of material 400, described envelope The bed of material 400 wraps up described chip structure 300 and fills the space between full insulating barrier and chip structure 300；

Described pin configuration sidewall surfaces have insulating barrier and plastic packaging layer 200 covers.

Hereinafter said structure will be described in detail.

In described chip structure 300, there is the integrated circuit being made up of semiconductor devices and electric interconnection structure.Described chip Connection end 301 is used for electrically connecting with pin configuration.

In the present embodiment, described chip connection end 301 includes：Some weld pads 310 positioned at chip structure surface；Positioned at institute State the conductive projection 311 on weld pad 310 surface；Soldered ball 312 positioned at described conductive projection 311 surface.Wherein, described weld pad 310 Electrically connect with the integrated circuit within chip structure so that described weld pad 310 can be used as integrated circuit and external electrical connections Port.

In the present embodiment, described chip structure 300 surface has separation layer (sign), and described separation layer has and exposes The opening on weld pad 310 surface, surface and described separation layer inner opening that described conductive projection 311 exposes positioned at weld pad 310 Sidewall surfaces, and the surface of described conductive projection 311 be higher than described insulation surface.

The material of described separation layer is insulating materials；Described conductive projection 311 is cylinder, the material of described conductive projection 311 Expect for aluminium, nickel, tungsten, platinum, copper, titanium, chromium, tantalum, tin, tin alloy, golden or silver-colored；The material of described soldered ball 312 is tin or tin alloy, institute State tin alloy be tin silver, tin-lead, SAC, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, in the silver-colored antimony of tin One or more.

In other embodiments, described weld pad 310 surface can also only have conductive projection or soldered ball, and described chip connects End is made up of weld pad 310 and conductive projection or has weld pad 310 and soldered ball to constitute.

In another embodiment, between described weld pad 310 and conductive projection 311 or soldered ball 312, also there is convex lower conduction Layer, described conductive projection 311 or soldered ball 312 are located at described convex lower conductiving layer surface.Described convex lower conductiving layer is used for strengthening conduction Bond strength between projection 311 or soldered ball 312 and weld pad 310.

Described chip structure 300 and supporting region 201 are corresponded, i.e. each chip structure 300 upside-down mounting carries in one In area 201.

In the present embodiment, described insulating barrier is the first insulating sublayer layer 206, and described pin configuration is the first pin layer 208, institute The first surface 209 stating pin configuration is the first pin layer 208 surface that described first insulating sublayer layer 206 exposes.

The material of the described envelope bed of material 400 is resin, and described resin can be epoxy resin, polyimide resin, benzo ring Butene resins or polybenzoxazoles resin；Described resin can also be polybutylene terephthalate, Merlon, gather to benzene two Formic acid glycol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethene- Acetate ethylene copolymer or polyvinyl alcohol；The described envelope bed of material 400 can also be using other suitable capsulation materials.

In the present embodiment, described first pin layer and chip structure are respectively positioned in the corresponding region of plastic packaging layer supporting region, because This, described first pin layer sidewall surfaces have insulating barrier and plastic packaging layer and cover, described first pin layer except expose for Electrical connection first surface and second surface outside, other surfaces are all protected, can reduce the first pin layer by outer The pollution infringement on boundary is it is ensured that the electric performance stablity of the first pin layer.

Additionally, the embodiment of the present invention also provides another kind of method for packing.

Refer to Figure 13, including：

Lead frame structure as shown in Figure 7 is provided；

There is provided chip structure 300, described chip structure 300 surface has some chip connection ends 301；

By the upside-down mounting of described chip structure 300 on the corresponding second insulating sublayer layer 211 of plastic packaging layer 200 supporting region 201, make institute State chip connection end 301 to electrically connect with second pin layer 213 surface in lead frame structure；

Form the envelope bed of material 400 in the second insulating sublayer layer 211 surface, chip structure 300 surface, pin configuration first surface, The described envelope bed of material 400 wraps up described chip structure 300 and fills the space between full insulating barrier and chip structure 300；

Along described plastic packaging layer 200 cutting area 202 to the described envelope bed of material 400, the second insulating sublayer layer 211, the first insulating sublayer Layer 206 and plastic packaging layer 200 are cut, and form encapsulating structure, and the pin configuration sidewall surfaces in described encapsulating structure have the One insulating sublayer layer 206, the second insulating sublayer layer 211 and plastic packaging layer 200 cover.

Hereinafter above-mentioned method for packing is illustrated.

Described second insulating sublayer layer 211 and the first insulating sublayer layer 206 constitute the required insulating barrier being formed, described second pin Layer 213 and the first pin layer 208 constitute pin configuration, and described 3rd opening is located in the corresponding region of supporting region 201, then formed It is located in the corresponding region of supporting region 201 in the second pin layer 213 in the 3rd opening.

Described chip structure 300, the technique of flip chip structure 300, the envelope bed of material 400 and its formation process such as Fig. 8 are to figure Will not be described here described in 11 embodiment.

In another embodiment, after forming the envelope bed of material 400, before carrying out cutting technique, in described pin configuration Second surface forms soldered ball；After forming described soldered ball, carry out cutting technique, and form encapsulating structure.

Accordingly, the embodiment of the present invention also provides another kind of encapsulating structure, please continue to refer to Figure 13, including：

Lead frame structure as shown in Figure 7；

Chip structure 300, described chip structure 300 surface has some chip connection ends 301；

The upside-down mounting of described chip structure 300, on the corresponding second insulating sublayer layer 211 of plastic packaging layer 200 supporting region 201, makes described Chip connection end 301 is electrically connected with the pin configuration first surface in lead frame structure；

Positioned at the second insulating sublayer layer 211 surface, chip structure 300 surface, pin configuration first surface the envelope bed of material 400, The described envelope bed of material 400 wraps up described chip structure 300 and fills full sky between second insulating sublayer layer 211 and chip structure 300 Between；

Described pin configuration sidewall surfaces have the first insulating sublayer layer 206, the second insulating sublayer layer 211 and plastic packaging layer 200 and cover Lid.

In the present embodiment, described second pin layer is used for the first pin layer being connected up again, due to described second pin Layer to supporting region center extend so that in same supporting region with respect to second pin layer between distance reduce, even if described Chip structure size is less, and the distance between adjacent chips connection end is less, and described second pin layer still disclosure satisfy that described The package requirements of small-size chips structure.

Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from this In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope limiting is defined.

Claims (8)

1. a kind of lead frame structure is it is characterised in that include：

Plastic packaging layer, described plastic packaging layer has some supporting regions, has and some run through the first of described plastic packaging layer in described supporting region Opening, described plastic packaging layer has first surface and the second surface relative with first surface；

Positioned at the insulating barrier of the first surface of described plastic packaging layer, described insulating barrier includes：Exhausted positioned at the first son of plastic packaging layer surface Edge layer and the second insulating sublayer layer being located at the first insulating sublayer layer surface, have in described first insulating sublayer layer and expose first Second opening of opening, the size of described second opening is more than the size of the first opening, and described second opening also exposes and is located at In supporting region first parameatal part plastic packaging layer surface, has and the second opening insertion in described second insulating sublayer layer 3rd opening, described 3rd opening is located in the correspondence position of plastic packaging layer supporting region；

Pin configuration in described first opening, the second opening and the 3rd opening, described insulating layer exposing goes out pin configuration First surface, described plastic packaging layer exposes the second surface of pin configuration.

2. lead frame structure as claimed in claim 1 is it is characterised in that described plastic packaging layer is also included between supporting region Cutting area.

3. lead frame structure as claimed in claim 1 is it is characterised in that the material of described first insulating sublayer layer is welding resistance material Material, the material of described second insulating sublayer layer is solder resist material.

4. lead frame structure as claimed in claim 3 is it is characterised in that the material of described first insulating sublayer layer is photic resistance Wlding material.

5. lead frame structure as claimed in claim 1 is it is characterised in that the material of described plastic packaging layer is resin；Described exhausted The material of edge layer is solder resist material；Described pin configuration is the alloy of tin or tin.

6. lead frame structure as claimed in claim 5 is it is characterised in that described resin includes epoxy resin, polyimides Resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, poly terephthalic acid second Diol ester, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethyl vinyl acetate second Alkene copolymer or polyvinyl alcohol.

7. the lead frame structure as described in claim 3 or 5 is it is characterised in that described solder resist material includes green oil, polyphenyl simultaneously Oxazole or polyimides.

8. lead frame structure as claimed in claim 1 is it is characterised in that described supporting region is arranged in arrays.