CN103972200A

CN103972200A - Lead frame structure

Info

Publication number: CN103972200A
Application number: CN201410220369.3A
Authority: CN
Inventors: 石磊; 陶玉娟
Original assignee: Nantong Fujitsu Microelectronics Co Ltd
Current assignee: Nantong Fujitsu Microelectronics Co Ltd
Priority date: 2014-05-22
Filing date: 2014-05-22
Publication date: 2014-08-06
Anticipated expiration: 2034-05-22
Also published as: CN103972200B

Abstract

A lead frame structure comprises a plastic package layer, an insulation layer and pin structures, wherein the plastic package layer is provided with a plurality of supporting areas; the supporting areas are internally provided with a plurality of first openings penetrating through the plastic package layer; the plastic package layer is provided with a first surface and a second surface opposite to the first surface; the insulation layer is located on the first surface of the plastic package layer; the insulation layer is internally provided with second openings exposing the first openings; the second openings are greater than the first openings in size; the second openings further expose part of the surface, around the first openings in the supporting areas, of the plastic package layer; the pin structures are located in the first openings and the second openings; the insulation layer exposes the first surfaces of the pin structures; the plastic package layer exposes the second surfaces of the pin structures. The shape and the electric connection performance of the lead frame are improved.

Description

Lead frame structure

Technical field

The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of lead frame structure.

Background technology

Along with electronic product is if mobile phone, notebook computer etc. are towards miniaturization, portable, ultrathin, multimedization and the low-cost future development that meets public demand, high density, high-performance, high reliability and cheaply packing forms and packaging technology thereof have obtained development fast.Compare with packing forms such as expensive BGA (BallGrid Array), fast-developing novel encapsulated technology in recent years, as four flat non-pin (QFN, Quad Flat No-leadPackage) encapsulation, because it has advantages of good hot property and electrical property, size is little, cost is low and high production rate etc. is numerous, caused a new revolution in microelectronic packaging technology field.

Fig. 1 is the cross-sectional view of a kind of encapsulating structure embodiment, described encapsulating structure comprises: lead frame, described lead frame comprises first surface 101 and the second surface 102 relative with first surface 101, described lead frame there are some load bearing units 103 and between load bearing unit 103 for the fixing muscle 104 of load bearing unit 103, each load bearing unit 103 has some discrete pins 105, has opening (not shown) between adjacent leads 105; Some semiconductor chips 107, described semiconductor chip 107 surfaces have some pads 108, on described pad 108, have metal coupling 109; Described semiconductor chip 107 upside-down mountings are on the first surface 101 of lead frame and corresponding with load bearing unit 103, metal coupling 109 on described semiconductor chip 107 welds together with the pin 105 of load bearing unit 103, form some encapsulation units, described encapsulation unit comprises a load bearing unit and semiconductor chip; Fill the plastic packaging layer 110 of opening between full adjacent leads 105, described plastic packaging layer is also filled in space between semiconductor chip 107 and first surface 101, and being covered in described nead frame 100 and semiconductor chip 107 surfaces, described plastic packaging layer 110 exposes pin 105 second surfaces 102.The follow-up correspondence position along described middle muscle 104 cuts described plastic packaging layer 110 and nead frame 100, makes some encapsulation units separated.

Yet in described encapsulating structure, the process costs that forms described lead frame is higher, technology difficulty is larger, and the pattern of described lead frame is bad, is unfavorable for the electric connection of semiconductor chip.

Summary of the invention

The problem that the present invention solves is to provide a kind of lead frame structure, and described lead frame appearance structure is improved, electrical connection properties improves.

For addressing the above problem, the invention provides a kind of lead frame structure, comprising:

Plastic packaging layer, described plastic packaging layer has some supporting regions, has some the first openings that run through described plastic packaging layer in described supporting region, and described plastic packaging layer has first surface and the second surface relative with first surface;

Be positioned at the insulating barrier of the first surface of described plastic packaging layer, in described insulating barrier, there is the second opening that exposes the first opening, the size of described the second opening is greater than the size of the first opening, and described the second opening also exposes the first parameatal part plastic packaging layer surface that is positioned at supporting region;

The pin configuration that is positioned at described the first opening and the second opening, described insulating layer exposing goes out the first surface of pin configuration, and described plastic packaging layer exposes the second surface of pin configuration.

Optionally, described plastic packaging layer also comprises the cutting area between supporting region.

Optionally, described insulating barrier comprises: the second insulating sublayer layer that is positioned at the first insulating sublayer layer on plastic packaging layer surface and is positioned at the first insulating sublayer layer surface, in described the first insulating sublayer layer, there is the second opening, in described the second insulating sublayer layer, have the 3rd opening connecting with the second opening, described the 3rd opening is positioned at the correspondence position of plastic packaging layer supporting region; Described pin configuration is positioned at described the first opening, the second opening and the 3rd opening.

Optionally, the material of described the first insulating sublayer layer is solder resist material, and the material of described the second insulating sublayer layer is solder resist material.

Optionally, the material of described the first insulating sublayer layer is photic solder resist material.

Optionally, the material of described plastic packaging layer is resin; The material of described insulating barrier is solder resist material; Described electric conducting material is the alloy of tin or tin.

Optionally, described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.

Optionally, described solder resist material comprises green oil, polybenzoxazoles or polyimides.

Optionally, described supporting region is matrix and arranges.

Compared with prior art, technical scheme of the present invention has the following advantages:

In lead frame structure of the present invention, described plastic packaging layer has supporting region, and described supporting region is used at subsequent technique flip chip structure.Wherein, in the supporting region of described plastic packaging layer, there is the first opening.On described plastic packaging layer surface, have the first insulating sublayer layer, in described the first insulating sublayer layer, have the second opening, described the second opening is positioned at supporting region.Because described the first pin layer is positioned at the first opening and the second opening, and the first opening and the second opening are positioned at supporting region, make the first pin layer to thering is part plastic packaging layer between supporting region edge and the first insulating sublayer layer is isolated, thereby guaranteed the independently structure for encapsulating in follow-up formation, the sidewall surfaces of described the first pin layer still has part plastic packaging layer and the protection of the first insulating sublayer layer, and described the first pin layer only exposes first surface and second surface for being electrically connected to, can avoid described pin configuration to be subject to the pollution of external environment condition, the electrical property of described pin configuration is more stable.

Further, described insulating barrier comprises: the second insulating sublayer layer that is positioned at the first insulating sublayer layer on plastic packaging layer surface and is positioned at the first insulating sublayer layer surface, in described the first insulating sublayer layer, there is the second opening, in described the second insulating sublayer layer, have the 3rd opening connecting with the second opening, described pin configuration is positioned at the first opening, the second opening and the 3rd opening.Part pin configuration in described the 3rd opening is for carrying out layout again to the part pin configuration in the second opening, makes the position of the pin configuration first surface that insulating layer exposing goes out be suitable for being connected with the link of the chip structure of follow-up upside-down mounting.

Accompanying drawing explanation

Fig. 1 is the cross-sectional view of a kind of encapsulating structure embodiment;

Fig. 2 to Fig. 5 is the cross-sectional view of forming process of the lead frame structure of the embodiment of the present invention;

Fig. 6 to Fig. 7 is the cross-sectional view of forming process of the another kind of lead frame structure of the embodiment of the present invention;

Fig. 8 to Figure 12 is the cross-sectional view of a kind of method for packing of the embodiment of the present invention;

Figure 13 is the cross-sectional view of the another kind of method for packing of the embodiment of the present invention.

Embodiment

As stated in the Background Art, in described encapsulating structure, the process costs that forms described lead frame is higher, technology difficulty is larger, and the pattern of described lead frame is bad, is unfavorable for the electric connection of semiconductor chip.

Through research, find, because lead frame is as shown in Figure 1 undertaken forming after etching by the metal substrate to provided, therefore larger for the use amount of metal material, lead frame process costs is improved.And the difficulty of etching is larger due to metal substrate is carried out, therefore make the technology difficulty of lead frame improve.In addition, the lead frame pattern forming by etching metal substrate is bad, and the electric connection stability of semiconductor chip is had to adverse effect.

Concrete, in one embodiment, the formation technique of described lead frame comprises: metal substrate is provided, and described metal substrate has first surface and the second surface relative with first surface; Described metal substrate is carried out to etching, form the opening that runs through described metal substrate.For fear of follow-up while filling plastic packaging material in described opening, plastic packaging material can be revealed from described opening, at etching metal substrate and after forming opening, at the second surface adhesive gel rete of described metal substrate, fill plastic packaging material in described opening after, remove described adhesive film.Yet described adhesive film can damage the pin surface topography being formed by metal substrate, cause the electrical connection stability variation of pin.

For fear of using described adhesive film, in another embodiment, the formation technique of described lead frame comprises: metal substrate is provided, and described metal substrate has first surface and the second surface relative with first surface; The first surface of described metal substrate is carried out to etching, in described metal substrate, form the first opening, the non-through described metal substrate of described the first opening; In described the first opening, fill full plastic packaging layer; The second surface of described metal substrate is carried out to etching, form the second opening in described metal substrate, described the second opening and the first opening connect, and described the second opening exposes the plastic packaging layer in the first opening.

Due to the equal non-through described metal substrate of described the first opening and the second opening, and when forming the second opening, in the first opening, be filled with plastic packaging layer, therefore follow-up while filling capsulation material in described the second opening, capsulation material can not revealed from the first opening, thereby has avoided at metallic substrate surfaces adhesive gel rete.Yet, because the expansion coefficient difference of described plastic packaging layer material and metal substrate material is larger, and the etching technics of etching the second opening carries out under hot environment, therefore in the process of etching the second opening, the difference of easy Swelling and contraction stress between described plastic packaging layer and metal substrate, and cause formed lead frame warped.Therefore, formed lead frame pattern is bad, causes follow-up unstable with electrical connection properties semiconductor chip.

In order to address the above problem, the present invention proposes a kind of lead frame structure.Wherein, have the first opening in the supporting region of plastic packaging layer, described plastic packaging layer surface has the first insulating sublayer layer, in described the first insulating sublayer layer, has the second opening, and described the second opening is positioned at supporting region.Because described the first pin layer is positioned at the first opening and the second opening, and the first opening and the second opening are positioned at supporting region, make the first pin layer to thering is part plastic packaging layer between supporting region edge and the first insulating sublayer layer is isolated, can avoid described pin configuration to be subject to the pollution of external environment condition, the electrical property of described pin configuration is more stable.

For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.

Fig. 2 to Fig. 5 is the cross-sectional view of forming process of the lead frame structure of the embodiment of the present invention.

Please refer to Fig. 2, the mould with cavity is provided, the appearance structure of described cavity is identical with the appearance structure of the plastic packaging layer 200 of required formation; Cavity in mould injects capsulation material, until described cavity is filled completely, forms plastic packaging layer 200.

In the present embodiment, described plastic packaging layer 200 is by injecting capsulation material in the mould of cavity and form to having.In another embodiment, described plastic packaging layer 200 forms by the plastic sealed board etching to provided.

In described mould, there is cavity, described cavity has defined structure and the pattern of the plastic packaging layer 200 of required formation, by injecting capsulation material and solidify in described cavity, can form described plastic packaging layer 200, after forming plastic packaging layer 200, remove described mould and can carry out follow-up technique.The material of described mould is exotic material, and can be under hot environment and the material generation chemical reaction of plastic packaging layer 200.

In the present embodiment, described mould comprises reeded the first Die and mould plate 400 of tool and the second Die and mould plate, when the reeded one side of described the first Die and mould plate 400 tool and the mutual closure of the second Die and mould plate, the surface of described groove and the second Die and mould plate can form the cavity in described mould.

The technique that forms plastic packaging layer 200 in described mould comprises: to the capsulation material that injects fluid in the groove of the first Die and mould plate 400, until capsulation material is filled full described groove, the surface of described capsulation material higher than or flush in the surface of described the first Die and mould plate 400; After injecting capsulation material, make the second Die and mould plate and the reeded one side of the first Die and mould plate 400 tool closed, thereby make the surface of groove and the second Die and mould plate form cavity; After the second Die and mould plate and the first Die and mould plate 400 closures, the capsulation material in cavity is solidified, form plastic packaging layer 200.Follow-up by separated described the first Die and mould plate 400 and the second Die and mould plate, described plastic packaging layer 200 can be taken out.The technique that forms described plastic packaging layer 200 is simple, and described the first Die and mould plate 400 and the second Die and mould plate can reuse.

Wherein, in described the first Die and mould plate 400, described groove has defined the structure of plastic packaging layer 200, and the figure of the first Die and mould plate 400 between adjacent notches is the figure of the first opening in the plastic packaging layer 200 of required formation, and the follow-up outer pin that is used to form pin configuration in described the first opening, therefore, between described groove the graphical definition of the first Die and mould plate 400 the outer pin of pin configuration of required formation.

Secondly, having an even surface of described the second Die and mould plate, and by after the second Die and mould plate and the first Die and mould plate 400 closures, the surface of described the second Die and mould plate can contact with the first Die and mould plate 400 reeded surfaces of tool, thereby the degree of depth that makes described groove is the thickness of formed plastic packaging layer 200, and the first opening being formed in plastic packaging layer 200 connects described plastic packaging layer 200, make described the first opening can be used in the outer pin that forms pin configuration.

In another embodiment, described mould is the container with cavity, and described cavity is communicated with outside by through hole, by inject the capsulation material of fluid in described through hole, can make to fill and expire capsulation material in described cavity; After described cavity is filled completely, described capsulation material is cured, in described cavity, form plastic packaging layer.Follow-uply by destroying described mould, described plastic packaging layer can be taken out.

The material of described plastic packaging layer 200 is resin, and described resin is epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described resin can be also polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.Described plastic packaging layer 200 can also be other suitable capsulation materials.

Please refer to Fig. 3, after forming plastic packaging layer 200, remove described mould, described plastic packaging layer 200 has some supporting regions 201 and the cutting area between supporting region 201 202, in described supporting region 201, have some the first openings 203 that run through described plastic packaging layer, described plastic packaging layer 200 has first surface 204 and the second surface 205 relative with first surface 204.

In the present embodiment, described plastic packaging layer 200 forms in the cavity of mould, therefore, after the capsulation material in cavity solidify to form plastic packaging layer 200, need to remove described mould.And in the present embodiment, described mould is formed by the first Die and mould plate 400 and second Die and mould plate of mutual closure, after described capsulation material solidifies, can make described the first Die and mould plate 400 separated with the second Die and mould plate, to remove described mould.

In addition, when described mould is overall structure, and while thering is the container of the cavity being communicated with outside, by injecting capsulation material with after forming plastic packaging layer 200 in cavity, by mould described in external damage, to remove described mould and to take out described plastic packaging layer 200, for example, described mould is broken into pieces.

In another embodiment, described plastic packaging layer 200 can also be by plastic packaging version, punching forms.Concrete, the formation technique of described plastic packaging layer 200 comprises: plastic sealed board is provided; Described plastic sealed board is carried out to drilling technology, the first opening 203 that forms plastic packaging layer 200 and run through described plastic packaging layer 200.

Described plastic sealed board is solid-state and has an even surface, material is resin, and described resin is epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol or other suitable capsulation materials;

Described drilling technology is laser drilling technique or water cutter technique, described laser drilling technique or water cutter technique can accurately navigate to the position that need to form the first opening 203 described plastic sealed board is punched, and can make position and the accurately easily control of size of formed the first opening 203; And described drilling technology can accurately be located, therefore can not cause pyrolytic damage to the plastic sealed board that need to form beyond the first opening 203, can make that formed plastic packaging layer 200 is smooth and pattern is good; In addition, described drilling technology, without extra mask layer or the patterned photoresist layer of forming, can make to form work simplification, the easy operating of the first opening 203.

Described drilling technology can also comprise: on plastic sealed board surface, form mask layer, described mask layer exposes the plastic sealed board surface that need to form the first opening 203; Take described mask layer as mask, and plastic sealed board is to form described the first opening 203, until described the first opening 203 connects described plastic sealed board described in etching.Described mask layer is patterned photoresist layer, and the formation technique of described photoresist layer comprises: at plastic sealed board surface spin coating photoresist film; Described photoresist film is carried out to exposure imaging with graphically.

Formed plastic packaging layer 200 has some supporting regions 201, and described supporting region 201 can be matrix and arrange, and the surface of described supporting region 201 is follow-up for flip chip structure; Cutting area 202 between adjacent supporting region 201 is as follow-up region of carrying out cutting technique, thereby some supporting regions 201 and the chip structure of upside-down mounting on supporting region 201 are separated from each other, to form independently encapsulating structure.

The first opening 203 of described perforation plastic packaging layer 200 is used to form the outer pin of pin configuration, and therefore described the first opening 203 is formed in supporting region 201, to guarantee that follow-up cutting technique can not damage the outer pin in described the first opening 203.And, the outer pin that exposes due to described plastic packaging layer 200 second surface 205 is follow-up need to be connected with external circuit or form soldered ball, between adjacent outer pin, be short-circuited, the size that described the first opening 203 is parallel to plastic packaging layer 200 surface direction is less, make the distance between adjacent the first opening 203 larger, with this, avoid follow-up adjacent outer pin generation short circuit.

Please refer to Fig. 4, on the first surface 204 of described plastic packaging layer 200, form the first insulating sublayer layer 206, in described the first insulating sublayer layer 206, there is the second opening 207 that exposes the first opening 203, the size of described the second opening 207 is greater than the size of the first opening 203, and described the second opening 207 also exposes the first opening 203 part plastic packaging layer 200 surface around that are positioned at supporting region 201.

In the present embodiment, described the first insulating sublayer layer 206 is required insulating barrier.In another embodiment, described the first insulating sublayer layer and the follow-up common insulating barrier that forms required formation of the second insulating sublayer layer that is formed at the first insulating sublayer layer surface.

In the present embodiment, the material of described the first insulating sublayer layer 206 is solder resist material, and described solder resist material comprises green oil (green paint), polybenzoxazoles (PBO), polyimides (PI).In addition, described the first insulating sublayer layer 206 can also adopt other insulating material.

In the present embodiment, the material of described the first insulating sublayer layer 206 is photic solder resist material, and described photic solder resist material can be exposed development, and directly graphically forms the second opening 207.The formation technique of described the first insulating sublayer layer 206 comprises: adopt spraying or spin coating proceeding to form the first dielectric film at the first surface 204 of plastic packaging layer 200; Described the first dielectric film is carried out to exposure imaging, to remove part first dielectric film that need to form the second opening 207, expose part plastic packaging layer 200 surface and the first opening 203, form the first insulating sublayer layer 206.

Adopt photic solder resist material to form the formation work simplification that the first insulating sublayer layer 206 can make the first insulating sublayer layer 206, without the mask layer that is additionally formed for etching; Secondly, avoided the first dielectric film to carry out etching, thus less to the damage on plastic packaging layer 200 surface; Again, directly the first dielectric film is carried out to exposure imaging, the more accurate easily control of the size of formed the second opening 207 and structure.

In another embodiment, the formation technique of described the first insulating sublayer layer 206 comprises: adopt spraying, spin coating or depositing operation to form the first dielectric film at the first surface 203 of plastic packaging layer 200; On described the first dielectric film surface, form mask layer, described mask layer exposes the part first dielectric film surface that need to form the second opening 207; Take described mask layer as mask, and the first dielectric film described in etching, until expose plastic packaging layer 200 surface and the first opening 203, formation the first insulating sublayer layer 206.The material of described the first insulating sublayer layer 206 is different from the material of plastic packaging layer 200, makes described the first dielectric film have Etch selectivity with respect to plastic packaging layer 200.Described in etching, the technique of the first dielectric film is anisotropic dry etch process, makes the sidewall of formed the second opening 207 vertical with respect to the first insulating sublayer layer 206 surface.

Described the second opening 207 is used to form interior pin, described interior pin is follow-up to be electrically connected to for the chip link with chip structure, therefore described the second opening 207 is formed in the corresponding region of supporting region 201, avoids follow-up cutting technique to cause damage to the pin configuration in the second opening 207.The size of described the second opening 207 is greater than the size of the first opening 203, and therefore described the second opening 207 exposes the first opening 203 part plastic packaging layer 200 surface around.In the present embodiment, described the second opening 207 flushes with the sidewall of the first opening 203 near the sidewall at supporting region 201 edges, and the second opening 207 exposes part plastic packaging layer 200 surface near supporting region 201 centers, described the second opening 207 is used to form interior pin, and therefore described interior pin extends to supporting region 201 center.

Described the second opening 207 is used to form the interior pin of pin configuration, and described interior pin is for being electrically connected to the chip structure of follow-up upside-down mounting on plastic packaging layer 200 first surface 203.The size that described the second opening 207 is parallel to the first insulating sublayer layer 206 surface direction is greater than the size of the first opening 203, and exposes the first opening 203 part plastic packaging layer 200 surface around.Because the interior pin area being formed in the second opening 207 is larger, therefore, when the follow-up chip link that makes chip structure and described interior pin weld, can simplify the difficulty of described welding procedure, make chip link more stable with being electrically connected to of interior pin.

In addition, follow-up after the first opening 203 and the interior formation pin configuration of the second opening 207, because the second opening 207 is greater than the first opening 203, make the interior pin size in the second opening 207 be greater than the outer pin size in the first opening 203, described pin configuration is difficult for coming off in the first opening 203 and the second opening 207; And the contact area between formed pin configuration and plastic packaging layer 200 and the first insulating sublayer layer 206 is larger, can avoid coming off of pin configuration equally.

In another embodiment, described the first insulating sublayer layer and follow-up the second insulating sublayer layer that is formed at the first insulating sublayer layer surface form insulating barrier jointly, in described the second insulating sublayer layer, there is the 3rd opening, the part pin configuration forming in described the 3rd opening is for connecting up to the interior pin in the second opening, to be more conducive to flip-chip again.

Please refer to Fig. 5, in described the first opening 203 (as shown in Figure 4) and the second opening 207 (as shown in Figure 4), fill full electric conducting material, at described the first opening 203 and interior formation the first pin layer 208 of the second opening 204.

In the present embodiment, described the first insulating sublayer layer 206 is formed insulating barrier, described the first pin layer 208 is formed pin configuration, and described the first insulating sublayer layer 206 exposes the first surface 209 of pin configuration, and described plastic packaging layer 200 exposes the second surface 210 of pin configuration.The first surface 209 of described pin configuration and the first insulating sublayer layer 206 flush, the second surface 210 of described pin configuration flushes with the second surface 205 of plastic packaging layer 200.

Owing to first forming the first insulating sublayer layer 206 of plastic packaging layer 200 and plastic packaging layer 200 first surface 204, and in described plastic packaging layer 200, there is the first opening 203, in described the first insulating sublayer layer 206, there is the second opening 207, by at described the first opening 203 and the interior filled conductive material of the second opening 207 to form the first sub-pin layer 208, using as pin configuration, can avoid because of the thermal expansion coefficient difference between capsulation material or insulating material and electric conducting material, and cause the problems such as formed pin configuration generation warped deformation; And, less at the electric conducting material of the first opening 203 and the second opening 207 interior fillings, can avoid the waste to electric conducting material, make work simplification, cost.

Wherein, be used to form the outer pin of pin configuration in described the first opening 203, described outer pin is for making follow-up upside-down mounting be electrically connected to external circuit in the chip structure of pin configuration second surface 210; The interior pin that is used to form pin configuration in described the second opening 207, described interior pin is realized and being electrically connected to by welding with chip structure link.Therefore, the surface that the first surface 209 of described pin configuration is interior pin, the surface that the second surface 210 of described pin configuration is outer pin.First surface 209 areas of described pin configuration are greater than first surface 209, are conducive to make first surface 209 and follow-up chip structure link to be welded to each other; The area of the second surface 210 of described pin configuration is less, can avoid being short-circuited between adjacent outer pin.And the interior pin size being formed in the second opening 207 is greater than the outer pin size in the first opening 203, make the first pin layer 208 be difficult to come off in the first opening 203 and the second opening 207.

The formation technique of described electric conducting material is silk-screen printing technique, described electric conducting material is the alloy of tin or tin, and described ashbury metal is that tin silver, tin are plumbous, one or more combinations in SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, tin silver antimony.In addition, described the first pin layer 208 can also adopt other electric conducting material.

The alloy of described tin or tin has good ductility, be easy to be packed in the first opening 203 and the second opening 207, and can be good with contacting of the first insulating sublayer layer 206 with plastic packaging layer 200, can make that formed the first pin layer 208 pattern are good and interior solid is even.And the alloy of described tin or tin has larger surface tension, in the difficult first opening part outflow from plastic packaging layer second surface of electric conducting material of the first opening 203 and the second opening 207 interior fillings, avoided the loss of electric conducting material.

In one embodiment, second surface 205 when filled electric conducting material surface higher than the first insulating sublayer layer 206 surface or plastic packaging layer 200, can carry out flatening process to the partially conductive material higher than the first insulating sublayer layer 206 surface or plastic packaging layer 200 second surface 205, formed the first pin layer 208 surface are flushed with the first insulating sublayer layer 206 surface and plastic packaging layer 200 second surface 205.

In the present embodiment, formed plastic packaging layer has supporting region and cutting area, and described supporting region is used at subsequent technique flip chip structure, and described cutting area is cut removal in subsequent technique, wherein, in the plastic packaging layer of described supporting region, has the first opening.On described plastic packaging layer surface, form the first insulating sublayer layer with the second opening, and described the second opening exposes the first opening and the first parameatal part plastic packaging layer surface, by filled conductive material in described the first opening and the second opening to form the first pin layer.Because the first pin layer forms by filled conductive material in the first opening and the second opening, thereby reduced the consumption of metal material, can reduce process costs with this, and the technique of filled conductive material has been simple.And, by filled conductive material in the first opening and the second opening, form the first pin layer, make described the first opening and the second opening can define pattern and the structure of described the first pin layer, thereby guarantee that formed pin configuration appearance is good, electrical connection properties stable.In addition, because the size of described the second opening is greater than the size of the first opening, while filling metal material in described the first opening and the second opening, metal material is difficult for overflowing and causing damage from the first opening of plastic packaging layer second surface, and formed the first pin layer is difficult for coming off from the first opening and the second opening.

Accordingly, the present invention also provides a kind of employing said method formed lead frame structure, please continue to refer to Fig. 5, comprising:

Plastic packaging layer 200, described plastic packaging layer 200 has some supporting regions 201 and the cutting area between supporting region 201 202, in described supporting region 201, have some the first opening (not shown) that run through described plastic packaging layer 200, described plastic packaging layer 200 has first surface 204 and the second surface 205 relative with first surface 204;

Be positioned at the insulating barrier of the first surface 204 of described plastic packaging layer 200, in described insulating barrier, there is the second opening (not shown) that exposes the first opening, the size of described the second opening is greater than the size of the first opening, and described the second opening also exposes the first parameatal part plastic packaging layer 200 surface that are positioned at supporting region 201;

Be positioned at the pin configuration of described the first opening and the second opening, described insulating layer exposing goes out the first surface 209 of pin configuration, and described plastic packaging layer exposes the second surface 210 of pin configuration.

Below will be elaborated to said structure.

In the present embodiment, described insulating barrier is the first insulating sublayer layer 206, and described pin configuration is the first pin layer 208.Described the first insulating sublayer layer 206 exposes the first surface 209 of pin configuration, and described plastic packaging layer 200 exposes the second surface 210 of pin configuration.The first surface 209 of described pin configuration and the first insulating sublayer layer 206 flush, the second surface 210 of described pin configuration flushes with the second surface 205 of plastic packaging layer 200.

The outer pin in described the first opening with pin configuration, described the first opening is positioned at supporting region 201; The outer pin in described the second opening with pin configuration, described the second opening is positioned at supporting region 201.Outer pin that described plastic packaging layer 200 second surface 205 expose is follow-up need to be connected with external circuit or form soldered ball; Described interior pin is follow-up to be electrically connected to for the chip link with chip structure.In the present embodiment, described the second opening flushes with the sidewall of the first opening near the sidewall at supporting region 201 edges, and the second opening exposes part plastic packaging layer 200 surface near supporting region 201 centers, the pin that is positioned at the second opening extends to supporting region 201 center.

The material of described the first insulating sublayer layer 206 is solder resist material, and described solder resist material comprises green oil (green paint), polybenzoxazoles (PBO), polyimides (PI); In addition, described solder resist material can also be other insulating material.In the present embodiment, the material of described the first insulating sublayer layer 206 is photic solder resist material

The material of described pin configuration is the alloy of tin or tin, and described ashbury metal is that tin silver, tin are plumbous, one or more combinations in SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, tin silver antimony.In addition, described pin configuration can also adopt other electric conducting material.

In the present embodiment, described plastic packaging layer has supporting region and cutting area, and described supporting region is used at subsequent technique flip chip structure, and described cutting area is cut removal in subsequent technique.Wherein, in the supporting region of described plastic packaging layer, there is the first opening.On described plastic packaging layer surface, have the first insulating sublayer layer, in described the first insulating sublayer layer, have the second opening, described the second opening is positioned at supporting region.Because described the first pin layer is positioned at the first opening and the second opening, and the first opening and the second opening are positioned at supporting region, make to there is part plastic packaging layer between the first pin layer and cutting area and the first insulating sublayer layer is isolated, thereby guaranteed after the described cutting area of follow-up cutting, the formed independently structure for encapsulating, the sidewall surfaces of described the first pin layer still has part plastic packaging layer and the protection of the first insulating sublayer layer, and described the first pin layer only exposes first surface and second surface for being electrically connected to, can avoid described pin configuration to be subject to the pollution of external environment condition, the electrical property of described pin configuration is more stable.

Embodiments of the invention also provide the formation method of another kind of lead frame structure, on the basis of Fig. 5, please continue to refer to Fig. 6 and Fig. 7.

Please refer to Fig. 6, after forming the first pin layer 208, on the first insulating sublayer layer 206 surface, form the second insulating sublayer layer 211, in described the second insulating sublayer layer 211, have the 3rd opening 212 connecting with the second opening 207 (as shown in Figure 4), described the 3rd opening 212 is positioned at the correspondence position of plastic packaging layer 200 supporting region 201.

In the present embodiment, described the second insulating sublayer layer 211 and the first insulating sublayer layer 206 form the insulating barrier of required formation.

In the present embodiment, the material of described the second insulating sublayer layer 211 is solder resist material, and described solder resist material comprises green oil (green paint), polybenzoxazoles (PBO), polyimides (PI).In addition, described the second insulating sublayer layer 211 can also adopt other insulating material.The material of the material of described the second insulating sublayer layer 211 and the first insulating sublayer layer 206 is identical or different.

In the present embodiment, the material of described the second insulating sublayer layer 211 is photic solder resist material, and described photic solder resist material can be exposed development, and directly graphically forms the 3rd opening 212.The formation technique of described the second insulating sublayer layer 211 comprises: adopt spraying or spin coating proceeding to form the second dielectric film at the first insulating sublayer layer 206 and the first pin layer 208 surface; Described the second dielectric film is carried out to exposure imaging, to remove part second dielectric film that need to form the 3rd opening 212, expose part the first insulating sublayer layer 206 and the first pin layer 208 surface, form the second insulating sublayer layer 211.

Adopt photic solder resist material to form the formation work simplification that the second insulating sublayer layer 211 can make the second insulating sublayer layer 211, without the mask layer that is additionally formed for etching; Secondly, avoided the second dielectric film to carry out etching, thus less to the damage on the first pin layer 208 and the first insulating sublayer layer 206 surface; Again, directly the second dielectric film is carried out to exposure imaging, the more accurate easily control of the size of formed the 3rd opening 212 and structure.

In another embodiment, the formation technique of described the second insulating sublayer layer 211 comprises: adopt spraying, spin coating or depositing operation to form the second dielectric film at the first insulating sublayer layer 206 and the first pin layer 208 surface; On described the second dielectric film surface, form mask layer, described mask layer exposes the part second dielectric film surface that need to form the 3rd opening 212; Take described mask layer as mask, and the second dielectric film described in etching, until expose the first insulating sublayer layer 206 and the first pin layer 208 surface, forms the second insulating sublayer layer 211.The material of described the second insulating sublayer layer 211 is different from the material of the first insulating sublayer layer 206, makes described the second dielectric film have Etch selectivity with respect to the first insulating sublayer layer 206.Described in etching, the technique of the second dielectric film is anisotropic dry etch process, makes the sidewall of formed the 3rd opening 212 vertical with respect to the second insulating sublayer layer 211 surface.

Described the 3rd opening 212 is for connecting up to the first pin layer 208 being formed in the first opening 203 (as shown in Figure 4) and the second opening 207 (as shown in Figure 4) again, make to be follow-uply formed at second position of pin layer in the 3rd opening 212 and the chip link of the chip structure of follow-up upside-down mounting adapts, to meet the package requirements of small-size chips physical dimension.

Described the 3rd opening 212 is formed in the corresponding region of supporting region 201, avoids follow-up cutting technique to cause damage to the second pin layer being formed in the 3rd opening 212.In the present embodiment, described the 3rd opening 212 exposes part the first pin layer 208 near supporting region center, and part first insulating sublayer layer 206 surface at close supporting region 201 centers, follow-up the second pin layer being formed in the 3rd opening 212 can extend to supporting region 201 center, distance between relative the second pin layer in same supporting region 201 is dwindled, even if the chip structure size of follow-up upside-down mounting is less, distance between chip link is less, the position of described the second pin layer still can be corresponding with chip link, thereby meet the package requirements of small-size chips structure.

Please refer to Fig. 7, fill full electric conducting material in described the 3rd opening 212 (as shown in Figure 6), form the second pin layer 213, described the second pin layer 213 and the first pin layer 208 form pin configuration.

Described the second pin layer 213 and the second insulating sublayer layer 211 flush.Described the second pin layer 213 surface follow-up by welding realize and chip structure link between electrical interconnection.Because described the 3rd opening 212 exposes near the part first pin layer 208 at supporting region center and part first insulating sublayer layer 206 surface at close supporting region 201 centers, formed the second pin layer 213 extends to supporting region 201 center, and it is less to be formed between relative the second pin layer 213 in same supporting region 201 distance, can meet the package requirements of small-size chips structure.

The formation technique of described electric conducting material is silk-screen printing technique, described electric conducting material is the alloy of tin or tin, and described ashbury metal is that tin silver, tin are plumbous, one or more combinations in SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, tin silver antimony.In addition, described the second pin layer 213 can also adopt other electric conducting material.

The alloy of described tin or tin has good ductility, is easy to be packed in the 3rd opening 212, and can be good with contacting of the second insulating sublayer layer 211, formed the second pin layer 213 pattern are good, interior solid is even.

In one embodiment, when filled electric conducting material surface is during higher than the second insulating sublayer layer 211 surface, partially conductive material higher than the second insulating sublayer layer 211 surface is carried out to flatening process, make formed the second pin layer 213 surface and the second insulating sublayer layer 211 flush.

In the present embodiment, at the first insulating sublayer layer and the first pin layer surface, form the second insulating sublayer layer, in described the second insulating sublayer layer, there is the 3rd opening that exposes part the first insulating sublayer layer and the first pin layer, described the 3rd opening is used to form the second pin layer, and described the second pin layer and the first pin layer form pin configuration.Described the second pin layer is for connecting up to the first pin layer again, and second position on pin layer surface and the chip link of the chip structure of follow-up upside-down mounting that the second insulating sublayer layer is exposed are corresponding, to meet undersized chip structure package requirements.

Accordingly, the present invention also provides a kind of employing said method formed lead frame structure, please continue to refer to Fig. 7, comprising:

Be positioned at the first insulating sublayer layer 206 of the first surface 204 of described plastic packaging layer 200, in described the first insulating sublayer layer 206, there is the second opening (not shown) that exposes the first opening, the size of described the second opening is greater than the size of the first opening, and described the second opening also exposes the first parameatal part plastic packaging layer 200 surface that are positioned at supporting region 201;

Be positioned at the first pin layer 208 of described the first opening and the second opening;

Be positioned at the second insulating sublayer layer 211 on the first insulating sublayer layer 206 surface, have the 3rd opening (not shown) connecting with the second opening in described the second insulating sublayer layer 211, described the 3rd opening is positioned at the correspondence position of plastic packaging layer 200 supporting region 201;

Be positioned at the second pin layer 213 of described the 3rd opening, described the second pin layer 213 and the first pin layer 208 form pin configuration.

Below will be elaborated to said structure.

Described the second insulating sublayer layer 211 and the first insulating sublayer layer 206 form the insulating barrier of required formation.The material of described the second insulating sublayer layer 211 is solder resist material, and described solder resist material comprises green oil (green paint), polybenzoxazoles (PBO), polyimides (PI).In addition, described the second insulating sublayer layer 211 can also adopt other insulating material.The material of the material of described the second insulating sublayer layer 211 and the first insulating sublayer layer 206 is identical or different.In the present embodiment, the material of described the second insulating sublayer layer 211 is photic solder resist material, and described photic solder resist material can be exposed development.

Described the 3rd opening 212 is positioned at the corresponding region of supporting region 201, avoids follow-up cutting technique to cause damage to the second pin layer 213.In the present embodiment, described the 3rd opening 212 exposes part the first insulating sublayer layer 206 surface near the part first pin layer 208 at supporting region 201 centers and close supporting region 201 centers, the the second pin layer that is positioned at the 3rd opening 212 extends to supporting region 201 center, distance between relative the second pin layer in same supporting region 201 is dwindled, can meet the package requirements of small-size chips structure.

In the present embodiment, described the second pin layer and the first pin layer form pin configuration, described the second pin layer is for connecting up to the first pin layer again, second position on pin layer surface and the chip link of the chip structure of follow-up upside-down mounting that the second insulating sublayer layer is exposed are corresponding, meet undersized chip structure package requirements.

Accordingly, the embodiment of the present invention also provides a kind of method for packing, on the basis of Fig. 5, please continue to refer to Fig. 8 to Figure 11, comprising:

Lead frame structure is as shown in Figure 5 provided.

The forming process of described lead frame structure, as described in the embodiment of Fig. 2 to Fig. 5, does not repeat at this.

Please refer to Fig. 8, chip structure 300 is provided, described chip structure 300 surfaces have some chip links 301.

Described chip structure 300 is formed through cutting by wafer, in described chip structure 300, has the integrated circuit consisting of semiconductor device and electric interconnection structure.Described chip link 301 is for being electrically connected to outside.

In the present embodiment, described chip link 301 comprises: the some weld pads 310 that are positioned at chip structure surface; Be positioned at the conductive projection 311 on described weld pad 310 surfaces; Be positioned at the soldered ball 312 on described conductive projection 311 surfaces.Wherein, described weld pad 310 is electrically connected to the integrated circuit of chip structure inside, makes the described weld pad 310 can be as integrated circuit and the outside port being electrically connected to.

In the present embodiment, described chip structure 300 surfaces have separator (not indicating), described separator has the opening that exposes weld pad 310 surfaces, described conductive projection 311 is formed at surface that weld pad 310 exposes and the sidewall surfaces of described separator inner opening, and the surface of described conductive projection 311 is higher than described insulation surface.

The material of described separator is insulating material, and described separator is for surperficial in subsequent technique protective core chip architecture; Described conductive projection 311 is cylinder, and the material of described conductive projection 311 is aluminium, nickel, tungsten, platinum, copper, titanium, chromium, tantalum, tin, ashbury metal, gold or silver-colored; The material of described soldered ball 312 is tin or ashbury metal, and described ashbury metal is that tin silver, tin are plumbous, one or more in SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, tin silver antimony.

In other embodiments, described weld pad 310 surfaces can also only have conductive projection or soldered ball, and described chip link consists of weld pad 310 and conductive projection or has weld pad 310 and soldered ball to form.

In another embodiment, before weld pad 310 surfaces form conductive projection 311 or soldered ball 312, the surface exposing at described weld pad 310 and the sidewall surfaces of described separator inner opening form protruding lower conductiving layer, and described conductive projection 311 or soldered ball 312 are formed at described protruding lower conductiving layer surface.Described protruding lower conductiving layer is for strengthening the bond strength between conductive projection 311 or soldered ball 312 and weld pad 310.

Please refer to Fig. 9, on the insulating barrier on plastic packaging layer 200 supporting region 201 surface, described chip link 300 is electrically connected to the pin configuration first surface 209 in lead frame structure described chip structure 300 upside-down mountings.

Described chip structure 300 is corresponding one by one with supporting region 201; make each chip structure 300 upside-down mounting in a supporting region 201; because described chip structure 300, the first pin layer 208 are all positioned at supporting region 201; follow-up carry out cutting technique after; can not expose the sidewall of described chip structure 300 or the first pin layer 208, chip structure 300 and the first pin layer 208 are protected.

In the present embodiment, described insulating barrier is the first insulating sublayer layer 206, and described pin configuration is the first pin layer 208, and the first surface 209 of described pin configuration is the first pin layer 208 surface that described the first insulating sublayer layer 206 exposes.

In the present embodiment, make described chip link 300 with the method that pin configuration in lead frame structure is electrically connected to be: after described soldered ball 212 contacts with the surface of the first pin layer 208, by reflux technique, described conductive projection 211 is welded together via soldered ball 212 and the first pin layer 208.

Please refer to Figure 10, at surface of insulating layer, chip structure 300 surfaces, pin configuration first surface 209, form the envelope bed of materials 400, the described chip structure 300 of the described envelope bed of material 400 parcel, and fill the space between full insulating barrier and chip structure 300.

The described envelope bed of material 400 is for electricity isolation, to realize the encapsulation to chip structure 300.In the present embodiment, the described envelope bed of material 400 is filled the space between full the first insulating sublayer layer 206 and chip structure 300, surrounds described chip link 300, and is covered in the first insulating sublayer layer 206 surface.

The material of the described envelope bed of material 400 is resin, and described resin can be epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described resin can be also polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol; The described envelope bed of material 400 can also adopt other suitable capsulation material.

The formation technique of the described envelope bed of material 400 is Shooting Technique (injection molding) or turns and mould technique (transfer molding).The described envelope bed of material 400 can also adopt other suitable technique to form.

Please refer to Figure 11, cutting area 202 (as shown in figure 10) along described plastic packaging layer 200 cuts the described envelope bed of material 400, insulating barrier and plastic packaging layer 200, form encapsulating structure, the pin configuration sidewall surfaces in described encapsulating structure has insulating barrier and plastic packaging layer 200 covers.

Because described the first pin layer 208 and chip structure 300 are formed in the corresponding region of supporting region 201, after cutting through described cutting area 202, described the first pin layer 208 still has the first insulating sublayer layer 206 and 200 covering of plastic packaging layer near the sidewall surfaces of cutting area 202, and described the first pin layer 208 only exposes first surface 209 and second surface 210.

Formed encapsulating structure can be electrically connected to outside by the second surface 210 of the first pin layer 208, for example, be connected with PCB circuit board, or be electrically connected to other encapsulating structure or chip structure.

In another embodiment, please refer to Figure 12, after forming the envelope bed of material 400, before carrying out cutting technique, at the second surface 210 formation soldered balls 214 of described pin configuration; After forming described soldered ball 214, carry out cutting technique, and form encapsulating structure.The material of described soldered ball 214 is tin or ashbury metal.

In the present embodiment, by described chip structure upside-down mounting on the insulating barrier on plastic packaging layer supporting region surface, described chip link is electrically connected to the pin configuration first surface in lead frame structure, after forming the envelope bed of material, cutting area along described plastic packaging layer cuts the described envelope bed of material, insulating barrier and plastic packaging layer, to form encapsulating structure.Because described the first opening and the second opening are formed in the corresponding region of plastic packaging layer supporting region; be that formed pin configuration is formed in the corresponding region of plastic packaging layer supporting region; and described chip structure upside-down mounting is on the insulating barrier on plastic packaging layer supporting region surface; therefore; after cutting; described pin configuration sidewall surfaces still has insulating barrier and plastic packaging layer covers; make in formed encapsulating structure; pin configuration is except exposing the first surface and second surface being electrically connected to, and other surface of pin configuration is all by plastic packaging layer and insulating barrier covering protection.Therefore, the surface that can reduce pin configuration is subject to outside contamination infringement, has guaranteed the electric performance stablity of pin configuration.

Accordingly, the embodiment of the present invention also provides a kind of encapsulating structure, please continue to refer to Figure 11, comprising:

Lead frame structure as shown in Figure 5;

Chip structure 300, described chip structure 300 surfaces have some chip links 301;

Described chip structure 300 upside-down mountings, on the insulating barrier on plastic packaging layer 200 supporting region 201 surface, make described chip link 301 be electrically connected to the pin configuration first surface 209 in lead frame structure;

Be positioned at the envelope bed of material 400 of surface of insulating layer, chip structure 300 surfaces, pin configuration first surface 209, the described envelope bed of material 400 wraps up described chip structure 300, also the space between insulating barrier and chip structure 300 is expired in filling;

Described pin configuration sidewall surfaces has insulating barrier and plastic packaging layer 200 covers.

Below will be elaborated to said structure.

In described chip structure 300, there is the integrated circuit being formed by semiconductor device and electric interconnection structure.Described chip link 301 is for being electrically connected to pin configuration.

In the present embodiment, described chip structure 300 surfaces have separator (not indicating), described separator has the opening that exposes weld pad 310 surfaces, described conductive projection 311 is positioned at surface that weld pad 310 exposes and the sidewall surfaces of described separator inner opening, and the surface of described conductive projection 311 is higher than described insulation surface.

The material of described separator is insulating material; Described conductive projection 311 is cylinder, and the material of described conductive projection 311 is aluminium, nickel, tungsten, platinum, copper, titanium, chromium, tantalum, tin, ashbury metal, gold or silver-colored; The material of described soldered ball 312 is tin or ashbury metal, and described ashbury metal is that tin silver, tin are plumbous, one or more in SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium, tin silver antimony.

In another embodiment, between described weld pad 310 and conductive projection 311 or soldered ball 312, also have protruding lower conductiving layer, described conductive projection 311 or soldered ball 312 are positioned at described protruding lower conductiving layer surface.Described protruding lower conductiving layer is for strengthening the bond strength between conductive projection 311 or soldered ball 312 and weld pad 310.

Described chip structure 300 is corresponding one by one with supporting region 201, and each chip structure 300 upside-down mounting is in a supporting region 201.

In the present embodiment; described the first pin layer and chip structure are all positioned at the corresponding region of plastic packaging layer supporting region; therefore; described the first pin layer sidewall surfaces has insulating barrier and plastic packaging layer covers; described the first pin layer is except exposing the first surface and second surface for being electrically connected to; other surface is all protected, and can reduce the extraneous pollution infringement that is subject to of the first pin layer, has guaranteed the electric performance stablity of the first pin layer.

In addition, the embodiment of the present invention also provides another kind of method for packing.

Please refer to Figure 13, comprising:

Lead frame structure is as shown in Figure 7 provided;

Chip structure 300 is provided, and described chip structure 300 surfaces have some chip links 301;

On the second insulating sublayer layer 211 of plastic packaging layer 200 supporting region 201 correspondence, described chip link 301 is connected with the second pin layer 213 surface electrical in lead frame structure described chip structure 300 upside-down mountings;

On the second insulating sublayer layer 211 surface, chip structure 300 surfaces, pin configuration first surface form the envelope bed of material 400, the described chip structure 300 of the described envelope bed of material 400 parcel, and fill the space between full insulating barrier and chip structure 300;

Cutting area 202 pairs of described envelope bed of materials 400, the second insulating sublayer layer 211, the first insulating sublayer layer 206 and plastic packaging layers 200 along described plastic packaging layer 200 cut, form encapsulating structure, the pin configuration sidewall surfaces in described encapsulating structure has the first insulating sublayer layer 206, the second insulating sublayer layer 211 and plastic packaging layer 200 and covers.

Below above-mentioned method for packing is described.

Described the second insulating sublayer layer 211 and the first insulating sublayer layer 206 form the insulating barrier of required formation, described the second pin layer 213 and the first pin layer 208 form pin configuration, described the 3rd opening is positioned at the corresponding region of supporting region 201, is formed at the corresponding region that the second pin layer 213 in the 3rd opening is positioned at supporting region 201.

The technique of described chip structure 300, flip chip structure 300, the envelope bed of material 400 and formation technique thereof do not repeat at this as described in the embodiment of Fig. 8 to Figure 11.

In another embodiment, after forming the envelope bed of material 400, before carrying out cutting technique, at the second surface formation soldered ball of described pin configuration; After forming described soldered ball, carry out cutting technique, and form encapsulating structure.

Accordingly, the embodiment of the present invention also provides another kind of encapsulating structure, please continue to refer to Figure 13, comprising:

Lead frame structure as shown in Figure 7;

Described chip structure 300 upside-down mountings, on the second insulating sublayer layer 211 of plastic packaging layer 200 supporting region 201 correspondence, make described chip link 301 be electrically connected to the pin configuration first surface in lead frame structure;

Be positioned at the envelope bed of material 400 of the second insulating sublayer layer 211 surface, chip structure 300 surfaces, pin configuration first surface, the described envelope bed of material 400 wraps up described chip structure 300, also the space between the second insulating sublayer layer 211 and chip structure 300 is expired in filling;

Described pin configuration sidewall surfaces has the first insulating sublayer layer 206, the second insulating sublayer layer 211 and plastic packaging layer 200 and covers.

In the present embodiment, described the second pin layer is for connecting up to the first pin layer again, because described the second pin layer extends to the center of supporting region, make in same supporting region with respect to the second pin layer between distance dwindle, even if described chip structure size is less, distance between adjacent chips link is less, and described the second pin layer still can meet the package requirements of described small-size chips structure.

Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.

Claims

1. a lead frame structure, is characterized in that, comprising:

2. lead frame structure as claimed in claim 1, is characterized in that, described plastic packaging layer also comprises the cutting area between supporting region.

3. lead frame structure as claimed in claim 1, it is characterized in that, described insulating barrier comprises: the second insulating sublayer layer that is positioned at the first insulating sublayer layer on plastic packaging layer surface and is positioned at the first insulating sublayer layer surface, in described the first insulating sublayer layer, there is the second opening, in described the second insulating sublayer layer, have the 3rd opening connecting with the second opening, described the 3rd opening is positioned at the correspondence position of plastic packaging layer supporting region; Described pin configuration is positioned at described the first opening, the second opening and the 3rd opening.

4. lead frame structure as claimed in claim 3, is characterized in that, the material of described the first insulating sublayer layer is solder resist material, and the material of described the second insulating sublayer layer is solder resist material.

5. lead frame structure as claimed in claim 4, is characterized in that, the material of described the first insulating sublayer layer is photic solder resist material.

6. lead frame structure as claimed in claim 1, is characterized in that, the material of described plastic packaging layer is resin; The material of described insulating barrier is solder resist material; Described electric conducting material is the alloy of tin or tin.

7. lead frame structure as claimed in claim 6, it is characterized in that, described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.

8. the lead frame structure as described in claim 4 or 6, is characterized in that, described solder resist material comprises green oil, polybenzoxazoles or polyimides.

9. lead frame structure as claimed in claim 1, is characterized in that, described supporting region is matrix and arranges.