CN103972195A - 半导体装置及其装配方法 - Google Patents

半导体装置及其装配方法 Download PDF

Info

Publication number
CN103972195A
CN103972195A CN201310078670.0A CN201310078670A CN103972195A CN 103972195 A CN103972195 A CN 103972195A CN 201310078670 A CN201310078670 A CN 201310078670A CN 103972195 A CN103972195 A CN 103972195A
Authority
CN
China
Prior art keywords
dykes
die attach
lead frame
semiconductor device
engaging zones
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310078670.0A
Other languages
English (en)
Inventor
刘鹏
贺青春
齐兆彬
许立强
赵彤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to CN201310078670.0A priority Critical patent/CN103972195A/zh
Priority to US14/077,174 priority patent/US8969135B2/en
Publication of CN103972195A publication Critical patent/CN103972195A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313Wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

本公开涉及半导体装置及其装配方法。一种半导体装置,包括引线框架,具有向下接合区域、管芯粘附区域和形成在向下接合区域和管芯粘附区域间的堤坝件。堤坝件的底部粘附在引线框架的表面上。在管芯粘附工艺中,堤坝件防止来自管芯粘附材料的对向下接合区域的污染。

Description

半导体装置及其装配方法
技术领域
本发明涉及集成电路(IC)装置装配,以及,更具体地,涉及用于半导体封装的引线框架。
背景技术
许多当前的半导体装配工艺包括向下接合(down bonding)工艺,其中管芯电连接到具有接合线的引线框架的向下接合区域上。然而,在向下接合工艺之前,引线框架的向下接合区域会被诸如来自管芯粘附工艺的焊料的管芯粘附材料所污染。
图1示出了具有粘附到引线框架16的管芯粘附区域14的管芯12的部分装配的半导体装置10,其中管芯粘附工艺造成引线框架16的向下接合区域20上的污染物18。接合线22电连接管芯12到引线框架16的向下接合区域20。向下接合区域20上的这样的污染物18使得导线接合具有较低的导线剥落强度。
防止向下接合区域20的污染的一个方法是在向下接合区域20和管芯粘附区域14之间半刻蚀沟槽,以防止管芯粘附材料漏到向下接合区域20中。然而,对于具有小的引线框架和大的管芯的装置而言,没有足够的空间以形成沟槽。此外,半刻蚀工艺会是价格昂贵的。因此,发现一种新方法以防止自管芯粘附材料的对向下接合区域的污染是有好处的。
附图说明
本发明,连同他的目的和优势,可以通过参考优选实施例的如下表述以及附图更好的理解,其中:
图1是部分装配的传统的半导体装置的等距图,示出了向下接合区域中由管芯粘附材料造成的污染;
图2是根据本发明实施例的具有形成在引线框架的向下接合区域和管芯粘附区域间的堤坝件(dam)的部分装配的半导体装置的等距图;
图3是根据本发明另一实施例的具有形成在引线框架的向下接合区域和管芯粘附区域间的堤坝件的部分装配的半导体装置的等距图;
图4A至图4C-2是示出根据本发明实施例的封装半导体装置的步骤的一系列图;以及
图5A-5C是示出根据本发明实施例形成堤坝件的步骤的一系列图。
具体实施方式
下面结合附图的详细阐述,意指目前发明优选实施例的表述,并且不意指代表其中本发明可以实施的仅有的形式。可以理解的是,相同或等同的功能可以通过不同实施例实现,他们意指包含于本发明的精神和范围内。在附图中,相似的数字始终用以代表相似的部件。此外,术语“包含”、“包括”或者其他他们的变体,意指覆盖了非排外的包括,由此包括一系列元件或步骤的模块、电路、装置部件、结构和方法步骤,不仅仅包括这些元件,还包括没有清楚列出的,或者为这些模块、电路、装置元件或者步骤所固有的其他元件或步骤。没有更多的约束,由“包括......”提出的元件或步骤不排除包括元件或步骤的额外的同样的元件或步骤的存在。
在一个实施例中,本发明提供半导体装置,包括:引线框架,其具有向下接合区域和管芯粘附区域,以及在向下接合区域和管芯粘附区域间的堤坝件。堤坝件底部粘附在引线框架的表面上。堤坝件阻止来自管芯粘附材料的对向下接合区域的污染。
在另一实施例中,本发明提供一种半导体装置的封装方法,包括在引线框架上向下接合区域和管芯粘附区域间形成堤坝件的步骤。堤坝件的底部粘附在引线框架的表面上。堤坝件防止自管芯粘附材料的对向下接合区域的污染。
现在参考图2,示出了本发明的部分装配的半导体装置30。半导体装置30包括引线框架32,其具有向下接合区域34、管芯粘附区域36和形成于向下接合区域34与管芯粘附区域36间的堤坝件38。堤坝件38的底部粘附在引线框架32的表面上。当管芯40粘附到引线框架32的管芯粘附区域36时,堤坝件38防止了来自管芯粘附材料42的对向下接合区域34的污染。因此,用接合线44连接的管芯40和向下接合区域34间的电连接有更小的可能产生导线剥落问题。如前面参考图1而讨论的,引线框架16的向下接合区域20会被管芯粘附材料污染,诸如管芯粘附工艺中引入的焊料的溶剂。在本发明的优选实施例中,堤坝件38无缝粘附到引线框架32的表面上。在优选实施例中,堤坝件38由Al、Au或者Cu中的至少一个制成的线而形成,并且使用楔接合设备(wedgebonding apparatus)粘附到引线框架32的表面。在优选实施例中,堤坝件包括一系列的邻接楔或针脚式接合物(stitch bond)。在另一优选实施例中,堤坝件38由固化的粘附胶形成。
参考图3,示出了另一半导体装置50的部分装配视图。部分装配半导体装置50包括引线框架32,其具有向下接合区域34、管芯粘附区域36和和形成于向下接合区域34与管芯粘附区域36间的堤坝件38。堤坝件38的底部粘附在引线框架32的表面上。管芯40粘附到引线框架32的管芯粘附区域36。堤坝件38防止了来自管芯粘附材料42的对向下接合区域34的污染。半导体装置50还包括粘附到第二引线框架56的第二管芯粘附区域54上的第二管芯52。第二管芯52使用接合线58电连接到向下接合区域34。堤坝件38防止向下接合区域34的污染,并且因此向下接合区域34的引线接合连接有更小的可能产生导线剥落问题。如之前图1中讨论的,引线框架16的向下接合区域20会被管芯粘附材料污染,诸如管芯粘附工艺中引入的焊料的溶剂。在本发明的优选实施例中,堤坝件38无缝粘附到引线框架32的表面上。在优选实施例中,堤坝件38由Al、Au或者Cu中的至少一个制成的线而形成,并且使用导线接合设备粘附到引线框架的表面。在另一优选实施例中,堤坝件38由固化的粘附胶形成。
图4A-4C是示出根据本发明实施例的封装半导体装置步骤的一系列图。以图4A开始,在引线框架32的向下接合区域34和管芯粘附区域36间,以将堤坝件38的底部粘附到引线框架32的表面上的方式形成堤坝件38。如前面参考图1所讨论的,引线框架16的向下接合区域20会被管芯粘附材料污染,诸如管芯粘附工艺中引入诸如管芯粘合剂或焊料。在本发明的优选实施例中,堤坝件38无缝粘附到引线框架32的表面上。在优选实施例中,堤坝件38由Al、Au或者Cu中的至少一个制成的线而形成,并且使用楔接合设备粘附到引线框架32的表面。在另一优选实施例中,堤坝件38由固化的粘附胶形成。
在图4B中图示的下面步骤中,管芯40粘附到引线框架32的管芯粘附区域36上,其会导致由管芯粘附材料42造成的在引线框架32表面的污染。然而,如图4B中所示,堤坝件38防止了自管芯粘附材料42的对向下接合区域34的污染。
在图4C中所示的下面的步骤中,在图4C-1中所示的一个实施例中,使用接合线44将管芯40电连接到向下接合区域34。由于堤坝件38防止了来自管芯粘附材料42的对向下接合区域34的污染,用接合线44连接的管芯40和向下接合区域34间的电连接有更小的可能产生导线剥落问题。在图4C-2中所示的另一实施例中,粘附到第二引线框架56上的第二管芯粘附区域54上的第二管芯52用接合线58电连接到向下接合区域34。
图5A-C是示出根据本发明实施例形成堤坝件步骤的一系列图。自图5A开始,借助楔接合设备,导线60的一端粘附到引线框架32的表面,其形成第一针脚式接合物62a,作为向下接合区域34和管芯粘附区域36间的堤坝件38的部分。在优选实施例中,针脚式接合物62a的长度范围是约0.5mm至约0.6mm。
在图5B中所示的下面的步骤中,借助楔接合设备,第二针脚式接合物62b邻近并且毗邻第一针脚式接合物62a形成,作为堤坝件38的另一部分。在优选实施例中,第一和第二针脚式接合物62a、62b至少部分重叠。第一和第二针脚式接合物62a、62b连续形成,直到堤坝件38的长度足够长,以能防止来自管芯粘附材料的对向下接合区域34的污染。在优选实施例中,具有约1.0mm长度的堤坝件38足以防止来自管芯粘附材料的对向下接合区域34的污染。因此,堤坝件38可由两个针脚式接合物形成。
在图5C中所示的下面的步骤中,通过在形成第二针脚式接合物62b之后折断导线60而完成堤坝件38的形成。
因此,本发明的一个实施例中,提供封装半导体装置的方法,包括以下步骤:提供具有管芯粘附区域和向下接合区域的引线框架;以及在引线框架的向下接合区域和管芯粘附区域间形成堤坝件,其中堤坝件的底部粘附到引线框架的表面,并且其中堤坝件防止来自管芯粘附材料的对向下接合区域的污染。该方法还可以包括以下步骤:将第一管芯粘附到管芯粘附区域;以及使用接合线将第一管芯电连接到向下接合区域。在另一实施例中,该方法还可以包括:粘附第一管芯至管芯粘附区域上;以及使用接合线将粘附到第二引线框架的第二管芯粘附区域上的第二管芯电连接到向下接合区域。在该方法中,堤坝件无缝粘附到第一引线框架的表面上。堤坝件可以由导线形成,诸如Al、Cu或Au线,并且通过针脚式接合工艺,使用楔接合设备,粘附到引线框架的表面。可替换地,堤坝件可以由固化的粘附胶形成。
为了图示和说明的目的,呈现本发明的优选实施例的表述,但是不意指是无遗漏的,或者限制本发明为公开的形式。对于本领域的技术人员来说,可以理解的是,在不脱离发明广义发明思路的情况下,对发明可以做出改变。因此,可以理解的是,本发明不限制为公开的特定实施例,而覆盖如附加的权利要求中定义的本发明的精神和范围之内的修改。

Claims (10)

1.一种半导体装置,包含:
引线框架,具有向下接合区域和管芯粘附区域;以及
堤坝件,形成在所述向下接合区域和所述管芯粘附区域之间,其中所述堤坝件的底部粘附在所述引线框架的表面上,并且其中所述堤坝件防止来自管芯粘附材料的对所述向下接合区域的污染。
2.根据权利要求1的半导体装置,进一步包括:
第一管芯,粘附在所述管芯粘附区域上;以及
接合线,将所述第一管芯电连接至所述向下接合区域。
3.根据权利要求1的半导体装置,进一步包括:
第一管芯,粘附在所述管芯粘附区域上;
第二引线框架,具有第二管芯粘附区域;
第二管芯,粘附在所述第二管芯粘附区域上;以及接合线,将所述第二管芯电连接至所述向下接合区域。
4.根据权利要求1的半导体装置,其中所述堤坝件无缝粘附在所述引线框架的表面上。
5.根据权利要求1的半导体装置,其中堤坝件是导线。
6.根据权利要求5的半导体装置,其中所述导线是Al、Cu和Au导线中的一种。
7.根据权利要求5的半导体装置,其中使用楔接合设备将所述导线粘附到所述第一引线框架的表面。
8.根据权利要求5的半导体装置,其中所述堤坝件包括一系列的毗邻针脚式接合物。
9.根据权利要求8的半导体装置,其中邻近的针脚式接合物至少部分重叠。
10.根据权利要求1的半导体装置,其中所述堤坝件由固化的粘附胶形成。
CN201310078670.0A 2013-01-28 2013-01-28 半导体装置及其装配方法 Pending CN103972195A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201310078670.0A CN103972195A (zh) 2013-01-28 2013-01-28 半导体装置及其装配方法
US14/077,174 US8969135B2 (en) 2013-01-28 2013-11-11 Semiconductor device and method of assembling same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310078670.0A CN103972195A (zh) 2013-01-28 2013-01-28 半导体装置及其装配方法

Publications (1)

Publication Number Publication Date
CN103972195A true CN103972195A (zh) 2014-08-06

Family

ID=51241531

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310078670.0A Pending CN103972195A (zh) 2013-01-28 2013-01-28 半导体装置及其装配方法

Country Status (2)

Country Link
US (1) US8969135B2 (zh)
CN (1) CN103972195A (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW550716B (en) * 2001-02-27 2003-09-01 Chippac Inc Plastic semiconductor package
US6759307B1 (en) * 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
CN1821803A (zh) * 2005-02-18 2006-08-23 雅马哈株式会社 引线框架、包含引线框架的传感器和及其形成方法
CN101958299A (zh) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 双面图形芯片直接置放先镀后刻单颗封装方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227663A (en) * 1989-12-19 1993-07-13 Lsi Logic Corporation Integral dam and heat sink for semiconductor device assembly
US5239131A (en) 1992-07-13 1993-08-24 Olin Corporation Electronic package having controlled epoxy flow
WO2002069374A2 (en) * 2001-02-27 2002-09-06 Chippac, Inc. Tape ball grid array semiconductor package structure and assembly process
US6955941B2 (en) * 2002-03-07 2005-10-18 Micron Technology, Inc. Methods and apparatus for packaging semiconductor devices
US7289326B2 (en) 2006-02-02 2007-10-30 Sun Microsystems, Inc. Direct contact cooling liquid embedded package for a central processor unit
US7414310B2 (en) * 2006-02-02 2008-08-19 Stats Chippac Ltd. Waferscale package system
US8633059B2 (en) * 2011-05-11 2014-01-21 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759307B1 (en) * 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
TW550716B (en) * 2001-02-27 2003-09-01 Chippac Inc Plastic semiconductor package
CN1821803A (zh) * 2005-02-18 2006-08-23 雅马哈株式会社 引线框架、包含引线框架的传感器和及其形成方法
CN101958299A (zh) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 双面图形芯片直接置放先镀后刻单颗封装方法

Also Published As

Publication number Publication date
US8969135B2 (en) 2015-03-03
US20140246767A1 (en) 2014-09-04

Similar Documents

Publication Publication Date Title
CN101593736B (zh) 半导体装置及其制造方法
US10373894B2 (en) Package structure and the method to fabricate thereof
CN100565828C (zh) 传感器芯片的封胶方法
US10636735B2 (en) Package structure and the method to fabricate thereof
CN205427873U (zh) 指纹感测单元及指纹感测模块
CN104810299A (zh) 电子部件、布置和方法
EP1338397A3 (en) Method for manufacturing encapsulated electronic components
TWI587413B (zh) 引線框架上的焊料阻流塞
US20150187683A1 (en) Qfn package and method for forming qfn package
CN103579029A (zh) 封装结构及其制造方法
CN103972195A (zh) 半导体装置及其装配方法
EP1909323A3 (en) Semiconductor device and method for manufacturing the same
CN104167403B (zh) 多脚封装的引线框架
US11444012B2 (en) Packaged electronic device with split die pad in robust package substrate
CN103258921A (zh) 发光二极管封装方法
US10068882B2 (en) High-frequency module
CN206806338U (zh) 薄型化双芯片的叠接封装结构
JP4763554B2 (ja) 半導体装置の製造方法
CN104299955B (zh) 一种方形扁平无引脚封装
JP2009289966A (ja) 半導体装置及びその製造方法
US11049836B2 (en) Bond wire support systems and methods
JP2010034261A (ja) 光結合型半導体リレー
EP1628338A1 (en) The manufacturing method of a modularized leadframe
KR200165742Y1 (ko) 반도체 패키지
JPH0452997Y2 (zh)

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: Texas in the United States

Applicant after: NXP America Co Ltd

Address before: Texas in the United States

Applicant before: Fisical Semiconductor Inc.

WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20140806