CN103972139A - Calibration method for improving wafer spike annealing uniformity - Google Patents
Calibration method for improving wafer spike annealing uniformity Download PDFInfo
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- CN103972139A CN103972139A CN201410215824.0A CN201410215824A CN103972139A CN 103972139 A CN103972139 A CN 103972139A CN 201410215824 A CN201410215824 A CN 201410215824A CN 103972139 A CN103972139 A CN 103972139A
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- wafer
- mechanical arm
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- resistance
- spike annealing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
Abstract
The invention discloses a calibration method for improving wafer spike annealing uniformity. A wafer is conveyed to a round support ring through a mechanical arm and then annealed, and the annealed wafer is placed on a resistance value measuring device, so that resistance of the wafer is measured. According to the distribution of measured resistance values, a computer system automatically calculates and judges the center point of the actual temperature distribution of the support ring. According to the center point, a motor control plate controls the mechanical arm to automatically calibrate the target position, on the support ring, of a next wafer which waits for spike annealing, wafer annealing uniformity is guaranteed, and it is avoided that the resistance values are high on one side of the wafer and low on the other side of the wafer. The spike annealing uniformity effect can be rapidly and accurately improved so that junction depth distribution uniformity of doped elements in the wafer can be guaranteed, and time and labor are saved.
Description
Technical field
The present invention relates to ic manufacturing technology field, more particularly, relate to the calibration steps that improves wafer spike annealing homogeneity in a kind of process for fabrication of semiconductor device.
Background technology
Along with the development of semi-conductor industry, integrated circuit is little to volume, speed fast and low-power consumption future development.Especially constantly scaled when the characteristic size of semiconductor device, the horizontal and vertical diffusion of its doped chemical after annealing also requires corresponding reducing, and junction depth is shallow.For the diffusion of controlled doping element and obtain more shallow junction depth, the annealing process that industry generally adopts is spike annealing.Spike annealing technique is to utilize the thermal source of heating wafer to be raised to fast to the temperature of 900～1200 ℃, fast cooling then, whole process approximately 1.5 seconds.
For spike annealing technique, industry main flow equipment adopts wafer filler ring supporting wafer, refers to Fig. 1, and Fig. 1 is the schematic diagram that the Temperature Distribution central point (O2 point) of filler ring in prior art overlaps with crystal circle center's point (O1 point).While carrying out spike annealing technical process, mechanical arm first transmits wafer to the target location of filler ring, and heating unit heats wafer frontside, and meanwhile, wafer filler ring drives wafer rotation with certain speed, to guarantee the uniformity of annealing.
Yet, affect filler ring Temperature Distribution because have: the planform of filler ring, drive the planform of the transmission device of filler ring rotation, the annealing time of wafer, diameter wafer, the velocity of rotation of wafer thickness and filler ring etc., so the temperature distributing rule of filler ring is along with different processing technologys changes, the central point of its Temperature Distribution is also along with different processing technologys changes, when the central point of wafer and the Temperature Distribution central point of filler ring appearance skew (as shown in Figure 2), the heat that can cause crystal round fringes to siphon away is on one side many, and the few situation of the heat that another side siphons away, therefore, there is the crystal round fringes heat asymmetric situation that runs off.
If it is asymmetric that crystal round fringes heat runs off, can cause the junction depth skewness of doped chemical in wafer, directly affect the effect of spike annealing.For the symmetry that guarantees that crystal round fringes heat runs off, industry reflects the situation of crystal round fringes heat absorption conventionally with the resistance value distribution schematic diagram on wafer.Refer to Fig. 3, Fig. 3 is when the off-centring shown in Fig. 2 appears in wafer, the resistance value distribution schematic diagram on wafer.As shown in the figure, there is the low situation in high one side on one side in crystal round fringes resistance value distribution.Conventionally, while there is analogue, by engineer, according to resistance value distribution, judge the drift condition of crystal circle center, more artificially adjust the target location that mechanical arm transmits wafer, improve the skew of crystal circle center.
Yet, it will be apparent to those skilled in the art that by artificial judgement and operation, cannot guarantee that the position location of mechanical arm is consistent with the central point of filler ring Temperature Distribution, cannot guarantee the homogeneity of wafer annealing; And expend time in again and manpower.
Summary of the invention
The object of the present invention is to provide a kind of calibration steps and system of improving wafer spike annealing homogeneity, it is by providing the skew of a kind of automatic decision crystal circle center, and adjust the auto-calibration system of mechanical arm, to improve fast and accurately the homogeneity of spike annealing effect, save time and manpower.
For achieving the above object, technical scheme of the present invention is as follows:
Improve calibration steps and the system of wafer spike annealing homogeneity, employing, described method specifically comprises the steps:
Step S1: the wafer after annealing is placed into the resistance measurement of carrying out wafer on resistance measurement device, resistance measurement device is transferred to resistance value change by the resistance value signal recording and send device;
Step S2: resistance value becomes send device this signal to be converted to the size distribution measured value of surveyed wafer resistance value, and the size distribution measured value of surveyed wafer resistance value is transferred to this computer system;
Step S3: computer system is by its logical calculated plate, filter out the coordinate figure [Xmax (abscissa) of maximum resistance on wafer outer ring, Ymax (ordinate), Rmax (resistance)], coordinate figure [Xmin (abscissa) with minimum resistance, Ymin (ordinate), Rmin (resistance)];
Step S4: according to the coordinate figure of the coordinate figure of maximum resistance and minimum resistance, the target location of the wafer that lower a slice is treated to spike annealing on filler ring revised, and is: (Xmin-Xmax) * (Rmax-Rmin)/C in the correction of X-direction; The correction of Y direction is: (Ymin-Ymax) * (Rmax-Rmin)/C, and the former elements of a fix of mechanical arm add the correction of X-axis or Y-axis, as the central point (O point) of revised filler ring Temperature Distribution; Wherein, C is constant, and unit is ohm;
Step S5: judgement correction size, during the correction Liang≤0.01mm of the correction of X-direction or Y direction, mechanical arm is size shown in correction at the amount of movement of X-axis or Y-axis directions of rays; During-0.01mm< correction <0.01mm, the amount of movement of mechanical arm is 0; During correction Liang≤-0.01mm, the moving direction of mechanical arm is that the amount of movement of the inverse direction of X-axis or Y-axis directions of rays is size shown in correction;
Step S6: Electric Machine Control plate is accepted department of computer science's instruction that logical calculated plate spreads out of of unifying, and control mechanical arm with according to the revised elements of a fix, the target location of the wafer that lower a slice is treated to spike annealing on filler ring revised and reorientated.
Purpose of design is herein, computer system is by its logical calculated plate, can filter out the coordinate figure of maximum resistance and the coordinate figure of minimum resistance on wafer outer ring, and can be according to the coordinate figure of the coordinate figure of maximum resistance and minimum resistance, automatically calculate and judge the actual temperature center of distribution point of filler ring, and the target location of the wafer that lower a slice is treated to spike annealing on filler ring revised automatically, and can control mechanical arm at the forward of X-axis or Y-axis ray or be reversed mobile adjustment according to correction, target location with the wafer of lower a slice being treated to spike annealing on filler ring is revised and is reorientated, avoid occurring that the low situation in high one side on one side appears in the resistance value on wafer, guaranteed the junction depth distributing homogeneity of doped chemical in wafer, time and manpower have been saved.
According to a kind of calibration steps and system of improving wafer spike annealing homogeneity of the present invention, employing: be provided with ceramic fibre pad between described mechanical arm and the contact-making surface of wafer.
According to a kind of calibration steps and system of improving wafer spike annealing homogeneity of the present invention, employing, the position error of described mechanical arm is less than 0.01mm.
According to a kind of calibration steps and system of improving wafer spike annealing homogeneity of the present invention, what adopt is, described wafer spike annealing is in obtaining the dark processing technology compared with shallow junction of doped chemical, wafer is raised to fast to the temperature of 800～1200 ℃, then fast cooling, whole process is 1～180 second.
According to a kind of calibration steps and system of improving wafer spike annealing homogeneity of the present invention, employing, described diameter wafer is 50～350mm.
According to a kind of calibration steps and system of improving wafer spike annealing homogeneity of the present invention, employing, the rotating speed of described circular filler ring is per minute 0～300 to turn.
According to a kind of calibration steps and system of improving wafer spike annealing homogeneity of the present invention, employing, the central coordinate of circle of the wafer that the elements of a fix of described mechanical arm are uploaded with mechanical arm is identical.
Purpose of design is herein, between mechanical arm and the contact-making surface of wafer, is provided with ceramic fibre pad, avoids the damage of mechanical arm to wafer; The uniform rotation of circular filler ring, object is to make the homogeneous heating of wafer under thermal source; The quick high-temp annealing of wafer is in order to obtain the dark compared with shallow junction of doped chemical; The central coordinate of circle of the wafer that the elements of a fix of mechanical arm are uploaded with mechanical arm is identical, facilitates the setting of the elements of a fix of mechanical arm coordinate control and wafer.
From technique scheme, can find out, a kind of calibration steps and system of improving wafer spike annealing homogeneity of the present invention, by the skew of automatic decision crystal circle center, automatic adjusting machine tool arm, thereby can improve fast and accurately the homogeneity of spike annealing effect, save time and manpower.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that the Temperature Distribution central point of filler ring in prior art overlaps with crystal circle center's point;
Fig. 2 is the schematic diagram that the Temperature Distribution central point of filler ring in prior art does not overlap with crystal circle center's point;
Fig. 3 is when the off-centring shown in Fig. 2 appears in wafer, the resistance value distribution schematic diagram on wafer;
Fig. 4 is the logic diagram that the present invention improves the calibration program preferred implementation of wafer spike annealing homogeneity;
Fig. 5 is the structure cutaway view of wafer of the present invention while carrying out spike annealing technique on wafer filler ring;
Fig. 6 is that mechanical arm is uploaded the transmission schematic diagram that wafer carries out spike annealing.
In figure: 1-thermal source, 2-filler ring, 3-mechanical arm, 4-wafer.
Embodiment
Below in conjunction with accompanying drawing 3-6, the specific embodiment of the present invention is described in further detail.
It should be noted that, in the following embodiments, the wafer that a slice diameter of take is D300 describes as example.
Refer to Fig. 4, Fig. 4 is the logic diagram that the present invention improves the calibration program preferred implementation of wafer spike annealing homogeneity, first, the mechanical arm 3 that wafer 4 is controlled by the elements of a fix uploads on circular filler ring 2, if coordinate control point is (0,0), unit is mm, and with the thermal source 1 of heating, it is carried out to annealing in process, and have the step of following raising wafer spike annealing homogeneity:
Step S1: the wafer 4 after annealing is placed into the resistance measurement of carrying out wafer 4 on resistance measurement device, resistance measurement device is transferred to resistance value change by the resistance value signal recording and send device, as Fig. 3, Fig. 3 is when the off-centring shown in Fig. 2 appears in wafer, the resistance value distribution schematic diagram on wafer;
Step S2: resistance value becomes send device this signal to be converted to the size distribution measured value of surveyed wafer 4 resistance values, and the size distribution measured value of surveyed wafer 4 resistance values is transferred to this computer system;
Step S3: computer system is by its logical calculated plate, filter out the coordinate figure [Xmax, Ymax, Rmax] of maximum resistance on wafer 4 outer rings, coordinate figure [Xmin with minimum resistance, Ymin, Rmin], as the coordinate figure (130 of maximum resistance,-20,181) and the coordinate figure of minimum resistance (130,40,175);
Step S4: according to the coordinate figure of the coordinate figure of maximum resistance and minimum resistance, the target location of the wafer 4 that lower a slice is treated to spike annealing on filler ring 2 revised, and is: (Xmin-Xmax) * (Rmax-Rmin)/C in the correction of X-direction; The correction of Y direction is: (Ymin-Ymax) * (Rmax-Rmin)/C, and the former elements of a fix of mechanical arm 3 add the correction of X-axis or Y-axis, as the center zero point of revised filler ring Temperature Distribution; Wherein, C is constant, and unit is ohm; Get C=60 ohm, the correction in X-direction is: (Xmin-Xmax) * (Rmax-Rmin)/C=-26mm; The correction of Y direction is: (Ymin-Ymax) * (Rmax-Rmin)/C=6mm;
Step S5: judgement correction size, during the correction Liang≤0.01mm of the correction of X-direction or Y direction, mechanical arm 3 is size shown in correction at the amount of movement of X-axis or Y-axis directions of rays; During-0.01mm< correction <0.01mm, the amount of movement of mechanical arm 3 is 0; During correction Liang≤-0.01mm, the moving direction of mechanical arm 3 is that the amount of movement of the inverse direction of X-axis or Y-axis directions of rays is size shown in correction;
Step S6: Electric Machine Control plate is accepted department of computer science's instruction that logical calculated plate spreads out of of unifying, and control mechanical arm 3 with according to the revised elements of a fix, the target location of the wafer 4 that lower a slice is treated to spike annealing on filler ring 2 revised and reorientated, as Fig. 5 and Fig. 6, according to calculating above the revised elements of a fix, be (26,6), and the target location of the wafer 4 that lower a slice is treated to spike annealing on filler ring 2 revise and reorientate.
Computer system is by its logical calculated plate, can filter out the coordinate figure of maximum resistance and the coordinate figure of minimum resistance on wafer 4 outer rings, and can be according to the coordinate figure of the coordinate figure of maximum resistance and minimum resistance, automatically calculate and judge the actual temperature center of distribution point of filler ring, and the target location of the wafer 4 that lower a slice is treated to spike annealing on filler ring 2 revised automatically, and can control mechanical arm 3 at the forward of X-axis or Y-axis ray or be reversed mobile adjustment according to correction, target location with the wafer 4 of lower a slice being treated to spike annealing on filler ring 2 is revised and is reorientated, avoid occurring that the low situation in high one side on one side appears in the resistance value on wafer, guaranteed the junction depth distributing homogeneity of doped chemical in wafer, and avoided the position of artificial adjustment wafer, and shortened the judgement time of temperature distributing rule and the adjusting operation time of wafer position, improved the efficiency of wafer annealing process, also reduced the cost of product.
In an embodiment, between mechanical arm 3 and the contact-making surface of wafer 4, be provided with ceramic fibre pad.
In an embodiment, the position error of mechanical arm 3 is less than 0.01mm.
In an embodiment, wafer 4 spike annealings are in obtaining the dark processing technology compared with shallow junction of doped chemical, wafer 4 are raised to fast to the temperature of 1100 ℃, fast cooling then, and whole process is 1.5 seconds.
In an embodiment, wafer 4 diameters are 300mm.
In an embodiment, the rotating speed of circular filler ring 2 is per minute 80 to turn.
The central coordinate of circle of the wafer 4 that in an embodiment, the elements of a fix of mechanical arm 3 are uploaded with mechanical arm 3 is identical.
Between the contact-making surface of mechanical arm 3 and wafer 4, be provided with ceramic fibre pad, avoid the damage of 3 pairs of wafers 4 of mechanical arm; The uniform rotation of circular filler ring 2, object is to make the homogeneous heating of wafer under thermal source; The quick high-temp annealing of wafer is in order to obtain the dark compared with shallow junction of doped chemical; The central coordinate of circle of the wafer 4 that the elements of a fix of mechanical arm 3 are uploaded with mechanical arm 3 is identical, facilitates the setting of the elements of a fix of mechanical arm 3 coordinate controls and wafer 4.
Use the calibration steps of a kind of wafer spike annealing homogeneity of the present invention and the actual temperature center of distribution point that filler ring could be calculated and judge to system automatically, and the target location of the wafer that lower a slice is treated to spike annealing on filler ring revised automatically; Avoid occurring that the low situation in high one side on one side appears in the resistance value on wafer, guaranteed the junction depth distributing homogeneity of doped chemical in wafer; Avoid the position of artificial adjustment wafer, shortened the judgement time of temperature distributing rule and the adjusting operation time of wafer position, improved the efficiency of wafer annealing process, also reduced the cost of product; The central coordinate of circle of the wafer that the elements of a fix of mechanical arm are uploaded with mechanical arm is identical, facilitates the setting of the elements of a fix of mechanical arm coordinate control and wafer.The present invention is applicable to the field of wafer spike annealing in various process for fabrication of semiconductor device.
Above-described is only the preferred embodiments of the present invention; described embodiment is not in order to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (7)
1. a calibration steps that improves wafer spike annealing homogeneity, the mechanical arm (3) that wafer (4) is controlled by the elements of a fix uploads on wafer filler ring (2), and with the thermal source (1) of heating, it is carried out to annealing in process, it is characterized in that, described method specifically comprises the steps:
Step S1: the wafer after annealing (4) is placed into the resistance measurement of carrying out wafer (4) on resistance measurement device, resistance measurement device is transferred to resistance value change by the resistance value signal recording and send device;
Step S2: resistance value becomes send device this signal to be converted to the size distribution measured value of surveyed wafer (4) resistance value, and the size distribution measured value of surveyed wafer (4) resistance value is transferred to this computer system;
Step S3: computer system, by its logical calculated plate, filters out the coordinate figure [Xmax, Ymax, Rmax] of maximum resistance on wafer (4) outer ring, and the coordinate figure of minimum resistance [Xmin, Ymin, Rmin];
Step S4: according to the coordinate figure of the coordinate figure of maximum resistance and minimum resistance, the target location of the wafer (4) that lower a slice is treated to spike annealing on filler ring (2) revised, and is: (Xmin-Xmax) * (Rmax-Rmin)/C in the correction of X-direction; The correction of Y direction is: (Ymin-Ymax) * (Rmax-Rmin)/C, and the former elements of a fix of mechanical arm (3) add the correction of X-axis or Y-axis, as the center zero point of revised filler ring Temperature Distribution; Wherein, C is constant, and unit is ohm;
Step S5: judgement correction size, during the correction Liang≤0.01mm of the correction of X-direction or Y direction, mechanical arm (3) is size shown in correction at the amount of movement of X-axis or Y-axis directions of rays; During-0.01mm< correction <0.01mm, the amount of movement of mechanical arm (3) is 0; During correction Liang≤-0.01mm, the moving direction of mechanical arm (3) is that the amount of movement of the inverse direction of X-axis or Y-axis directions of rays is size shown in correction;
Step S6: Electric Machine Control plate is accepted department of computer science's instruction that logical calculated plate spreads out of of unifying, and control mechanical arm (3) with according to the revised elements of a fix, the target location of the wafer (4) that lower a slice is treated to spike annealing on filler ring (2) revised and reorientated.
2. calibration steps as claimed in claim 1, is characterized in that, between described mechanical arm (3) and the contact-making surface of wafer (4), is provided with ceramic fibre pad.
3. calibration steps according to claim 1, is characterized in that, the position error of described mechanical arm (3) is less than 0.01mm.
4. calibration steps according to claim 1, it is characterized in that, described wafer (4) spike annealing is in obtaining the dark processing technology compared with shallow junction of doped chemical, and wafer (4) is raised to the temperature of 800～1200 ℃ fast, then fast cooling, whole process is 1～180 second.
5. calibration steps according to claim 1, is characterized in that, described wafer (4) diameter is 50～350mm.
6. calibration steps according to claim 1, is characterized in that, the rotating speed of described circular filler ring (2) is per minute 0～300 to turn.
7. calibration steps according to claim 1, is characterized in that, the central coordinate of circle of the wafer (4) that the elements of a fix of described mechanical arm (3) are uploaded with mechanical arm (3) is identical.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110289224A (en) * | 2019-06-19 | 2019-09-27 | 上海华力集成电路制造有限公司 | A kind of accurate method for monitoring and improving square resistance and measure stability |
| CN111599744A (en) * | 2019-02-21 | 2020-08-28 | 细美事有限公司 | Apparatus and method for processing substrate |
| CN112420541A (en) * | 2020-11-18 | 2021-02-26 | 上海华力集成电路制造有限公司 | Monitoring method for source-drain annealing process of wafer product |
| CN112614780A (en) * | 2020-12-16 | 2021-04-06 | 上海华力微电子有限公司 | Wafer spike annealing monitoring method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290362A (en) * | 2011-07-22 | 2011-12-21 | 清华大学 | Method for correcting positioning error of wafer during laser processing |
-
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- 2014-05-20 CN CN201410215824.0A patent/CN103972139B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290362A (en) * | 2011-07-22 | 2011-12-21 | 清华大学 | Method for correcting positioning error of wafer during laser processing |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599744A (en) * | 2019-02-21 | 2020-08-28 | 细美事有限公司 | Apparatus and method for processing substrate |
| CN111599744B (en) * | 2019-02-21 | 2023-07-25 | 细美事有限公司 | Apparatus and method for processing substrate |
| CN110289224A (en) * | 2019-06-19 | 2019-09-27 | 上海华力集成电路制造有限公司 | A kind of accurate method for monitoring and improving square resistance and measure stability |
| CN110289224B (en) * | 2019-06-19 | 2021-08-10 | 上海华力集成电路制造有限公司 | Method for accurately monitoring and improving square resistance measurement stability |
| CN112420541A (en) * | 2020-11-18 | 2021-02-26 | 上海华力集成电路制造有限公司 | Monitoring method for source-drain annealing process of wafer product |
| CN112614780A (en) * | 2020-12-16 | 2021-04-06 | 上海华力微电子有限公司 | Wafer spike annealing monitoring method |
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