CN103972118A - Forming method of metal cap of wafer-level copper pillar bump structure - Google Patents

Forming method of metal cap of wafer-level copper pillar bump structure Download PDF

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Publication number
CN103972118A
CN103972118A CN201410229821.2A CN201410229821A CN103972118A CN 103972118 A CN103972118 A CN 103972118A CN 201410229821 A CN201410229821 A CN 201410229821A CN 103972118 A CN103972118 A CN 103972118A
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CN
China
Prior art keywords
metal
opening
dielectric layer
post projection
metal cap
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Pending
Application number
CN201410229821.2A
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Chinese (zh)
Inventor
徐虹
张黎
陈栋
陈锦辉
赖志明
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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Application filed by Jiangyin Changdian Advanced Packaging Co Ltd filed Critical Jiangyin Changdian Advanced Packaging Co Ltd
Priority to CN201410229821.2A priority Critical patent/CN103972118A/en
Publication of CN103972118A publication Critical patent/CN103972118A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked

Abstract

The invention discloses a forming method of a metal cap of a wafer-level copper pillar bump structure, and belongs to the technical field of semiconductor encapsulation. The forming method comprises the following steps: providing a wafer-level chip base body; depositing a dielectric layer on the upper surface of the chip base body, opening a dielectric layer opening just above a chip electrode, and opening a photoresist opening just above the dielectric layer opening by a photolithography technique; electroplating copper pillar bumps in the dielectric layer opening and the photoresist opening by an electroplating process; forming a composite metal layer with a multi-layer structure on the top of the copper pillar bumps by an electroplating or gold leaching process, wherein the composite metal layer with the multi-layer structure comprises a plurality of solder bumps and a plurality of metal layers, and the metal layers are deposited between the adjacent solder bumps; and forming the metal cap of solder-based metal alloy by the composite metal layer with the multi-layer structure through a reflux process. The method provided by the invention can be used for forming the metal cap with alloy solders with a stable component ratio.

Description

A kind of formation method of metal cap of wafer scale copper post projection cube structure
Technical field
A kind of formation method that the present invention relates to metal cap of wafer scale copper post projection cube structure, belongs to semiconductor packaging field.
Background technology
As everyone knows, along with the development of chip processing procedure exceeds Moore's Law, chip density is more and more higher, spacing between chip constantly reduces, have benefited from the superior electric conductivity of copper product, heat conductivility and reliability, copper post projection (Cu pillar) technology with tin metal cap replaces Solder Bumps (solder bump) gradually, becomes and covers brilliant mainstream technology.
But due to tin short texture, intensity is poor, the tin metal cap of being made up of pure tin easily produces metal whisker, its wetability also can passing in time occur deteriorated, make electronic product have inefficacy hidden danger, manufacture scolder because conventionally adopting solder in the industry, conventional method is to select the tin-base alloy solder electrolyte of certain proportioning to form the metal cap of tinbase metal alloy at the top of copper post codeposition by electric plating method, but this tin-base alloy solder bath composition proportioning complexity, also often there is certain deviation in the component ratio of solder in the process of metal cap that forms tinbase metal alloy, especially when the solder of two or more outside detin, be difficult to obtain and stablize proportioning.
Summary of the invention
The object of the invention is to the deficiency of the metal cap of the tinbase metal alloy that overcomes existing copper post projection, the formation method of the metal cap of the wafer scale copper post projection cube structure that a kind of component ratio of solder is stable is provided.
The object of the present invention is achieved like this:
The formation method of the metal cap of a kind of wafer scale copper of the present invention post projection cube structure, it adopts Wafer level packaging to make copper post projection cube structure, its semiconductor device that is wafer scale provides encapsulation, to improve electrical properties, increase density, reduce device size, to reduce costs, and the additional testing of wafer scale, its formation method is as follows:
Provide the chip basal body with several chip electrodes of a wafer scale, the upper surface of the surperficial exposed chip matrix of described chip electrode;
Deposit a dielectric layer at the upper surface of described chip basal body, described dielectric layer is offered dielectric layer opening directly over chip electrode, a surface of described dielectric layer opening exposed chip electrode;
At the surface-coated thick photoresist of the above-mentioned dielectric layer that is provided with dielectric layer opening, and offer photoresist opening by photoetching process directly over dielectric layer opening, form the photoresist layer with photoresist patterns of openings;
By electroplating technology electro-coppering post projection in dielectric layer opening and photoresist opening, the upper surface of described copper post projection is not higher than the upper surface of photoresist layer;
Top at above-mentioned copper post projection forms sandwich construction complex metal layer by plating or gold-leaching technology, and described sandwich construction complex metal layer comprises several tin post projections and several metal levels, and described metal level is deposited between adjacent tin post projection;
Adopt degumming process to remove remaining photoresist;
Described sandwich construction complex metal layer forms the metal cap of tinbase metal alloy by reflux technique.
Alternatively, the thickness range of described metal level is 0.01~0.5 μ m.Described metal level is single layer structure, and its material is Ag, Cu, Zn, Bi or In; Described metal level is sandwich construction, realizes by repeating plating or gold-leaching technology layering, and the material of every one deck is Ag, Cu, Zn, Bi or In.
Further, the upper surface of described sandwich construction complex metal layer is no more than the upper surface of photoresist layer.
Further, the height of described copper post projection is not less than the thickness of dielectric layer.
Further, the opening border of described photoresist opening is greater than the opening border of dielectric layer opening.
Further, the rounded or polygon of the cross section of described dielectric layer opening.
Further, the rounded or polygon of the cross section of described photoresist opening.
Sandwich construction complex metal layer of the present invention forms by metal alloy, metal alloy is the alloy that has estimated performance by adding certain or some element, making metal become (under certain process conditions, as high temperature, vacuum etc.), to improve original performance, as intensity, reliability etc.
the invention has the beneficial effects as follows:
The present invention is by the Ag of plating or gold-leaching technology gradation stringer (thickness is micron order or nanoscale) between some layers of metallic tin (being tin post projection), Cu, Zn, Bi and/or In metal, form the sandwich construction complex metal layer that tin and another or two or more metal form, by the mode refluxing, the sandwich construction complex metal layer metal alloyization on the top of copper post projection is formed again to the metal cap of tinbase metal alloy, compared with traditional plating alloy scolder, the more diversification of composition of the metal cap of the tinbase metal alloy that the method forms, method is simpler, meanwhile, realize the proportioning control of composition by controlling the deposit thickness of each metal level, technological operation is easier, each thin metal layer is embedded between some layers of metallic tin and refluxes and form the metal cap of tinbase metal alloy, can make metal more even diffusely.
Brief description of the drawings
Fig. 1 is the schematic diagram of the embodiment of the copper post convex block package structure of the formation method formation of the metal cap of a kind of wafer scale copper of the present invention post projection cube structure;
Fig. 2 to Fig. 9 is the process flow diagram of the formation method of the metal cap of a kind of wafer scale copper of the present invention post projection cube structure;
In figure:
Chip basal body 1
Chip electrode 11
Dielectric layer 2
Dielectric layer opening 21
Photoresist layer 3
Photoresist opening 31
Copper post projection 4
Metal cap 5
Tin post projection I 511
Tin post projection II 512
Tin post projection III 513
Metal level I 521
Metal level II 522.
Embodiment
Now will with reference to accompanying drawing, the present invention be described more fully hereinafter, exemplary embodiment of the present invention shown in the drawings, thus scope of the present invention is conveyed to fully those skilled in the art by the disclosure.But the present invention can realize in many different forms, and should not be interpreted as being limited to the embodiment setting forth here.
The embodiment of the copper post convex block package structure that the formation method of the metal cap of a kind of wafer scale copper of the present invention post projection cube structure forms, as shown in Figure 1.The upper surface of chip basal body 1 of the wafer scale of passivation layer (not shown) is anticipated with several chip electrodes 11 in surface, and chip electrode 11 needs to arrange by array or technique, the upper surface of the surperficial exposed chip matrix 1 of chip electrode 11.Be provided with the dielectric layer 2 of dielectric layer opening 21 at the upper surface of chip basal body 1, dielectric layer opening 21 be positioned at chip electrode 11 directly over.The shape of cross section of dielectric layer opening 21 can be circular, also can be the polygons such as rectangle, hexagon, conventionally, the shape of cross section of dielectric layer opening 21 is consistent with the shape of cross section of chip electrode 11, and the cross-sectional boundaries of dielectric layer opening 21 does not exceed the cross-sectional boundaries of chip electrode 11.At the interior copper post projection 4 of height higher than dielectric layer 2 that arrange of dielectric layer opening 21.The lower end of copper post projection 4, i.e. part in dielectric layer opening 21, is limited by the shape of dielectric layer opening 21, forms the shape of cross section identical with the shape of cross section of dielectric layer opening 21; The upper end of copper post projection 4, i.e. part outside dielectric layer opening 21, its shape of cross section can be identical with the shape of cross section of the lower end of copper post projection 4, also can make according to actual needs, as the cross section of the lower end of copper post projection 4 is square, the cross section of its upper end can be square also can be rounded.The metal cap 5 of tinbase metal alloy is set on the top of copper post projection 4, its material is mainly Sn, a kind of or wherein several combination arbitrarily in doping Ag, Cu, Zn, Bi, In etc., as Sn-Ag, Sn-Cu, Sn-Zn, Sn-Bi, Sn-In, Sn-Ag-Cu, with overcome the intensity of pure tin metal cap poor, easily produce the existing defects such as metal whisker, contribute to copper post convex block package structure to be connected with substrate.
The formation method of the metal cap of the wafer scale copper post projection cube structure of above-described embodiment is as follows:
As shown in Figure 2, provide the chip basal body 1 with several chip electrodes 11 of a wafer scale, passivation layer (not shown) has been anticipated on the surface of chip basal body 1, the upper surface of the surperficial exposed chip matrix 1 of chip electrode 11.
As shown in Figure 3, deposit a dielectric layer 2 at the upper surface of said chip matrix 1, described dielectric layer 2 is offered dielectric layer opening 21, the surface of exposed chip electrode 11 directly over chip electrode 11.
As shown in Figure 4, at the surface-coated thick photoresist of the above-mentioned dielectric layer 2 that is provided with dielectric layer opening, thick photoresist layer is offered photoresist opening 31 directly over dielectric layer opening 21 by photoetching process, forms the photoresist layer 3 with photoresist patterns of openings;
The opening border of photoresist opening 31 is greater than the opening border of dielectric layer opening 21, and the shape of cross section of photoresist opening 31 and dielectric layer opening 21 can be identical, also can be different.
As shown in Figure 5, by electroplating technology, at dielectric layer opening 21 and the interior electro-coppering post of photoresist opening 31 projection 4, copper post projection 4 is highly not less than the thickness of dielectric layer 2; Electroplate certain thickness tin post projection I 511 at the top of described copper post projection 4, the upper surface of tin post projection I 511 is no more than the upper surface of photoresist layer 3 again.
As shown in Figure 6, form the metal level I 521 being evenly distributed by plating or gold-leaching technology at the upper surface of tin post projection I 511, metal level I 521 can be single layer structure, and its material is Ag, Cu, Zn, Bi, In etc.; Metal level I 521 can be also the sandwich construction that comprises multiple sub-metal levels, multiple sub-metal levels are realized by repeating plating or gold-leaching technology layering, each sub-metal level is evenly distributed, its material is Ag, Cu, Zn, Bi, In etc., select according to actual needs, and the thickness of controlling the sub-metal level that every one deck forms is at micron or nanoscale.
As shown in Figure 7, form the tin post projection II 512 thicker than metal level I 521 by the mode of electroplating on the surface of metal level I 521; Pass through plating or the gold-leaching technology upper surface depositing metal layers II 522 in tin post projection II 512, metal level II 522 can be single layer structure again, and its material is Ag, Cu, Zn, Bi, In etc.; Metal level II 522 can be also the sandwich construction that comprises multiple sub-metal levels, multiple sub-metal levels are realized by repeating plating or gold-leaching technology layering, each sub-metal level deposition evenly, its material is Ag, Cu, Zn, Bi, In etc., select according to actual needs, and the thickness of controlling the sub-metal level that every one deck forms is at micron or nanoscale; Form the tin post projection III 513 thicker than metal level II 522 by the mode of electroplating on the surface of metal level II 522;
The sandwich construction complex metal layer that tin post projection I 511, metal level I 521, tin post projection II 512, metal level II 522, tin post projection III 513 form on copper post projection 4, the upper surface of sandwich construction complex metal layer is no more than the upper surface of photoresist layer 3; Wherein, the thickness range of metal level I 521, metal level II 522 is 0.01~0.5 μ m.
As shown in Figure 8, adopt degumming process to remove remaining photoresist.
As shown in Figure 9, make sandwich construction complex metal layer form the metal cap 5 of tinbase metal alloy by reflux technique.
Adopt the formation method of the metal cap of a kind of wafer scale copper of the present invention post projection cube structure can form the metal cap of the SAC alloy that contains 1.0%Ag and 0.5%Cu, specific as follows: it first electroplates 3 μ m tin posts on copper post projection top, secondly deposit 0.1 μ m silver metal layer on the top of tin post projection, then form 3 μ m tin post projections at the electroplating surface of silver metal layer, again at the surface deposition 0.05 μ m copper metal layer of tin post projection, finally, at the electroplating surface 3.85 μ m tin post projections of copper metal layer, after refluxing, form the metal cap of SAC alloy; Or first electroplate 3 μ m tin post projections on copper post projection top, secondly deposit 0.05 μ m copper metal layer on the top of tin post projection, then form 3 μ m tin post projections at the electroplating surface of copper metal layer, again at the surface deposition 0.1 μ m silver metal layer of tin post projection, finally, at the electroplating surface 3.85 μ m tin post projections of silver metal layer, after backflow, can form equally the metal cap of SAC alloy.Because the thickness of each sub-metal level is all very thin, at micron or nanoscale, conventional reflux temperature can be realized metal alloy, so can adopt conventional reflux temperature to carry out reflux technique.
The formation method of the metal cap of a kind of wafer scale copper of the present invention post projection cube structure is not limited to above preferred embodiment, the thickness of each metal level and sub-metal level thereof need to be determined according to each composition proportion in the metal cap of tinbase metal alloy and tin post bump height, generally speaking, tin post projection is more a little than metal bed thickness; The formation order of each metal level and sub-metal level thereof does not have particular provisions yet; The number of plies of sandwich construction complex metal layer does not limit, determine according to actual needs, sandwich construction complex metal layer on copper post projection generally starts with tin post projection, finish with tin post projection, metal level embeds between adjacent tin post projection, be beneficial to metal alloy, also can make metal diffusion more even; The material of every layer of metal level and sub-metal level thereof can be identical, also can be different.
Therefore any those skilled in the art without departing from the spirit and scope of the present invention, any amendment, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all fall in the protection range that the claims in the present invention define.

Claims (10)

1. a formation method for the metal cap of wafer scale copper post projection cube structure, its formation method is as follows:
Provide the chip basal body with several chip electrodes of a wafer scale, the upper surface of the surperficial exposed chip matrix of described chip electrode;
Deposit a dielectric layer at the upper surface of described chip basal body, described dielectric layer is offered dielectric layer opening directly over chip electrode, a surface of described dielectric layer opening exposed chip electrode;
At the surface-coated thick photoresist of the above-mentioned dielectric layer that is provided with dielectric layer opening, and offer photoresist opening by photoetching process directly over dielectric layer opening, form the photoresist layer with photoresist patterns of openings;
By electroplating technology electro-coppering post projection in dielectric layer opening and photoresist opening, the upper surface of described copper post projection is not higher than the upper surface of photoresist layer;
Top at above-mentioned copper post projection forms sandwich construction complex metal layer by plating or gold-leaching technology, and described sandwich construction complex metal layer comprises several tin post projections and several metal levels, and described metal level is deposited between adjacent tin post projection;
Adopt degumming process to remove remaining photoresist;
Described sandwich construction complex metal layer forms the metal cap of tinbase metal alloy by reflux technique.
2. the formation method of the metal cap of wafer scale copper post projection cube structure according to claim 1, is characterized in that: the thickness of described metal level is less than the thickness of tin post projection.
3. the formation method of the metal cap of wafer scale copper post projection cube structure according to claim 2, is characterized in that: the thickness range of described metal level is 0.01~0.5 μ m.
4. the formation method of the metal cap of wafer scale copper post projection cube structure according to claim 3, is characterized in that: described metal level is single layer structure, its material is Ag, Cu, Zn, Bi or In.
5. the formation method of the metal cap of wafer scale copper post projection cube structure according to claim 3, is characterized in that: described metal level is sandwich construction, realizes by repeating plating or gold-leaching technology layering, and the material of every one deck is Ag, Cu, Zn, Bi or In.
6. according to the formation method of the metal cap of the wafer scale copper post projection cube structure described in any one in claim 1 to 5, it is characterized in that: the upper surface of described sandwich construction complex metal layer is no more than the upper surface of photoresist layer.
7. according to the formation method of the metal cap of the wafer scale copper post projection cube structure described in any one in claim 1 to 5, it is characterized in that: the height of described copper post projection is not less than the thickness of dielectric layer.
8. according to the formation method of the metal cap of the wafer scale copper post projection cube structure described in any one in claim 1 to 5, it is characterized in that: the opening border of described photoresist opening is greater than the opening border of dielectric layer opening.
9. according to the formation method of the metal cap of the wafer scale copper post projection cube structure described in any one in claim 1 to 5, it is characterized in that: the rounded or polygon of the cross section of described dielectric layer opening.
10. according to the formation method of the metal cap of the wafer scale copper post projection cube structure described in any one in claim 1 to 5, it is characterized in that: the rounded or polygon of the cross section of described photoresist opening.
CN201410229821.2A 2014-05-28 2014-05-28 Forming method of metal cap of wafer-level copper pillar bump structure Pending CN103972118A (en)

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CN106868574A (en) * 2015-12-14 2017-06-20 台湾先进系统股份有限公司 Adjustable insoluble anode plate and method for applying adjustable insoluble anode plate to copper column electroplating
US10699948B2 (en) 2017-11-13 2020-06-30 Analog Devices Global Unlimited Company Plated metallization structures
US10957639B2 (en) 2017-02-24 2021-03-23 Commissariat A L'energie Atomique Et Aux Energies Alternatives Electronic component having a transistor and interdigitated fingers to form at least a portion of a capacitive component within the electronic component
CN112992865A (en) * 2021-02-26 2021-06-18 西安微电子技术研究所 Wafer-level bonding process monitoring structure, method and preparation method
CN113173558A (en) * 2020-03-31 2021-07-27 台湾积体电路制造股份有限公司 Method of manufacturing bump or pillar and semiconductor device

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JP2012122115A (en) * 2010-12-10 2012-06-28 Mitsubishi Shindoh Co Ltd METHOD FOR PLATING Ag-Sn ONTO COPPER OR COPPER ALLOY PLATE AND Ag-Sn-PLATED COPPER OR COPPER ALLOY PLATE PRODUCED BY THE METHOD
US20130292827A1 (en) * 2010-02-11 2013-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar Structure having a Non-Planar Surface for Semiconductor Devices

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US20130292827A1 (en) * 2010-02-11 2013-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar Structure having a Non-Planar Surface for Semiconductor Devices
CN102456630A (en) * 2010-10-27 2012-05-16 中国科学院微电子研究所 Method for preparing multi-component brazing filler metal coatings of microelectronic device salient points
JP2012122115A (en) * 2010-12-10 2012-06-28 Mitsubishi Shindoh Co Ltd METHOD FOR PLATING Ag-Sn ONTO COPPER OR COPPER ALLOY PLATE AND Ag-Sn-PLATED COPPER OR COPPER ALLOY PLATE PRODUCED BY THE METHOD

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106868574A (en) * 2015-12-14 2017-06-20 台湾先进系统股份有限公司 Adjustable insoluble anode plate and method for applying adjustable insoluble anode plate to copper column electroplating
US10957639B2 (en) 2017-02-24 2021-03-23 Commissariat A L'energie Atomique Et Aux Energies Alternatives Electronic component having a transistor and interdigitated fingers to form at least a portion of a capacitive component within the electronic component
US10699948B2 (en) 2017-11-13 2020-06-30 Analog Devices Global Unlimited Company Plated metallization structures
US11862518B2 (en) 2017-11-13 2024-01-02 Analog Devices International Unlimited Company Plated metallization structures
CN113173558A (en) * 2020-03-31 2021-07-27 台湾积体电路制造股份有限公司 Method of manufacturing bump or pillar and semiconductor device
CN113173558B (en) * 2020-03-31 2024-03-29 台湾积体电路制造股份有限公司 Method for manufacturing bump or pillar and semiconductor device
CN112992865A (en) * 2021-02-26 2021-06-18 西安微电子技术研究所 Wafer-level bonding process monitoring structure, method and preparation method
CN112992865B (en) * 2021-02-26 2023-07-11 珠海天成先进半导体科技有限公司 Wafer-level bonding process monitoring structure, method and preparation method

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