CN102456630A - Method for preparing multi-component brazing filler metal coatings of microelectronic device salient points - Google Patents
Method for preparing multi-component brazing filler metal coatings of microelectronic device salient points Download PDFInfo
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- CN102456630A CN102456630A CN2010105275765A CN201010527576A CN102456630A CN 102456630 A CN102456630 A CN 102456630A CN 2010105275765 A CN2010105275765 A CN 2010105275765A CN 201010527576 A CN201010527576 A CN 201010527576A CN 102456630 A CN102456630 A CN 102456630A
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- 239000002184 metal Substances 0.000 title claims abstract description 52
- 238000004377 microelectronic Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000945 filler Substances 0.000 title claims abstract description 14
- 238000005219 brazing Methods 0.000 title abstract description 12
- 238000000576 coating method Methods 0.000 title abstract 9
- 238000009713 electroplating Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229910000679 solder Inorganic materials 0.000 claims description 108
- 239000000470 constituent Substances 0.000 claims description 37
- 239000010949 copper Substances 0.000 claims description 31
- 229910052802 copper Inorganic materials 0.000 claims description 27
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 25
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- 239000000758 substrate Substances 0.000 claims description 22
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- 238000002360 preparation method Methods 0.000 claims description 13
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- 238000002161 passivation Methods 0.000 claims description 10
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
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- 238000005530 etching Methods 0.000 claims description 8
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- 238000005289 physical deposition Methods 0.000 claims description 6
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- 230000008021 deposition Effects 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
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- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 238000011161 development Methods 0.000 claims description 3
- 239000006104 solid solution Substances 0.000 claims description 3
- 229910052684 Cerium Inorganic materials 0.000 claims description 2
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- -1 Xi Yin Chemical compound 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- JWVAUCBYEDDGAD-UHFFFAOYSA-N bismuth tin Chemical compound [Sn].[Bi] JWVAUCBYEDDGAD-UHFFFAOYSA-N 0.000 claims description 2
- ZMIGMASIKSOYAM-UHFFFAOYSA-N cerium Chemical compound [Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce] ZMIGMASIKSOYAM-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- 229910052746 lanthanum Inorganic materials 0.000 claims description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 2
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 238000010992 reflux Methods 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 3
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- 238000005260 corrosion Methods 0.000 description 8
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- 238000005275 alloying Methods 0.000 description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
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- 239000000956 alloy Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
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- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The invention discloses a method for preparing multi-component brazing filler metal coatings of microelectronic device salient points, wherein in the method, the base of a microelectronic device is provided with metal column salient points, and the method comprises the following steps: electroplating a main component brazing filler metal coating on the metal column salient points; depositing micro component coatings on the main component brazing filler metal coating; and refluxing the microelectronic device at the preset temperature, and promoting the micro component coatings to be dissolved in the main component brazing filler metal coating, thereby forming the multi-component brazing filler metal coatings on the metal column salient points. According to the method provided by the invention, the process for preparing the multi-component brazing filler metal coatings of the microelectronic device salient points is simplified.
Description
Technical field
The present invention relates to microelectronics technology, relate in particular to a kind of method for preparing microelectronic component salient point multicomponent solder layer.
Background technology
Along with the continuous progress of microelectric technique, the characteristic size of integrated circuit is constantly dwindled, and interconnection density improves constantly.Because the requirement that the user improves constantly circuit functionality, the complexity of chip constantly increases.In this case, rely on the lead-in wire bonding separately and realize that the chip connection becomes more and more difficult.Bump interconnect can be realized on the entire chip surface area, can improve the interconnection density between chip and chip or chip and substrate largely, becomes the mainstream technology of high-density packages gradually.
The salient point preparation method comprises deposition, plating, silk screen printing, plant C4NP technology that ball and IBM develop recently etc.Above-mentioned technology respectively has pluses and minuses.Wherein electroplating Bumping Technology is the major technique of wafer current level salient point preparation.Through assisting of thick glue mask, directly carry out the making of solder layer, obtain salient point through metal etch under high temperature reflux, the salient point at last.For improving electrical property and reliability, often use copper post salient point, promptly first electro-coppering post plates one deck solder at copper capital end then again.The use of solder layer can reduce the required temperature and pressure of assembling, guarantees that also the suffered stress of chip is within safe range simultaneously.The salient point that this copper post combines with solder is the main flow mode of used interconnection in the present first order encapsulation.The general simple use of prior art is electroplated and is realized that selectable brazing filler metal compositions useful is fewer, is difficult to realize the preparation of the above multicomponent salient point of binary solder.
The microalloying of brazing filler metal alloy is a main method that improves solder performance and welding spot reliability.Many documents of delivering have at present all at length been discussed various materials and have been added the influence to solder performance.For example, at following document:
[1]D.Q.Yu，et?al.，J?Alloy?Comp，376(2004)170；
[2]F.Guo，et?al.，JOM，61(2009)39；
[3] B.Li, et al among the J.Electron.Mater.34 (2005) 217, has mentioned the mechanical property that micro-rare earth element can significantly improve solder, and wetability is improved the heterogeneous microstructure of alloy.At following document:
[4]J.Y.Tsai，et?al.，J.Electron.Mater.32(2003)1203；
[5] C.E.Ho, et al. among the J.Mater.Sci:Mater.Electron.18 (2007) 155, has mentioned the growth that the Ni that in the SnAg alloy, adds trace can suppress solder and copper pad interface C u3Sn compound, has positive role for welding spot reliability.At following document:
[6]I.E.Anderson?et?al.，J.Electron.Mater.35(2006)94；
[7] Weiping Liu; Et al.; Electronic Components and Technology Conference; 2009, among the pp 994-1007, mentioned and in the SnAgCu alloy, added microstructure, mechanical property and the reliability that elements such as micro Fe, Ni, Co, Mn, Ce can significantly improve alloy.At following document:
[8] K.Nogita, et al., JOM in 61 (2009) 45, has mentioned in the SnCu alloy and has added 0.05wt%Ni, can refinement welding point interface tissue, reduce micro-crack and generate.
In order to realize electroplating the diversification of salient point composition, some new methods are suggested.For example U.S. Pat 6083773A1 and US6893799B2 use the mode that picks with the mould transfer to make solder layer at copper capital end respectively; Though this mode can realize multiple brazing filler metal compositions useful; But the technology more complicated, obtainable bump density also has considerable restraint.
In realizing process of the present invention, the inventor recognizes that there is following defective in prior art: preparation technology's more complicated of multicomponent solder on the microelectronic component metal column salient point.
Summary of the invention
The technical problem that (one) will solve
The objective of the invention is to solve in the prior art problem of the complicated process of preparation of multicomponent solder layer on the microelectronic component salient point, thereby propose a kind of method for preparing microelectronic component salient point multicomponent solder layer.
(2) technical scheme
The present invention then impels said little component layers to dissolve in the method that said major constituent solder layer forms said multicomponent solder layer through preparing major constituent solder layer and little component layers respectively, has avoided the complicated technology of Direct Electroplating multicomponent solder.
In addition, prepare the little component layers of solder, accurately control the component and the proportioning of multicomponent solder layer by the thickness of little component layers through physical deposition mode.
(3) beneficial effect
Through technical scheme of the present invention, can simplify the preparation technology of microelectronic component salient point, and can obtain high performance multicomponent solder layer.
Description of drawings
Fig. 1 is the flow chart of the preparation microelectronic component salient point multicomponent solder layer method of the embodiment of the invention one;
Fig. 2 is the sketch map of in substrate 1, making passivation layer 3 and selective removal metal pad 2 top, passivation layer of the embodiment of the invention three and embodiment four correspondences;
Fig. 3 is the sketch map that in substrate 1, deposits ubm layer 4 of the embodiment of the invention three and embodiment four correspondences;
Fig. 4 is the making thick photoresist layer 5 in substrate 1 of the embodiment of the invention three and embodiment four correspondences, and passes through the sketch map of exposure, development acquisition salient point patterns of openings;
Fig. 5 is the sketch map that passes through to electroplate acquisition copper post 6 and solder master component layer 7 of the embodiment of the invention three and embodiment four correspondences;
Fig. 6 is the sketch map that photoresist 5 is removed of the embodiment of the invention three correspondences;
Fig. 7 is the sketch map that the embodiment of the invention three corresponding modes of passing through sputter are made the little component layer 8 of solder;
Fig. 8 is that the embodiment of the invention three corresponding high temperature refluxes that pass through are handled the sketch map that obtains alloying solder layer 9;
Fig. 9 be the embodiment of the invention three corresponding be that mask etching is removed the sketch map after little component layer and the ubm layer with the salient point;
Figure 10 is the sketch map that the embodiment of the invention four corresponding modes of passing through sputter are made the little component layer 8 of solder;
Figure 11 is the sketch map with photoresist 5 and little component layer 8 removal of photoresist 5 top solders of the embodiment of the invention four correspondences;
Figure 12 is that the embodiment of the invention four corresponding high temperature refluxes that pass through are handled the sketch map that obtains alloying solder layer 9;
Figure 13 be the embodiment of the invention four corresponding be that mask etching is removed the sketch map after the ubm layer with the salient point.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
Embodiment one:
Fig. 1 is the flow chart of the preparation microelectronic component salient point multicomponent solder layer method of the embodiment of the invention one.As shown in Figure 1, this method comprises:
Step S102 electroplates the major constituent solder layer on the metal column salient point;
Step S104, the little component layers of deposition on the major constituent solder layer;
Step S106 refluxes to microelectronic component under preset temperature, impels little component layers to dissolve in the major constituent solder layer, on the metal column salient point, forms the multicomponent solder layer.
In the present embodiment, should prepared beforehand metal column salient point in the substrate of microelectronic component.And above-mentioned preset temperature should guarantee that the little component layers of solder dissolves in the major constituent solder layer, and forms the multicomponent solder layer.This preset temperature is determined by the material and the thickness of major constituent solder layer and little component layers.Present embodiment provides a kind of method for preparing microelectronic component salient point multicomponent solder layer, has avoided the complicated technology of Direct Electroplating multicomponent solder layer.
Embodiment two:
In prior art, Direct Electroplating multicomponent solder layer can't accurately be controlled its set of dispense ratio, and on the basis of embodiment one, embodiment two has provided the technical scheme of control multicomponent solder layer composition.In embodiment two, through little component layers and major constituent thickness of filler ratio, the set of dispense ratio of control multicomponent solder layer.Wherein, the control to little component layers deposit thickness is key wherein.The present invention utilizes the advantage of physical deposition mode good reliability, adopts physical deposition mode on the major constituent solder layer, to deposit little component layers, accurately controls the thickness of little component layers, thereby reaches the purpose of accurate control multicomponent solder layer set of dispense ratio.Preferably, physical deposition mode is sputter or evaporation.
In addition, " little component layers is dissolved in the major constituent solder layer " of indication comprises following a kind of situation at least among the present invention: little component layers is dissolved in the major constituent solder layer, forms solid solution; Or little component layers and major constituent solder layer reacting generating compound.
Embodiment three:
Present embodiment and embodiment four will be that example describes from the complete preparation process of microelectronic component salient point.In the present embodiment, the processing of metal pad has been accomplished in the substrate of used microelectronic component, and is as shown in Figure 2, and 1 is substrate among Fig. 2, can be the silicon wafer of accomplishing circuit devcie processing, and 2 is metal pad, is generally the top-level metallic of silicon wafer.Follow-up salient point preparation may further comprise the steps:
Step 1: make passivation layer 3, and selective etch falls the passivation layer 3 on metal pad 2 surfaces, as shown in Figure 2.
Wherein, passivation layer 3 can be but be not limited to be silicon nitride (Si
xN
y), silica, polyimides, benzocyclobutane olefine resin materials such as (BCB).The making of passivation layer can strengthen low temperature methods such as chemical vapour deposition (CVD) (PECVD), sputter, spin coating by using plasma.
Step 2:, as shown in Figure 3 at substrate 1 positive bump making process lower metal layer 4.
Ubm layer mainly is for follow-up electroplating technology provides Seed Layer, and can be but be not limited to be titanium/copper (Ti/Cu) or the metallic combinations such as (TiW/Cu) of titanium tungsten/copper.
Step 3: make thick photoresist layer 5, and through exposure, the acquisition salient point patterns of openings of developing, as shown in Figure 4.
The making of thick photoresist layer can be used the mode of liquid photoresist spin coating, the mode that also can use the dry film photoresist to paste, and photoresist thickness will surpass the height dimension of the salient point of required making.
Step 4: use the mode of electroplating, make metal column salient point 6 and major constituent solder layer 7, as shown in Figure 5.
The major constituent solder layer can have multiple, so long as the material that can make through plating mode all can, present embodiment uses the major constituent of tin material as solder.The thickness of tin is selected according to the solder alloy component that will obtain.In the present embodiment, the metal column salient point is the copper post.
Step 5: remove thick photoresist layer 5, as shown in Figure 6.
The removal of thick photoresist can be used but the mode that is not limited to use ultrasonic auxiliary acetone to soak.
Step 6: use vacuum-deposited mode to make the little component layers 8 of solder, as shown in Figure 7.
The vacuum moulding machine mode can be but be not limited to be technologies such as sputter, evaporation; Controllability for technology; The thickness of preferred little component layers 8 is between 0.5 nanometer to 1 micron; Can be that homogenous material also can be the lamination of a plurality of materials, concrete thickness and composition be selected according to solder major constituent layer thickness and required brazing filler metal compositions useful.The main solder of for example electroplating is Sn-1Ag, and thickness is 30 microns, and target solder bump composition is Sn-1Ag-0.01Ni, and known Sn-1Ag density is 7.39g/cm3, and the density of nickel is 8.9g/cm
3, the thickness of the nickel that need deposit so is 2.5 nanometers.
Step 7: high temperature reflux, form alloying solder layer 9, as shown in Figure 8.
According to solder layer material therefor type and set of dispense ratio, select suitable reflux temperature control curve, after the high temperature reflux, little component layers is dissolved within the major constituent solder layer, forms alloy material.Be prepared as example with above-mentioned Sn-1Ag-0.01Ni salient point and explain that 2.5 nanometer nickel are dissolved in the process of 30 micron thick Sn-1Ag solders.Known to 270 degree, the speed that Ni is dissolved in pure tin is 2.5 * 10
-6Cm/s.Therefore thickness is that the Ni of 2.5 nanometers is dissolved in the pure tin required time and is merely 0.1 second.Under the unleaded reflux technique condition of typical case, promptly the highest reflux temperature 260 degree, about 20 seconds of time, Sn-1Ag can dissolve these nickel fully.According to present research, because the solubility of nickel in Sn is very little, therefore, sub-fraction nickel is dissolved in Sn and forms solid solution, and a part can generate Ni
3Sn
4Intermetallic compound.
Step 8: with the salient point is little component layers 8 of mask etching and ubm layer 4, accomplishes the salient point manufacturing, as shown in Figure 9.
Little component layers in zone does not have alloying outside the salient point, can use corresponding corrosive liquid to remove, though salient point itself comprises little component material, alloying is dissolved in the major constituent solder, and material character changes, and can keep out the corrosiveness of corresponding solution.For suprabasil little component layers,, be easy to etching because it is very thin.For example prepare above-mentioned Sn-1Ag-0.01Ni salient point, nickel layer thickness is merely 2.5 nanometers.And for ubm layer, the embodiment of the invention is used the combination of titanium and copper, uses copper corrosion liquid and titanium corrosive liquid to handle substrate respectively.If select the corrosive liquid of etching copper and mickel simultaneously, then need not increase etch step.Through above-mentioned etch step, can remove little component solder layer and ubm layer clean.In order to reduce of the influence of copper corrosion liquid, use the lower copper corrosion liquid of corrosion rate to the copper post.
Embodiment four:
Embodiment four used substrates are identical with embodiment three, and step 1 is also identical with embodiment three to step 4, repeats no more here, and follow-up step is following:
Step 5: use vacuum-deposited mode to make little component layers 8, shown in figure 10.
The vacuum moulding machine mode can be but be not limited to be technologies such as sputter, evaporation; Controllability for technology; The thickness of preferred little component solder layer 8 is between 0.5 nanometer to 1 micron; Can be that homogenous material also can be the lamination of a plurality of materials, concrete thickness and composition be selected according to solder major constituent thickness and required brazing filler metal compositions useful.For example, if the plating solder is a pure tin, thickness is 30 microns, and the component of target solder is Sn-0.7Cu, and the density of known copper is 8.9g/cm
3, the density of tin is 7.2g/cm
3, through calculating, the thickness of deposited copper should be 0.17 micron on tin material so.
Step 6: remove the little component layers 8 on thick photoresist layer 5 and the thick photoresist layer 5, shown in figure 11.
The removal of thick photoresist can be used but the mode that is not limited to use ultrasonic auxiliary acetone to soak.
Step 7: high temperature reflux, form alloying solder layer 9, shown in figure 12.
According to solder layer material therefor type and set of dispense ratio, select suitable reflux temperature control curve, after the high temperature reflux, little component layers is dissolved within the major constituent solder layer, forms alloy material.
Step 8: with the salient point is mask etching ubm layer 4, accomplishes the salient point manufacturing, shown in figure 13.
Metal is the combination of titanium and copper under the salient point that the embodiment of the invention is used, and uses copper corrosion liquid and titanium corrosive liquid to handle substrate respectively, and ubm layer is removed totally, in order to reduce the influence of copper corrosion liquid to the copper post, uses the lower copper corrosion liquid of corrosion rate.
Embodiment one is illustrated with the method that two couples of embodiment prepare microelectronic component salient point multicomponent solder layer; Embodiment three is illustrated with four pairs of complete methods that prepare the microelectronic component salient point of embodiment.Among above-mentioned each embodiment, substrate can be a kind of in silicon, germanium silicon, GaAs, silicon-on-insulator semi-conducting materials such as (SOI) or glass, pottery, the sapphire insulation material.The metal column salient point can be in copper, nickel, the gold a kind of; The metal column bump height can be between 1 micron to 100 microns.Used solder master component layer can be a kind of material in metallic tin, indium, Xi Yin, tin copper, tin indium, tin bismuth, the SAC.The thickness of solder master component layer can be between 1 micron to 100 microns.The little component layer of used solder can be one or more combination in the metal materials such as silver, copper, platinum, gold, titanium, palladium, germanium, aluminium, manganese, nickel, iron, chromium, cobalt, neodymium, cerium, neodymium, lanthanum.The little component layer thickness of solder can be between 0.5 nanometer to 1 micron.
Among embodiment three and the embodiment four, ubm layer is but is not limited to be titanium/copper (Ti/Cu) or titanium tungsten/copper combinations of materials such as (TiW/Cu).Make thick photoresist and adopt modes such as liquid photoresist spin coating or the stickup of dry film photoresist.
It should be noted that if no special instructions or each other and conflict that the preparation parameter here can be applied to above-mentioned each embodiment and produce correspondingly technique effect, repeats no more here.
Above specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, the above specific embodiment of the present invention that is merely that it should be understood that; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. a method for preparing microelectronic component salient point multicomponent solder layer is characterized in that having the metal column salient point in the substrate of said microelectronic component, and this method comprises:
Preparation major constituent solder layer on said metal column salient point;
The little component layers of deposition on said major constituent solder layer;
Under preset temperature, said microelectronic component is refluxed, impel said little component layers to dissolve in said major constituent solder layer, on said metal column salient point, form said multicomponent solder layer.
2. the method for preparing microelectronic component salient point multicomponent solder layer according to claim 1 is characterized in that, the material and the thickness of the corresponding said major constituent solder layer of said preset temperature and said little component layers.
3. the method for preparing microelectronic component salient point multicomponent solder layer according to claim 1 is characterized in that, through said little component layers and said major constituent thickness of filler ratio, controls the set of dispense ratio of said multicomponent solder layer.
4. the method for preparing microelectronic component salient point multicomponent solder layer according to claim 3 is characterized in that, adopts physical deposition mode on said major constituent solder layer, to deposit said little component solder layer.
5. the method for preparing microelectronic component salient point multicomponent solder layer according to claim 4 is characterized in that said physical deposition mode is sputter or evaporation.
6. the method for preparing microelectronic component salient point multicomponent solder layer according to claim 1 is characterized in that, adopts plating mode on said metal column salient point, to prepare the major constituent solder layer.
7. the method for preparing microelectronic component salient point multicomponent solder layer according to claim 1 is characterized in that said little component layers is dissolved in the major constituent solder layer, on the metal column salient point, forms the multicomponent solder layer and comprises following a kind of situation at least:
Said little component layers is dissolved in said major constituent solder layer, forms solid solution; Or
Said little component layers and said major constituent solder layer reacting generating compound.
8. according to the said method for preparing microelectronic component salient point multicomponent solder layer of claim 1, it is characterized in that said major constituent solder layer is a kind of in the following material: tin, indium, Xi Yin, tin copper, tin indium, tin bismuth, SAC.
9. the said according to Claim 8 method for preparing microelectronic component salient point multicomponent solder layer; It is characterized in that said little component layers is one or more combinations in the following material: silver, copper, platinum, gold, titanium, palladium, germanium, aluminium, manganese, nickel, iron, chromium, cobalt, neodymium, cerium, neodymium, lanthanum.
10. according to each described method for preparing microelectronic component salient point multicomponent solder layer in the claim 1 to 9, it is characterized in that,
Saidly also comprise before on the metal column salient point, electroplating the major constituent solder layer: the position at the above metal column salient point of substrate of said microelectronic component prepares metal pad; In the substrate of said microelectronic component, prepare passivation layer; The passivation layer at the said metal pad of selective removal top; In the substrate of said microelectronic component, prepare ubm layer; On said ubm layer, make photoresist layer; Photoresist layer through exposure, the said metal column salient point of development step selective removal position; Plated metal post salient point in the substrate of said microelectronic component;
Saidly on the metal column salient point, also comprise after the preparation major constituent solder layer: remove said photoresist layer;
Saidly under preset temperature, said microelectronic component is refluxed; Impel said little component layers to dissolve in said major constituent solder layer, form said multicomponent solder layer and also comprise afterwards: with said multicomponent solder layer is little component layers remaining in the said microelectronic component substrate of mask etching and the ubm layer except that said metal column salient point position.
11. according to each described method for preparing microelectronic component salient point multicomponent solder layer in the claim 1 to 9, it is characterized in that,
Saidly also comprise before on the metal column salient point, electroplating the major constituent solder layer: the position at the above metal column salient point of substrate of said microelectronic component prepares metal pad; In the substrate of said microelectronic component, prepare passivation layer; The passivation layer at the said metal pad of selective removal top; In the substrate of said microelectronic component, prepare ubm layer; On said ubm layer, make photoresist layer; Photoresist layer through exposure, the said metal column salient point of development step selective removal position; Plated metal post salient point in the substrate of said microelectronic component;
Said on the major constituent solder layer deposition also comprise after little component layers: remove said photoresist layer and reach the little component layers except that said metal column salient point position;
Saidly under preset temperature, said microelectronic component is refluxed; Impel said little component layers to dissolve in said major constituent solder layer, form said multicomponent solder layer and also comprise afterwards: with said multicomponent solder layer is the ubm layer of mask etching except that said metal column salient point position.
12. according to each described method for preparing microelectronic component salient point multicomponent solder layer in the claim 1 to 9, it is characterized in that,
Said metal column salient point is made up of at least a in the following material: copper, nickel, gold; The height of said metal column salient point is between 1 micron to 100 microns.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972118A (en) * | 2014-05-28 | 2014-08-06 | 江阴长电先进封装有限公司 | Forming method of metal cap of wafer-level copper pillar bump structure |
| CN106057692A (en) * | 2016-05-26 | 2016-10-26 | 河南工业大学 | Three-dimensional integrated circuit stack integration method and three-dimensional integrated circuit |
| US20220001475A1 (en) * | 2018-11-06 | 2022-01-06 | Mbda France | Method for connection by brazing enabling improved fatigue resistance of brazed joints |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101617396A (en) * | 2007-03-23 | 2009-12-30 | 英特尔公司 | Copper die bumps with electromigration cap and plated solder |
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2010
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101617396A (en) * | 2007-03-23 | 2009-12-30 | 英特尔公司 | Copper die bumps with electromigration cap and plated solder |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972118A (en) * | 2014-05-28 | 2014-08-06 | 江阴长电先进封装有限公司 | Forming method of metal cap of wafer-level copper pillar bump structure |
| CN106057692A (en) * | 2016-05-26 | 2016-10-26 | 河南工业大学 | Three-dimensional integrated circuit stack integration method and three-dimensional integrated circuit |
| CN106057692B (en) * | 2016-05-26 | 2018-08-21 | 河南工业大学 | A kind of three dimensional integrated circuits storehouse integrated approach and three dimensional integrated circuits |
| US20220001475A1 (en) * | 2018-11-06 | 2022-01-06 | Mbda France | Method for connection by brazing enabling improved fatigue resistance of brazed joints |
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