CN103941510A - TFT array substrate, display panel and display device - Google Patents
TFT array substrate, display panel and display device Download PDFInfo
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- CN103941510A CN103941510A CN201310346856.XA CN201310346856A CN103941510A CN 103941510 A CN103941510 A CN 103941510A CN 201310346856 A CN201310346856 A CN 201310346856A CN 103941510 A CN103941510 A CN 103941510A
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Abstract
The embodiment of the invention provides a TFT array substrate. The TFT array substrate comprises a first substrate body and a pixel array located on the first substrate body. The pixel array comprises a plurality of grid lines, a plurality of data lines intersecting with the grid lines in an insulating mode, a plurality of public lines and pixel units formed in regions defined by the grid lines and the data lines. The pixel units comprise pixel electrodes electrically connected to the data lines, opposite electrodes which are arranged opposite to the pixel electrodes and TFTs, wherein grids of the TFTs are electrically connected to the grid lines, sources/drains of the TFTs are electrically connected to the public lines and the drains/sources of the TFTs are electrically connected to the opposite electrodes. One TFT is shared by N pixel units, wherein N is larger than or equal to two. Compared with the prior art, the TFT array substrate, a display panel and a display device have the advantages that one TFT is shared by at least two pixel units, so that the number of the TFT serving as pixel switches in a display region is greatly reduced, and therefore the aperture opening rate is increased.
Description
Technical field
The present invention relates to flat pannel display field, relate in particular to a kind of tft array substrate, and the display panel that comprises this tft array substrate and display device.
Background technology
The advantages such as liquid crystal display (Liquid Crystal Display, LCD) panel is light, thin with it, low-power consumption are received people's concern.LCD panel mainly comprises tft array substrate (TFT Array Substrate) and the color membrane substrates (Color Filter Substrate) being oppositely arranged, and is arranged at the liquid crystal layer between the two.Conventionally, LCD can be divided into TN(twisted-nematic by its display mode) type, IPS/FFS(flat field switching/fringing field switch) type etc.
Publication number is the IPS type display panels that discloses a kind of novel tft array substrate and comprised this tft array substrate in the Chinese patent application file of CN101286516B.Fig. 1 is the structural representation of a pixel cell in this tft array substrate.Fig. 2 is the electrical block diagram of this tft array substrate.From Fig. 1 and Fig. 2, can find out, this tft array substrate comprises gate line (or sweep trace) 1, in its horizontal direction in drawing, extends; Concentric line (or COM line) 2, is close to and is similar to and be parallel to gate line 1; Data line (or signal wire) 3, this data line 3 extends upward in the side that is approximately perpendicular to gate line 1; The on-off element of TFT6, is configured near the intersection point of gate line 1 and data line 3; Linear pixel electrode 5 and comparative electrode 4, be parallel to data line 3, be configured in by gate line 1 and data line 3 around region in.Pixel electrode 5 and comparative electrode 4 are alternately arranged with predetermined space.An electrode (source electrode or drain electrode) of TFT6 is connected to concentric line 2, and another electrode (drain electrode or source electrode) is connected to comparative electrode 4.Pixel electrode 5 is connected to data line 3.That is to say, common electric voltage is applied to comparative electrode 4 from concentric line 2 by TFT6, and figure signal is directly applied to pixel electrode 5 by data line 3.In addition, liquid crystal capacitance 7 and memory capacitance 8 between pixel electrode 5 and comparative electrode 4, have also been formed.
In above-mentioned prior art, each pixel comprises that near the TFT intersection point that is arranged at gate line 1 and data line 3 is as pixel switch, and these TFT are normally lighttight, make the aperture opening ratio of display panel not high.
Summary of the invention
An embodiments of the invention technical matters to be solved is that, in prior art, each pixel comprises a near TFT of intersection point that is arranged at gate line and data line, makes the aperture opening ratio of display panel not high.
In order to solve the problems of the technologies described above, embodiments of the invention provide a kind of tft array substrate, comprise first substrate, are positioned at the pel array on described first substrate; Described pel array comprises: many gate lines; Many data lines that intersect with described many gate lines insulation; Many concentric lines; Be formed at the pixel cell in described gate line and data line institute region, comprise: pixel electrode, is electrically connected to described data line; The comparative electrode being oppositely arranged with described pixel electrode; And TFT, the grid of described TFT is electrically connected to described gate line, and the source/drain of described TFT is electrically connected to described concentric line, and the drain/source of described TFT is electrically connected to described comparative electrode; Wherein, N pixel cell shares a TFT, N >=2.
Embodiments of the invention also provide a kind of display panel, comprise above-mentioned tft array substrate; The color membrane substrates being oppositely arranged with described tft array substrate, and be arranged at the liquid crystal layer between described tft array substrate and described color membrane substrates.
Embodiments of the invention also provide a kind of display device, comprise above-mentioned display panel.
In terms of existing technologies, the tft array substrate that embodiments of the invention provide, display panel and display device, at least two pixel cells share TFT, make in viewing area to greatly reduce as the quantity of the TFT of pixel switch, thereby have improved aperture opening ratio.
Accompanying drawing explanation
Fig. 1 is the structural representation of a pixel cell in the tft array substrate of prior art;
Fig. 2 is the electrical block diagram of the tft array substrate of prior art;
The vertical view of the tft array substrate that Fig. 3 provides for embodiment mono-;
The electrical block diagram of the tft array substrate that Fig. 4 provides for embodiment mono-;
Fig. 5 is the cut-open view of AA ' in Fig. 3;
Fig. 6 is the cut-open view of BB ' in Fig. 3;
The vertical view of the tft array substrate that Fig. 7 provides for embodiment bis-;
The electrical block diagram of the tft array substrate that Fig. 8 provides for embodiment bis-;
The vertical view of the TFT that Fig. 9 provides for embodiment tri-;
Figure 10 is the cut-open view of CC ' in Fig. 9;
Figure 11 is the cut-open view of DD ' in Fig. 9;
The cut-open view of the display panel that Figure 12 embodiment five provides.
Embodiment
Core concept of the present invention is to provide a kind of tft array substrate, comprises pel array; Wherein each pixel cell comprises pixel electrode and comparative electrode, and pixel electrode is electrically connected to data line, and comparative electrode is electrically connected to concentric line by a TFT; N pixel cell shares a TFT, N >=2, that is to say that at least two pixel cells share a TFT, same concentric line charges to the comparative electrode in this N pixel cell by same TFT simultaneously, make like this in viewing area to greatly reduce as the quantity of the TFT of pixel switch, thereby improved aperture opening ratio.
Embodiment mono-
As shown in Figure 3, the electrical block diagram of this tft array substrate as shown in Figure 4 for the vertical view of the tft array substrate that the embodiment of the present invention one provides.From Fig. 3 and Fig. 4, can find out, this tft array substrate 10 comprises first substrate 100, is positioned at the pel array on first substrate 100.
This pel array comprises: many gate lines 101; Many the data lines 102 that intersect with 101 insulation of this many gate lines; Many concentric lines 103; And be formed at the pixel cell 110 (region of being enclosed by gate line 101 and data line 102 as shown in Figure 3, comprises 2 pixel cells 1101,1102) in gate line 101 and 102 regions of data line.Wherein, concentric line 103 conventionally and gate line 101 extend in the same direction, the two can parallel or almost parallel.
This pixel cell 110 comprises: pixel electrode 104, is electrically connected to data line 102; The comparative electrode 105 being oppositely arranged with pixel electrode 104; And TFT106, the grid 1061 of TFT106 is electrically connected to gate line 101, the source electrode of TFT106 (can be also drain electrode) 1062 is electrically connected to concentric line 103, and it is TFT106 semiconductor layer that the drain electrode of TFT106 (can be also source electrode) 1063 is electrically connected to comparative electrode 105,1064; Wherein, N pixel cell shares a TFT106, N >=2, and N is positive integer (take in Fig. 3 N=2 describes for example).
In addition, between pixel electrode 104 and comparative electrode 105, be also formed with memory capacitance 107, memory capacitance 107 consists of pixel electrode 104, comparative electrode 105 and the insulation course that is arranged between the two.When forming liquid crystal panel with this tft array substrate, between pixel electrode 104 and comparative electrode 105, be also formed with liquid crystal capacitance 108, liquid crystal capacitance 108 is by pixel electrode 104, comparative electrode 105 and be arranged at liquid crystal (not shown) formation between the two.In conjunction with the simple principle of work of setting forth the display panels that comprises this tft array substrate 10 of Fig. 4.When pixel cell charges, gate line 101 is applied in start signal the TFT106 as pixel switch in this pixel cell is opened, and the TFT106 that the common potential on concentric line 103 is opened by this is applied to the comparative electrode 105 in this pixel cell; Now data line 102 is applied in picture signal, and then this picture signal is applied to the pixel electrode 104 in pixel cell; The two ends of liquid crystal capacitance 108 are applied in respectively common potential and picture signal like this, then drive liquid crystal wherein to rotate; In addition, the two ends of memory capacitance 107 are also applied in respectively common potential and picture signal.When pixel cell keeps, gate line 101 is applied in shutdown signal the TFT106 as pixel switch in this pixel cell is closed, and the comparative electrode 105 in pixel cell is floated; Now data line 102 is applied in picture signal, and then this picture signal is applied to the pixel electrode 104 in pixel cell; But now, because comparative electrode 105 in this pixel cell is floated, the voltage difference of the voltage difference of liquid crystal capacitance 108 and memory capacitance 107 all remains unchanged.
In addition, it should be noted that, in Fig. 3 and Fig. 4, only with 2 pixel cells, share a TFT106, being that N=2 is that example describes, but can being that 3 pixel cells share a TFT106, can be also that 4 pixel cells share a TFT106, also can be that N pixel cell shares a TFT106, etc., at this, do not elaborate one by one.N pixel cell shares the implication of a TFT, and TFT controls the switch of this N pixel cell simultaneously, and in other words, when this TFT opens, the comparative electrodes of the pixel cell of all shared these TFT are charged simultaneously; When this TFT closes, all comparative electrodes that share the pixel cell of this TFT are floated simultaneously.In addition, N the shared TFT of pixel cell can comprise a grid, source/drain electrode, a N drain/source, and the comparative electrode of N pixel cell is corresponding N the drain/source that is electrically connected to this TFT one by one.Wherein the N of a TFT drain/source is separated from one another, connects each other in other words the N of TFT drain/source not conducting each other when TFT closes in other words by semiconductor layer.Conventionally the pixel electrode sharing in N the pixel cell of same TFT can not be electrically connected to same data line, the pixel electrode of N pixel cell respectively one by one correspondence be electrically connected to the different data line of N bar.
In the present embodiment, because N pixel cell shares a TFT, so the quantity of TFT reduced N-1, greatly improved aperture opening ratio.
From Fig. 3, can also further find out, N the pixel cell that shares a TFT can be positioned at same a line, and adjacent.Two the adjacent pixel cells in same a line of take below share TFT as example (as shown in Figure 3), further set forth the details of the present embodiment.In Fig. 3, as shown in Figure 5, the cut-open view of BB ' as shown in Figure 6 for the cut-open view of AA '.
From Fig. 3, further can find out, the first pixel cell 1101 and the second pixel cell 1102 share same TFT, and the two is adjacent and be all positioned at the region that adjacent two gate lines 1011,1012 and adjacent two data lines 1021,1022 surround.Between the first pixel cell 1101 and the second pixel cell 1102, there is no data line, the two shared TFT106 is arranged between the two near gate line 101 places.
The first pixel cell 1101 comprises: the first pixel electrode 1041, is electrically connected to the first data line 1021; The first comparative electrode 1051 being oppositely arranged with the first pixel electrode 1041.The second pixel cell 1102 comprises: the second pixel electrode 1042, is electrically connected to the second data line 1022; The second comparative electrode 1052 being oppositely arranged with the second pixel electrode 1042.The first pixel cell 1101 and the shared TFT106 of the second pixel cell 1102 comprise grid 1061, source electrode 1062(can be also drain electrode), first drain electrode 1063A(can be also source electrode), second drain electrode 1063B(can be also source electrode), semiconductor layer 1064; Grid 1061 is positioned at same layer and links into an integrated entity with gate line 101; Source electrode 1062 is positioned at same layer and links into an integrated entity with concentric line 103; The first drain electrode 1063A, the second drain electrode 1063B and source electrode 1062 are positioned at same layer but are separated from one another; The first drain electrode 1063 is electrically connected to the first comparative electrode 1051; The second drain electrode 1064 is electrically connected to the second comparative electrode 1052; The first pixel electrode 1041 is electrically connected to the first data line 1021; The second pixel electrode 1042 is electrically connected to the second data line 1022.
In conjunction with Fig. 3, Fig. 5 and Fig. 6, can find out, in layer structure, this tft array substrate 10 comprises first substrate 100 and is positioned at the pel array on first substrate 100.This pel array comprises that the gate line 101(being positioned at successively on first substrate 100 comprises first grid polar curve 1011, second gate line 1012) and the grid 1061 of TFT, gate insulator 111, the semiconductor layer 1064 of TFT, the source electrode 1062 of TFT, the first drain electrode 1063A, the second drain electrode 1063B and concentric line 103, comparative electrode 105(comprises the first comparative electrode 1051, the second comparative electrode 1052), passivation layer 112; Pixel electrode 104(comprises the first pixel electrode 1041, the second pixel electrode 1042); Data line 102(comprises the first data line 1021, the second data line 1022).
In addition, in embodiment mono-, pixel electrode 104 is positioned at different layers with comparative electrode 105, and pixel electrode 104 is strip, and comparative electrode 105 is sheet.As a kind of optional mode of texturing, pixel electrode 104 is positioned at different layers with comparative electrode 105, and pixel electrode 104 is sheet, and comparative electrode 105 is strip; As long as pixel electrode 104 is positioned at different layers with comparative electrode 105, and one of them be strip, another is sheet.Certainly, can be also that pixel electrode 104 is positioned at different layers with comparative electrode 105, and be strip alternative arrangement.
Embodiment bis-
As shown in Figure 7, the electrical block diagram of this tft array substrate as shown in Figure 8 for the vertical view of the tft array substrate that the embodiment of the present invention two provides.Embodiment bis-is the further optimization on the basis of embodiment mono-, and the part identical with embodiment mono-no longer repeats, and emphasis is narrated different parts.
From Fig. 7 and Fig. 8, can find out, in same row, the source/drain of the TFT of two adjacent pixel cells is electrically connected to same concentric line, grid is electrically connected to different gate lines; In other words, in same row, two of adjacent lines pixel cells can share same concentric line, and the quantity of the concentric line of whole like this tft array substrate just can reduce by half, and has reduced the occupied area of concentric line, and aperture opening ratio is further provided.
Specifically, in the first row, the first pixel cell 1101 is adjacent with the second pixel cell 1102, and the two shares a TFT1091, and the concrete syndeton between the first pixel cell 1101 and the second pixel cell 1102 and a TFT1091 can be with reference to Fig. 3, Fig. 5 and Fig. 6.The 3rd pixel cell 1103 and the 4th pixel cell 1104 in the second row, and the two shared the 2nd TFT1092, the concrete syndeton between the 3rd pixel cell 1103 and the 4th pixel cell 1104 and the 2nd TFT1092 also can be with reference to Fig. 3, Fig. 5 and Fig. 6.The source/drain of the source/drain of the one TFT1091, the 2nd TFT1092 is all connected to the concentric line 103 being arranged between the first row and the second row.It is emphasized that, the grid of the one TFT1091, it is insulated from each other that the grid of the 2nd TFT1092 is connected to respectively first grid polar curve 1011 and second gate line 1012(first grid polar curve 1011 and second gate line 1012), the adjacent pixel unit that is positioned at so same row is all electrically connected to same data line, and (the first pixel cell 1101 and the 3rd pixel cell 1103 are all electrically connected to same data line 1021, the second pixel cell 1102 and the 4th pixel cell 1104 are all electrically connected to same data line 1022), but due to a TFT1091, the 2nd TFT1092 is controlled by different gate lines respectively, the first pixel cell 1101 and the second pixel cell 1102 can not be applied in picture signal simultaneously.In like manner, the 3rd pixel cell 1103 and the 4th pixel cell 1104 can not be applied in picture signal simultaneously yet.
Embodiment tri-
In embodiment mono-, take pixel electrode and comparative electrode is positioned at different layers as example describes, and has provided layer structure as shown in Figure 5 and Figure 6.But in other embodiment of the present invention, when pixel electrode and comparative electrode are positioned at different layers, its layer structure can have multiple different distortion.For example, comparative electrode, gate line, concentric line are positioned at same layer, and described pixel electrode, data line bit are in same layer.
The electrical block diagram of the tft array substrate that the embodiment of the present invention three provides can be with reference to shown in figure 4, and the part that its circuit structure is identical with embodiment mono-no longer too much repeats.It is example (as shown in Figure 9) that two the adjacent pixel cells of take in same a line share TFT, and in Fig. 9, as shown in figure 10, the cut-open view of DD ' as shown in figure 11 for the cut-open view of CC '.Particularly, this tft array substrate comprise first substrate 100 and be positioned on first substrate 100 pel array.
This pel array comprises: many gate line 101(comprise first grid polar curve 1011, second gate line 1012); Many data line 102(that intersect with these many gate lines 101 insulation comprise the first data line 1021, the second data line 1022); Many concentric lines 103; And the pixel cell 110(being formed in gate line 101 and 102 regions of data line comprises the first pixel cell 1101, the second pixel cell 1102).Wherein, concentric line 103 conventionally and gate line 101 extend in the same direction, the two can parallel or almost parallel.
This pixel cell 110 comprises: pixel electrode 104(comprises the first pixel electrode 1041, the second pixel electrode 1042), be electrically connected to data line 102; The comparative electrode 105(being oppositely arranged with pixel electrode 104 comprises the first comparative electrode 1051, the second comparative electrode 1052); And TFT106, the grid 1061 of TFT106 is electrically connected to gate line 101, the source/drain 1062 of TFT106 is electrically connected to concentric line 103, and the drain/source 1063(of TFT106 comprises the first drain electrode 1063A, the second drain electrode 1063B) be electrically connected to comparative electrode 105; Wherein, N pixel cell shares a TFT106, N >=2, and N is positive integer (take in Fig. 9 N=2 describes for example).
In the present embodiment, pixel electrode 104 and comparative electrode 105 and the insulation course being arranged between the two form memory capacitance 107.When forming liquid crystal panel with this tft array substrate, between pixel electrode 104 and comparative electrode 105, be also formed with liquid crystal capacitance 108, liquid crystal capacitance 108 is by pixel electrode 104, comparative electrode 105 and be arranged at liquid crystal (not shown) formation between the two.The principle of work of the display panels that embodiment tri-provides is identical with embodiment mono-, at this, no longer repeats to set forth.
From Fig. 9, further can find out, the first pixel cell 1101 and the second pixel cell 1102 share same TFT, and the two is adjacent and be all positioned at the region that adjacent two gate lines 1011,1012 and adjacent two data lines 1021,1022 surround.Between the first pixel cell 1101 and the second pixel cell 1102, there is no data line, the two shared TFT is arranged between the two near gate line 101 places.
The first pixel cell 1101 comprises the first pixel electrode 1041, is electrically connected to the first data line 1021; The first comparative electrode 1051 being oppositely arranged with the first pixel electrode 1041; The second pixel cell 1102 comprises the second pixel electrode 1042, is electrically connected to the second data line 1022; The second comparative electrode 1052 being oppositely arranged with the second pixel electrode 1042.The first pixel cell 1101 and the shared TFT106 of the second pixel cell 1102 comprise grid 1061, source electrode 1062(can be also drain electrode), first drain electrode 1063A(can be also source electrode), second drain electrode 1063B(can be also source electrode); Grid 1061 is positioned at same layer and links into an integrated entity with gate line 101; Source electrode 1061 is positioned at same layer and links into an integrated entity with concentric line 103; The first drain electrode 1063A, the second drain electrode 1063B and source electrode 1062 are positioned at same layer but are separated from one another; The first drain electrode 1063 is electrically connected to the first comparative electrode 1051; The second drain electrode 1064 is electrically connected to the second comparative electrode 1055; The first pixel electrode 1041 is electrically connected to the first data line 1021; The second pixel electrode 1042 is electrically connected to the second data line 1022.
In addition, from Fig. 9, Figure 10 and Figure 11, can find out, in layer structure, the tft array substrate 10 that embodiment tri-provides comprises first substrate 100 and is positioned at the pel array on first substrate 100.This pel array comprises the ground floor being positioned at successively on first substrate 100: comparative electrode 105(comprises the first comparative electrode 1051, the second comparative electrode 1052), gate line 101(comprises first grid polar curve 1011, second gate line 1012), the grid 1061 of TFT, concentric line 103, four are positioned at same layer, adopt same material; The second layer: gate insulator 111; The 3rd layer: the semiconductor layer 1064 of TFT; The 4th layer: the source electrode of TFT 1062, the first drain electrode 1063A, the second drain electrode 1063B, data line 102(comprise the first data line 1021, the second data line 1022) and pixel electrode 104(comprise the first pixel electrode 1041, the second pixel electrode 1042); Layer 5: passivation layer 112.Concentric line 103 is electrically connected to by running through the first via hole H1 of gate insulator 111 with the source electrode 1062 of TFT; The first drain electrode 1063A is electrically connected to by running through the second via hole H2 of gate insulator 111 with the first comparative electrode 1051; The second drain electrode 1063B is electrically connected to by running through the 3rd via hole H3 of gate insulator 111 with the second comparative electrode 1052; The first data line 1021 is directly being electrically connected to layer with the first pixel electrode 1041; The second data line 1022 is directly being electrically connected to layer with the second pixel electrode 1042.
Certainly, for comparative electrode and pixel electrode, be positioned at the tft array substrate of different layers, can also have multiple other structures.
For example, the grid of gate line, TFT is positioned at ground floor, and the source electrode of TFT and drain electrode, concentric line and comparative electrode are formed at the second layer on described ground floor;
Or the grid of gate line, TFT is positioned at ground floor, the source electrode of TFT and drain electrode, concentric line are formed at the second layer on described ground floor, and comparative electrode is formed at the 3rd layer on the described second layer;
Or the grid of gate line, TFT is positioned at ground floor, comparative electrode is formed at the second layer on described ground floor, and the source electrode of TFT and drain electrode, concentric line are formed at the 3rd layer on the described second layer.
For aforementioned any mode, all can continue in the following way: data line, pixel electrode are formed at the 4th layer on the source electrode of TFT and drain electrode, concentric line and comparative electrode;
Or data line is formed at the 4th layer on the source electrode of TFT and drain electrode, concentric line and comparative electrode, and pixel electrode is formed at the layer 5 on the 4th layer;
Or pixel electrode is formed at the 4th layer on the source electrode of TFT and drain electrode, concentric line and comparative electrode, and data line is formed at the layer 5 on the 4th layer.
Between above-mentioned each layer, other layers can be set, as insulation course; Other layers also can be set.According to practical structures and technique, adjust, at this, exceed elaboration.
Embodiment tetra-
In embodiment mono-, two, three, take pixel electrode and comparative electrode is positioned at different layers and describes as example, but other embodiment of the present invention can also adopt pixel electrode and comparative electrode to be positioned at same layer, and is strip, and the structure of alternative arrangement.For example: the grid of gate line and concentric line, TFT is positioned at ground floor; The source electrode of data line, TFT, the drain electrode of TFT are formed at the second layer on ground floor, and comparative electrode is formed at the 3rd layer on the second layer, and are electrically connected to the drain/source of TFT; Pixel electrode is formed in the 3rd layer, and is electrically connected to data line.
Embodiment five
The embodiment of the present invention five provides a kind of display panel, as Figure 12 shows.This display panel comprises above-described embodiment one～five tft array substrate 10 described in any; The color membrane substrates 20 being oppositely arranged with this tft array substrate, and be arranged at the liquid crystal layer 30 between tft array substrate 10 and color membrane substrates 20.
Embodiment six
The embodiment of the present invention six provides a kind of display device, comprises the display panel described in embodiment five; Further display device also comprises for the backlight module of light source is provided to this display panel.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (12)
1. a tft array substrate, comprises first substrate, and is positioned at the pel array on described first substrate;
Described pel array comprises:
Many gate lines;
Many data lines that intersect with described many gate lines insulation;
Many concentric lines;
Be formed at the pixel cell in described gate line and data line institute region, comprise: pixel electrode, is electrically connected to described data line; The comparative electrode being oppositely arranged with described pixel electrode; And TFT, the grid of described TFT is electrically connected to described gate line, and the source/drain of described TFT is electrically connected to described concentric line, and the drain/source of described TFT is electrically connected to described comparative electrode; Wherein, N pixel cell shares a TFT, N >=2.
2. tft array substrate according to claim 1, it is characterized in that, the shared TFT of a described N pixel cell comprises a grid, source/drain electrode, a N drain/source, and the comparative electrode of a described N pixel cell one by one correspondence is electrically connected to a described N drain/source.
3. tft array substrate according to claim 2, is characterized in that, the pixel electrode of a described N pixel cell is electrically connected to respectively the different data line of N bar.
4. tft array substrate according to claim 1, is characterized in that, described N the pixel cell that shares a TFT is positioned at same a line, and adjacent.
5. tft array substrate according to claim 1, is characterized in that, in same row, the source/drain of the TFT of two adjacent pixel cells is electrically connected to same concentric line, grid is electrically connected to different gate lines.
6. tft array substrate according to claim 1, is characterized in that, described pixel electrode and described comparative electrode are positioned at same layer, and is strip alternative arrangement; Or
Described pixel electrode and described comparative electrode are positioned at different layers, and are strip alternative arrangement; Or described pixel electrode and described comparative electrode are positioned at different layers, and one of them be strip, another is sheet.
7. tft array substrate according to claim 1, is characterized in that, described comparative electrode, gate line, concentric line are positioned at same layer, and described pixel electrode, data line bit are in same layer.
8. tft array substrate according to claim 1, is characterized in that, described gate line and described concentric line are positioned at ground floor; Described data line is formed at the second layer on described ground floor, and described comparative electrode is formed at the 3rd layer on the described second layer, and is electrically connected to the drain/source of described TFT; Described pixel electrode is formed in the 3rd layer, and is electrically connected to described data line.
9. tft array substrate according to claim 1, is characterized in that, the grid of described gate line, TFT is positioned at ground floor, and the source electrode of described TFT and drain electrode, concentric line and comparative electrode are formed at the second layer on described ground floor;
Or the grid of described gate line, TFT is positioned at ground floor, the source electrode of described TFT and drain electrode, concentric line are formed at the second layer on described ground floor, and described comparative electrode is formed at the 3rd layer on the described second layer; Or the grid of described gate line, TFT is positioned at ground floor, described comparative electrode is formed at the second layer on described ground floor, and the source electrode of described TFT and drain electrode, concentric line are formed at the 3rd layer on the described second layer.
10. tft array substrate according to claim 9, is characterized in that, described data line, pixel electrode are formed at the 4th layer on the source electrode of described TFT and drain electrode, concentric line and comparative electrode;
Or described data line is formed at the 4th layer on the source electrode of described TFT and drain electrode, concentric line and comparative electrode, and described pixel electrode is formed at the layer 5 on described the 4th layer;
Or described pixel electrode is formed at the 4th layer on the source electrode of described TFT and drain electrode, concentric line and comparative electrode, and described data line is formed at the layer 5 on described the 4th layer.
11. 1 kinds of display panels, comprise the tft array substrate as described in claim 1-10 any one; The color membrane substrates being oppositely arranged with described tft array substrate, and be arranged at the liquid crystal layer between described tft array substrate and described color membrane substrates.
12. 1 kinds of display device, comprise that profit requires the display panel described in 11.
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| CN104900207A (en) * | 2015-06-24 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, drive method thereof and display device |
| CN105158994A (en) * | 2015-09-30 | 2015-12-16 | 武汉华星光电技术有限公司 | Pixel unit and array substrate |
| CN106297668A (en) * | 2016-11-02 | 2017-01-04 | 京东方科技集团股份有限公司 | A kind of OLED driver circuit, array base palte and display device |
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| WO2017054329A1 (en) * | 2015-09-30 | 2017-04-06 | 武汉华星光电技术有限公司 | Pixel unit and array substrate |
| CN105158994B (en) * | 2015-09-30 | 2018-03-06 | 武汉华星光电技术有限公司 | Pixel cell and array base palte |
| CN106297668A (en) * | 2016-11-02 | 2017-01-04 | 京东方科技集团股份有限公司 | A kind of OLED driver circuit, array base palte and display device |
| US10607545B2 (en) | 2016-11-02 | 2020-03-31 | Boe Technology Group Co., Ltd. | Organic light-emitting diode driving circuit with sense thin film transistors sharing gate electrode and source electrode, array substrate and display device |
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