CN103929890A - Method for manufacturing inner layer circuit of circuit board - Google Patents
Method for manufacturing inner layer circuit of circuit board Download PDFInfo
- Publication number
- CN103929890A CN103929890A CN201310753292.1A CN201310753292A CN103929890A CN 103929890 A CN103929890 A CN 103929890A CN 201310753292 A CN201310753292 A CN 201310753292A CN 103929890 A CN103929890 A CN 103929890A
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- CN
- China
- Prior art keywords
- substrate
- copper
- circuit
- photoresist
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052802 copper Inorganic materials 0.000 claims abstract description 48
- 239000010949 copper Substances 0.000 claims abstract description 48
- 239000011347 resin Substances 0.000 claims abstract description 34
- 229920005989 resin Polymers 0.000 claims abstract description 34
- 238000007747 plating Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000011889 copper foil Substances 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 239000000126 substance Substances 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims abstract description 14
- 238000005553 drilling Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 230000004913 activation Effects 0.000 claims description 12
- 238000004140 cleaning Methods 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 6
- 230000009467 reduction Effects 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract description 8
- 238000009713 electroplating Methods 0.000 abstract description 5
- 229910052763 palladium Inorganic materials 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000003292 glue Substances 0.000 abstract 2
- 101001134276 Homo sapiens S-methyl-5'-thioadenosine phosphorylase Proteins 0.000 description 5
- 102100022050 Protein canopy homolog 2 Human genes 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 102000004528 Mannose-Binding Protein-Associated Serine Proteases Human genes 0.000 description 1
- 108010042484 Mannose-Binding Protein-Associated Serine Proteases Proteins 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 210000003205 muscle Anatomy 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention discloses a method for manufacturing an inner layer circuit of a circuit board, which comprises the following steps: mechanically drilling a hole on the substrate to form a through hole for double-sided interconnection; carrying out glue residue removal treatment on the substrate after mechanical drilling; removing copper foils on two sides of the substrate; carrying out chemical copper plating on the surface of the resin core plate to form a chemical copper plating layer on the surface of the resin core plate; manufacturing an electroplating mask on the surface of the resin core plate through photoetching, so that the region masked by the photoresist is not electroplated; electroplating copper on the area not masked by the photoresist; removing the photoresist used for the electroplating mask to expose the surface of the whole electroplated substrate; and corroding the chemical copper plating layer masked by the photoresist to form the inner layer circuit board. In the chemical copper plating process, the surface of the resin core plate is only fluffed without being subjected to the treatment of removing the glue residues, and the fluffed resin surface has larger specific surface area and can be combined with more palladium metal, so that the binding force of the chemical copper plating layer is improved.
Description
Technical field
The present invention relates to printed substrate manufacturing technology field, relate in particular to a kind of manufacture method of circuit board internal layer circuit.
Background technology
Along with the development of large scale integrated circuit, circuit is more and more thinner, and 22nm technology has entered volume production, and the refinement of circuit causes having proposed unprecedented challenge for equipment and process.For improving chip density and the signal handling capacity in unit are, 3D encapsulation is arisen at the historic moment, and people propose the concept of three-dimension packaging, chip is carried out to three-dimensional integration packaging, will chip is carried out stacking, form three-dimension packaging, to improve the packaging density in unit are.
In the time that the live width line-spacing of encapsulating carrier plate is greater than 50um, encapsulating carrier plate generally adopts subtractive process to make.When live width line-spacing is less than 50um, there are two kinds of ways, a kind of is to adopt half additive process SAP to manufacture the circuit below 50um, one is to adopt MSAP technique, manufactures 25um-50um or wider circuit.
MSAP itself is thinned to 1-2um at central layer surface Copper Foil, and then photoetching forms plating mask figure, after graphic plating, photoresist is removed, then the extra thin copper foil of photoresist bottom is eroded.Because extra thin copper foil is that the thin material of cathode copper own is than the electro-coppering dense materials of graphic plating, corrosion rate differs greatly, in the process that low copper corrosion is fallen, owing to being justifying corrosion, the copper of whole substrate surface all can be corroded, so, the copper of electroplating also can be corroded, therefore, the mask pattern design of graphic plating, electroplating parameter, extra thin copper foil thickness, the parameter of dodging the ultra-thin copper of erosion will have a strong impact on last circuit precision, therefore, the effectively adhesion of control circuit and insulating barrier of MSAP technique.For the less circuit of live width, sudden strain of a muscle erosion is larger for the etch quantity of electro-coppering, will have a strong impact on dimensional accuracy, and MASP cannot process the circuit that live width is less than 25un conventionally.
For SAP because there is no the extra thin copper foil of bottom, only has the chemical plating copper layer that one deck is very thin, the etch-rate of chemical plating copper layer is far longer than the etch-rate of the surperficial electrolytic copper foil of electro-coppering and double face copper, from high accuracy control circuit size, SAP technique has unmatched dimension of picture precision control ability.But existing SAP method is made internal layer circuit, and the problem of existence is that circuit adhesion is poor, cannot meet the technical requirement of circuit board processing and manufacturing.
In sum, internal layer circuit live width is less than 50um circuit, need to realize by MSAP or SAP method, and MSAP method can only be accomplished 25um live width, less live width, cannot meet the control requirement of Line-width precision.SAP method can be accomplished less live width, still, current SAP method, in the surperficial SAP technique of central layer (core) layer, the metallic circuit figure adhesion obtaining is very little, cannot meet actual track needs.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of manufacture method of circuit board internal layer circuit, can realize the manufacture that live width is less than the fine-line of 50um, and circuit adhesion meets the technical requirement of circuit board processing and manufacturing.
In order to achieve the above object, the technical scheme that the embodiment of the present invention adopts is as follows:
A manufacture method for circuit board internal layer circuit, comprises the steps:
On substrate, carry out machine drilling, form the through hole of two-sided interconnection use;
Described substrate after machine drilling is carried out to de-smear processing;
Copper Foil two-sided described substrate is removed;
Electroless copper is carried out on surface at described resin central layer, makes described resin central layer surface form chemical plating copper layer, and the process of described electroless copper is: fluffy → acidleach → clean → microetch → preimpregnation → activation → reduction → electroless copper;
By photoetching making plating mask, the region of being lived by photoresist masking is not electroplated on described resin central layer surface;
Not by the region electro-coppering of described photoresist masking;
Described photoresist for plating mask is removed, the substrate surface of whole plating is come out;
To be eroded by the chemical plating copper layer of photoresist masking, form internal layer circuit plate.
Further, carry out, before electroless copper, also comprising on the surface of described resin central layer: described resin central layer is carried out to plasma cleaning activation.
Further, the thickness of described electro-coppering is more than 15um.
Compared with prior art, the invention has the beneficial effects as follows:
The present invention, in the technique of electroless copper, only carries out fluffy processing to resin central layer surface, and without de-smear processing, the resin surface after fluffy has larger specific area, can be in conjunction with more palladium metal, thus improve the adhesion of chemical plating copper layer.Meanwhile, the present invention carries out plasma cleaning activation to resin central layer before electroless copper, also further improves the adhesion of chemical plating copper layer.
Brief description of the drawings
The process chart of the manufacture method of a kind of circuit board internal layer circuit that Fig. 1 provides for the embodiment of the present invention;
The step schematic diagram of the manufacture method of a kind of circuit board internal layer circuit that Fig. 2-Fig. 9 provides for the embodiment of the present invention.
Embodiment
In order better to understand technique scheme, below in conjunction with Figure of description and concrete execution mode, technique scheme is described in detail.
As shown in Figure 1, the embodiment of the present invention provides a kind of manufacture method of circuit board internal layer circuit, comprises the steps:
Step 110: carry out machine drilling on substrate, form the through hole of two-sided interconnection use;
Particularly, as shown in Figure 2, described substrate is double face copper, comprises resin central layer 1 and the Copper Foil 2 that is coated on resin central layer 1 two sides; Substrate forms the through hole of two-sided interconnection use after machine drilling, as shown in Fig. 3.
Step 120: the described substrate after machine drilling is carried out to de-smear processing;
Particularly, the residue of the resin producing in machine drilling process on described substrate and glass is removed; Because the surface of resin central layer 1 is protected by Copper Foil 2, in the process of de-smear, be not corroded.
Step 130: Copper Foil two-sided described substrate 2 is removed;
Particularly, as shown in Figure 4, Copper Foil two-sided described substrate 2 is etched away, make described substrate resin central layer 1 surface exposure out.
Step 140: electroless copper is carried out on the surface at described resin central layer 1, makes described resin central layer 1 surface form chemical plating copper layer 3, and the process of described electroless copper is: fluffy → acidleach → clean → microetch → preimpregnation → activation → reduction → electroless copper;
Particularly, as shown in Figure 5, carry out electroless copper on the whole plate of substrate surface, make resin central layer 1 surface uniform parcel layer of copper, form chemical plating copper layer 3; In the present embodiment, the process of electroless copper is: fluffy → acidleach → clean → microetch → preimpregnation → activation → reduction → electroless copper, compared with existing chemical-copper-plating process, do after fluffy processing, do not do de-smear processing, there is larger specific area on resin chip 1 surface after fluffy, can be in conjunction with more palladium metal.Improve the adhesion of electroless copper.
Step 150: by photoetching making plating mask, the region of being sheltered by photoresist 4 is not electroplated, as shown in Figure 6 on described resin central layer 1 surface;
Step 160: the region electro-coppering of not sheltered by photoresist 4;
Particularly, as shown in Figure 7, thicken the thickness of chemical plating copper layer metallic copper by plating, more than general electro-coppering 5 thickness 15um.
Step 170: the photoresist for plating mask 4 is removed, the substrate surface of whole plating is come out, as shown in Figure 8;
Step 180: the chemical plating copper layer of being sheltered by photoresist 4 is eroded, form internal layer circuit plate, as shown in Figure 9.
Further, before step 140, also comprise step: described resin central layer 1 is carried out to plasma cleaning activation.The effect of plasma cleaning activation is as follows: after (1) activation, fluffy solution resin material easier and substrate surface works; (2) increase base plate resin surface hydrophilicity, make the each step solution of follow-up electroless copper more easily enter the cavity of resin, improve electroless copper surface uniformity; (3) clean surface, removes surperficial organic contaminations, improves the adhesion of chemical plating copper layer.
The surface roughness that the present invention manufactures circuit to be needed comes from the Copper Foil of substrate surface.Need low roughness owing to manufacturing fine rule road, therefore need the Copper Foil of double face copper to adopt the Copper Foil of low roughness.The roughness of Copper Foil requires the linewidth requirements on the fine rule road of processing as required to select, and thinner circuit just needs lower Copper Foil roughness.
The embodiment of the present invention utilizes plasma cleaning to remove surperficial pollutant, activating surface, raising resin surface wettability, fluffy, neutralization, activating reagent can be contacted with solution better, make fluffy after, the larger specific area that resin forms, improve uniformity and the adhesion of the distribution of activation effect and activation palladium, thereby improve the adhesion of electroless copper.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (3)
1. a manufacture method for circuit board internal layer circuit, is characterized in that, comprises the steps:
On substrate, carry out machine drilling, form the through hole of two-sided interconnection use;
Described substrate after machine drilling is carried out to de-smear processing;
Copper Foil two-sided described substrate is removed;
Electroless copper is carried out on surface at described resin central layer, makes described resin central layer surface form chemical plating copper layer, and the process of described electroless copper is: fluffy → acidleach → clean → microetch → preimpregnation → activation → reduction → electroless copper;
By photoetching making plating mask, the region of being lived by photoresist masking is not electroplated on described resin central layer surface;
Not by the region electro-coppering of described photoresist masking;
Described photoresist for plating mask is removed, the substrate surface of whole plating is come out;
To be eroded by the chemical plating copper layer of photoresist masking, form internal layer circuit plate.
2. the manufacture method of circuit board internal layer circuit as claimed in claim 1, is characterized in that, carries out, before electroless copper, also comprising: described resin central layer is carried out to plasma cleaning activation on the surface of described resin central layer.
3. the manufacture method of circuit board internal layer circuit as claimed in claim 1, is characterized in that, the thickness of described electro-coppering is more than 15um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310753292.1A CN103929890B (en) | 2013-12-31 | 2013-12-31 | Method for manufacturing inner layer circuit of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310753292.1A CN103929890B (en) | 2013-12-31 | 2013-12-31 | Method for manufacturing inner layer circuit of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103929890A true CN103929890A (en) | 2014-07-16 |
| CN103929890B CN103929890B (en) | 2017-08-29 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310753292.1A Active CN103929890B (en) | 2013-12-31 | 2013-12-31 | Method for manufacturing inner layer circuit of circuit board |
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| Country | Link |
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| CN (1) | CN103929890B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104821371A (en) * | 2015-04-23 | 2015-08-05 | 曹先贵 | Manufacturing method of LED integrated package substrate |
| CN105722339A (en) * | 2016-02-29 | 2016-06-29 | 江西合力泰科技有限公司 | Metal ring mounting method for biological recognition module |
| CN107041078A (en) * | 2017-05-27 | 2017-08-11 | 华进半导体封装先导技术研发中心有限公司 | The manufacture method of high density flexible substrate |
| CN111276443A (en) * | 2020-02-10 | 2020-06-12 | 中国电子科技集团公司第十三研究所 | Preparation method of microwave thin film hybrid integrated circuit |
| CN112654132A (en) * | 2017-08-18 | 2021-04-13 | 景硕科技股份有限公司 | Multilayer circuit board capable of performing electrical test |
| CN112752447A (en) * | 2020-12-25 | 2021-05-04 | 惠州市大亚湾科翔科技电路板有限公司 | Manufacturing process of circuit board with embedded components |
| CN112911835A (en) * | 2020-12-30 | 2021-06-04 | 恩达电路(深圳)有限公司 | Production method of multilayer mixed-pressing stepped back-pressing metal-based high-frequency circuit board |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104821371A (en) * | 2015-04-23 | 2015-08-05 | 曹先贵 | Manufacturing method of LED integrated package substrate |
| CN105722339A (en) * | 2016-02-29 | 2016-06-29 | 江西合力泰科技有限公司 | Metal ring mounting method for biological recognition module |
| CN107041078A (en) * | 2017-05-27 | 2017-08-11 | 华进半导体封装先导技术研发中心有限公司 | The manufacture method of high density flexible substrate |
| CN107041078B (en) * | 2017-05-27 | 2019-04-19 | 华进半导体封装先导技术研发中心有限公司 | The manufacturing method of high density flexible substrate |
| CN112654132A (en) * | 2017-08-18 | 2021-04-13 | 景硕科技股份有限公司 | Multilayer circuit board capable of performing electrical test |
| CN112654132B (en) * | 2017-08-18 | 2022-01-14 | 景硕科技股份有限公司 | Multilayer circuit board capable of performing electrical test |
| CN111276443A (en) * | 2020-02-10 | 2020-06-12 | 中国电子科技集团公司第十三研究所 | Preparation method of microwave thin film hybrid integrated circuit |
| CN111276443B (en) * | 2020-02-10 | 2023-03-14 | 中国电子科技集团公司第十三研究所 | Preparation method of microwave thin film hybrid integrated circuit |
| CN112752447A (en) * | 2020-12-25 | 2021-05-04 | 惠州市大亚湾科翔科技电路板有限公司 | Manufacturing process of circuit board with embedded components |
| CN112752447B (en) * | 2020-12-25 | 2022-05-17 | 惠州市大亚湾科翔科技电路板有限公司 | Manufacturing process of circuit board with embedded components |
| CN112911835A (en) * | 2020-12-30 | 2021-06-04 | 恩达电路(深圳)有限公司 | Production method of multilayer mixed-pressing stepped back-pressing metal-based high-frequency circuit board |
| CN112911835B (en) * | 2020-12-30 | 2023-03-10 | 恩达电路(深圳)有限公司 | Production method of multilayer mixed-pressing stepped back-pressing metal-based high-frequency circuit board |
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| CN103929890B (en) | 2017-08-29 |
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Effective date of registration: 20190430 Address after: 214135 China Sensor Network International Innovation Park D1, 200 Linghu Avenue, Wuxi New District, Jiangsu Province Patentee after: National Center for Advanced Packaging Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Co-patentee before: National Center for Advanced Packaging Co.,Ltd. Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
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