CN103926764B - A kind of tft array substrate and display panel, display device - Google Patents
A kind of tft array substrate and display panel, display device Download PDFInfo
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- CN103926764B CN103926764B CN201310081939.0A CN201310081939A CN103926764B CN 103926764 B CN103926764 B CN 103926764B CN 201310081939 A CN201310081939 A CN 201310081939A CN 103926764 B CN103926764 B CN 103926764B
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Abstract
The invention discloses a kind of double grid line style（Dual Gate Line）Tft array substrate and include double grid line style tft array substrate display panel, the display device.The double grid line style tft array substrate uses plurality of transmission lines, and each transmission line is arranged between adjacent two pixel column；Also, each transmission line is arranged between the adjacent data wire.Plurality of transmission lines is corresponding with a plurality of grid line to be electrically connected.The design of transmission line so can reduce the panel border area shared by peripheral wiring, improve typesetting rate.
Description
Technical field
The present invention relates to active array（Active Matrix Array）Field, more particularly to a kind of double grid line style（Dual
Gate Line）TFT（Thin Film Transistor）Array base palte and include the double grid line style tft array substrate display surface
Plate, display device.
Background technology
TFT-LCD（Thin Film Transistor-Liquid Crystal Display, tft liquid crystal shows
Device）It is the orientation for changing liquid crystal molecule using the change for being clipped in electric-field intensity on liquid crystal layer, so as to control the power of printing opacity to show
Diagram as.In general, one piece of complete liquid crystal display panel must have backlight module, polaroid, tft array substrate and
Color film（CF, Color Filter）The layer of liquid crystal molecule filled in substrate and the box being made up of their two pieces of substrates is constituted.TFT
Have on array base palte voltage break-make and size on substantial amounts of pixel electrode, pixel electrode by be connected with horizontal grid line grid,
The source signal control being connected with longitudinal data line.The pixel electrode on public electrode and tft array substrate on CF upper substrates
Between electric-field intensity change control the orientation of liquid crystal molecule.It is parallel with grid line and in same layer on tft array substrate
Storage capacitance hearth electrode line（Vcom lines）The storage capacitance that can be formed between pixel electrode is used for maintaining next signal
The state of liquid crystal molecule before facing.
Prior art proposes a kind of double grid line style（Dual Gate Line）Tft array structure, as shown in Figure 1.In figure
The grid for the TFT being electrically connected to one-row pixels in two grid lines, such as the first row pixel PX is electrically connected to grid line G11, G12
On, wherein the grid positioned at the TFT of the pixel of odd column is electrically connected to the first grid line G11, positioned at the pixel PX of even column TFT
Grid be electrically connected to the second grid line G12；（In addition to first row and last row）Two adjacent pixel columns, are jointly electrically connected to same
One data line：Two adjacent pixel columns, the wherein TFT of all pixels source/drain is electrically connected to same data wire, for example
The TFT of second pixel column and the 3rd pixel column source/drain is jointly electrically connected to data wire D2, the like.So that
To reduce the quantity of data wire.
But because the quantity of the grid line cabling of outer peripheral areas adds one times, therefore the more areas of grid cabling needs enter
The double grid line style used in row typesetting so that frame becomes causes typesetting rate low greatly, such as CN201110104773（Dual Gate
Line）Tft array structure, although bring expected technique effect, but do not account for and brought because panel border becomes greatly
Harmful effect.This is especially apparent for the influence using same driving chip driving data line and the tft array substrate of grid line,
Typesetting rate declines more notable.In addition, at present in technology, by grid drive chip（Gate IC or Gate integrated
circuit）It is arranged on data driving chip（Source IC, Source integrated circuit）Adjacent side, such as
Shown in Fig. 1, Fig. 7.Although the quantity of the grid line cabling of outer peripheral areas does not increase, due to grid drive chip and data-driven
Chip is adjacent position relationship, and grid drive chip needs to occupy certain typesetting area in itself, made with data driving chip
Obtain frame to increase, also result in typesetting rate low.
The content of the invention
The invention aims to overcome in the prior art, cause because of the mode of grid cabling panel border become it is big and
The problem of harmful effect brought is present, and provide a kind of double grid line style tft array substrate and comprising TFT gusts of the double grid line style
Row substrate display panel, display device.The cabling mode for the grid line that the double grid line style tft array substrate is used can reduce outer
The frame area of area gate cabling or the array base palte occupied by driving chip is enclosed, the typesetting rate of frame region is improved.
According to the exemplary embodiment of the present invention there is provided a kind of tft array substrate, including,
One substrate；A plurality of grid line and a plurality of data lines that the insulation being arranged on the substrate intersects, the grid line is by row
Configuration, the data wire is configured by row；Pel array, each pixel is arranged at the infall of the grid line and the data wire,
Two grid lines are electrically connected to one-row pixels, two adjacent pixel columns are electrically connected to same data line；I.e.：With in one-row pixels
TFT grid be electrically connected on two grid lines, wherein the grid positioned at the pixel PX of odd column TFT is electrically connected to described two
A grid line in bar grid line（Referred to as the first grid line）, the grid positioned at the pixel PX of even column TFT is electrically connected to described two
Another grid line in bar grid line（Referred to as the second grid line）；Two adjacent pixel columns are electrically connected to same data line：Adjacent
Two pixel columns, the TFT of all pixels therein source/drain is electrically connected to same data wire.Wherein, the tft array base
Plate also includes, plurality of transmission lines, and each transmission line is arranged between adjacent two pixel column；
Also, each transmission line is arranged between the adjacent data wire.
Plurality of transmission lines electrical connection corresponding with the multi-strip scanning line, the i.e. quantity of transmission line cannot be less than scannings
The quantity of line, has two kinds of situations to be respectively：When the quantity of transmission line can be equal with the quantity of scan line, then transmission line is with scanning
Line corresponds electrical connection；When transmission line is more than the quantity of scan line, then each scan line all at least transmission lines and its
Electrical connection, but because the quantity of transmission line is more, can there are some transmission lines not electrically connected with any scan line.
Preferably, the size of described tft array substrate resolution ratio needs to meet resolution condition：M is picture
The columns of element, n is the line number of pixel, and m, n are positive integer.Its reason is that transmission line has foot in pixel region when meeting this condition
Enough positions must meet following condition：I.e.Pixel region just has enough spaces and sets transmission line.
Preferably, the tft array substrate also includes being located between the grid line and data wire, and the two is electrically insulated
The first insulating barrier；Through the first via of the insulating barrier.
Preferably, the transmission line is connected by first via with the grid line.
Preferably, described transmission line and data line bit are in same layer or different layers.
Preferably, the tft array substrate also includes data driving chip, grid drive chip, the raster data model core
Piece is electrically connected with the transmission line；The data driving chip is electrically connected with data wire；Described grid drive chip is arranged on
The offside of data driving chip.
Preferably, the tft array substrate also includes a driving chip, institute's driving chip and the data wire, the grid
Line is electrically connected.
Preferably, the tft array substrate also includes the grid line lead in peripherally located region, the grid line lead with it is described
Grid line is located at same layer；The transmission line is electrically connected by the grid line lead with the driving chip.
Preferably, the tft array substrate also includes being located at the second via through the insulating barrier, the grid line lead
It is connected with described transmission line by the second via, the grid line lead is directly to electrically connect with the driving chip, the number
It is directly to electrically connect according to line and the driving chip.
Present invention also offers a kind of display panel, including：Tft array substrate, the tft array substrate is described above
Tft array substrate.
The display panel can be liquid crystal display panel or Organic Light Emitting Diode（OLED）Display panel or plasma are aobvious
Show panel or Electronic Paper.
Present invention also offers a kind of display device, including, display panel；Described display panel is above-mentioned display surface
Plate.
Understand that compared with prior art, the invention discloses a kind of double grid line style via above-mentioned technical scheme（Dual
Gate Line）Tft array substrate and include double grid line style tft array substrate display panel, the display device.The double grid line style
Tft array substrate uses plurality of transmission lines, and each transmission line is arranged between adjacent two pixel column；Also, it is every
Transmission line described in one is arranged between the adjacent data wire.Plurality of transmission lines is corresponding with a plurality of grid line to be electrically connected.Such as
The design of this transmission line can reduce the panel border area shared by peripheral wiring, improve typesetting rate.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, makes required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of schematic diagram of disclosed double grid linear array board structure in the prior art；
Fig. 2 a are a kind of schematic diagram of double grid linear array board structure disclosed in the embodiment of the present invention one；
Fig. 2 b are a kind of schematic diagram of another structure of double grid linear array substrate disclosed in the embodiment of the present invention one；
Fig. 2 c are a kind of the first via profile of double grid linear array board structure disclosed in the embodiment of the present invention one；
Fig. 2 d are a kind of another first via section of double grid linear array board structure disclosed in the embodiment of the present invention one
Figure；
Fig. 3 is a kind of schematic diagram of double grid linear array board structure disclosed in the embodiment of the present invention two；
Fig. 4 a are a kind of schematic diagram of double grid linear array board structure disclosed in the embodiment of the present invention three；
Fig. 4 b are a kind of the second via profile of double grid linear array board structure disclosed in the embodiment of the present invention three；
Fig. 5 is a kind of schematic diagram of double grid linear array board structure disclosed in the embodiment of the present invention four；
Fig. 6 is a kind of schematic diagram of double grid linear array board structure disclosed in the embodiment of the present invention five；
Fig. 7 is disclosed another double grid line style (Dual Gate Line) tft array substrate structure in the prior art
Schematic diagram；
Fig. 8 is the schematic diagram for implementing a kind of double grid linear array board structure of the present invention in Fig. 7 structures.
10：Tft array substrate； 11：First insulating barrier；12：3rd insulating barrier；
13：ITO pixel electrodes 14：Second insulating barrier
D：Data wire D1-Dx:Data wire, x, n take positive integer
G：Grid line G11-Gm2:Grid line, wherein m are positive integer.
H：First via LH：Second via
L：Grid line lead L1-Lp：Grid line lead, wherein p >=m, m, p are positive integer.
T：Transmission line T1-Tp：Transmission line, wherein p >=m, m, p are positive integer.
T1-Tq：Transmission line, wherein q are positive integer.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Following examples of the present invention disclose a kind of double grid line style（Dual Gate Line）TFT（Thin Film
Transistor）Array base palte and include double grid line style tft array substrate display panel, the display device.Double grid line style TFT
Array base palte uses plurality of transmission lines, and each transmission line is arranged between adjacent two pixel column；And it is each
The transmission line is arranged between the adjacent data wire.Plurality of transmission lines is corresponding with a plurality of grid line to be electrically connected.So
The design of transmission line can reduce panel（Panel）Left and right side frame width.Concrete structure passes through following examples
It is described in detail.
In following examples, the size of tft array substrate resolution ratio is satisfied by resolution condition：M is pixel
Columns, n be pixel line number, m, n are positive integer.
Embodiment one
As shown in Figure 2 a, a kind of schematic diagram of double grid linear array board structure disclosed by the invention, mainly includes, substrate
10th, the pel array of multiple pixel PX compositions, TFT, the first via H, data driving chip（Source IC）, raster data model core
Piece（Gate IC）, grid line G11-Gm2, data wire D1-Dx and transmission line T1-Tp.
The a plurality of grid line G11-Gm2 that the insulation being arranged on the substrate intersects（Wherein m is positive integer）With many datas
Line D1-Dx（WhereinX, n take positive integer, the i.e. x to be（n+1）The integer part of/2 acquired results）, the grid line
G11-Gm2 is configured by row, parallel to each other；The data wire D1-Dx is configured by row, parallel to each other；Grid line G11-Gm2 and data wire
D1-Dx is insulated from each other to intersect, generally the two square crossing.Substrate can be using the transparent material such as glass or quartz or plastics.
In pel array, two grid lines are electrically connected to one-row pixels, as shown in Figure 2 a the TFT in the first row pixel PX
Grid is electrically connected on grid line G11, G12, wherein the grid positioned at the pixel PX of odd column TFT is electrically connected to grid line G11, position
Grid line G12 is electrically connected in the pixel PX of even column TFT grid；The grid of TFT in second row pixel PX is electrically connected to
On grid line G21, G22, wherein the grid positioned at the pixel PX of odd column TFT is electrically connected to grid line G21, positioned at the picture of even column
Plain PX TFT grid is electrically connected to grid line G22, the like.
Two adjacent pixel columns are jointly electrically connected to same data line：The TFT of all pixels in two adjacent pixel columns
Source/drain be electrically connected to same data wire, for example, as shown in Figure 2 a, the second pixel column and the 3rd pixel column, wherein all
Pixel PX TFT source/drain is jointly electrically connected to data wire D2；All pixels PX in 4th pixel column and the 5th pixel column
TFT source/drain be jointly electrically connected to data wire D3, the like.
As shown in Figure 2 b, all pixels PX TFT source/drain is electrically connected jointly in the first pixel column and the second pixel column
It is connected to data wire D1；3rd pixel column and the 4th pixel column wherein all pixels PX TFT source/drain are jointly electrically connected to
Data wire D2, the like.
It should be noted that for different pixel arrangements, the first pixel column and/or last pixel column can be without phases
An adjacent pixel column is attached thereto to same data wire, as shown in Figure 2 a；First pixel column and/or last pixel column can also
There is an adjacent pixel column to be attached thereto to same data wire, as shown in Figure 2 b.
Plurality of transmission lines T1-Tp in Fig. 2 a, each transmission line is arranged between adjacent two pixel column；And
Each transmission line is arranged between the adjacent data wire.That is, each transmission line is arranged at adjacent two
Between pixel column, but data wire can not be provided between two adjacent pixel columns where transmission line；I.e. each transmission line is set
Between the two adjacent pixel columns of data wire are not provided with.
For example, transmission line T1 is arranged between the first pixel column and the second pixel column, and positioned at data wire D1 and data wire
Between D2；Transmission line T2 is arranged between the 3rd pixel column and the 4th pixel column, and positioned between data wire D2 and data wire D3；
Transmission line T3 is arranged between the 5th pixel column and the 6th pixel column, and positioned between data wire D3 and data wire D4；Class successively
Push away.
The quantity of the transmission line T1-Tp is equal with grid line G11-Gm2 quantity, i.e. p=m, and p, m are positive integer, therefore transmission
Line T1-Tp is corresponded with grid line G11-Gm2 and electrically connected, and such as transmission line T1 is electrically connected with grid line Gm2 by the first via H.
The first insulating barrier 11 is provided between the grid line G and data wire D, makes the grid line G and data wire D electrical
Insulation, as shown in Figure 2 c, transmission line T can be located at same layer to concrete structure with data wire D, and such transmission line T can be with data
Line D is prepared using same material, in same processing step.By setting the first via H to run through the first insulating barrier 11 so that institute
Transmission line T is stated to be connected with the grid line G by the first via H.
Described grid drive chip Gate IC are arranged on data driving chip Source IC offside, such as Fig. 2 a institutes
State, it may be possible to reduce the typesetting area shared by cabling at the left and right side frame of panel.
The grid drive chip Gate IC are directly electrically connected with the transmission line T1-Tp, for example, transmission line T1 with
Gate IC are directly electrically connected.
The data driving chip Source IC are directly electrically connected with data wire D1-Dx, for example, data wire D1 with
Source IC are directly electrically connected.
For on double grid line style tft array substrate, described transmission line T and data wire D can disclosed in above-described embodiment one
To be not in same layer.In order to not increase the manufacturing process of tft array substrate, other conductors in existing tft array can be used
Transmission line is prepared, different according to TFT structure, the conductor that can be selected can be different, as long as the work as transmission line can be played
With.In general, same layer can be located at transmission line T and pixel electrode or public electrode, using identical material, such as
For, transmission line T and ITO（Indium tin oxide）Pixel electrode is same layer, concrete structure as shown in Figure 2 d, transmission line T and number
It is located at different layers according to line D, the first insulating barrier 11 is located between the grid line G and data wire D, and both is electrically insulated, the 3rd
Insulating barrier 12 is located between the transmission line T and data wire D, and both is electrically insulated；Transmission line T and ITO pixel electrodes 13
For same layer, the first insulating barrier 11 and the 3rd insulating barrier 12 are run through by the first via H of setting so that the transmission line T passes through
The first via H is connected with the grid line G.
Embodiment two
On the basis of the invention described above disclosed embodiment one, the invention discloses another double grid linear array substrate,
I.e.：With a driving chip IC while driven grid line and data wire, the driving chip are electrically connected with the data wire, the grid line
Connect.Therefore, it is possible to simplify processing step, price reduction cost.Peripheral wiring does not increase simultaneously, therefore typesetting rate will not be reduced.
Concrete structure is as shown in figure 3, transmission line T1-Tp and data wire D1-Dx can be located at same layer, using identical material
Material；With a driving chip IC while driven grid line and data wire, i.e. data wire D1-Dx is directly electrically connected to driving chip IC,
The transmission of data-signal is realized, for example, data wire D1 is directly electrically connected with driving chip IC；
Transmission line T1-Tp is directly electrically connected on driving chip IC, for example, transmission line T1 is directly electrically connected with driving chip IC
Connect；
Grid line G11-Gm2 electrically connects, as shown in Figure 2 c, transmission line T and data with transmission line T1-Tp by the first via H
Line D is located at same layer, and such transmission line T can be with data wire D preparations using same material, in same processing step.Pass through
The first via H is set to run through the first insulating barrier 11 so that the transmission line T is connected by the first via H and grid line G
Connect, so as to realize grid line G11-Gm2 and driving chip IC electrical connection.
Embodiment three
On the basis of the invention described above disclosed embodiment one, two, the invention discloses another double grid linear array base
Plate, i.e.,：Tft array substrate also including peripherally located region grid line lead L, positioned at the grid line lead L and transmission line T it
Between, and the second insulating barrier 14 for making the two be electrically insulated, through the second via LH of the insulating barrier.
Concrete structure is as shown in Fig. 4 a, 4b, and grid line lead L1-Lp is located at the outer peripheral areas of tft array substrate, grid line lead
L1-Lp and grid line G11-Gm2 is located at same layer；
As shown in fig. 4 a, data wire D1-Dx is directly to electrically connect with the driving chip IC, for example, data wire D1 is with driving
Dynamic chip IC is directly electrically connected；
As shown in Figure 4 b, grid line lead L and grid line G11-Gm2 are located at same layer, the grid line lead L and transmission line T it
Between, and the second insulating barrier 14 for making the two be electrically insulated, through the second via LH, the grid line lead L of the second insulating barrier 14
It is connected with described transmission line T by the second via LH；
As shown in fig. 4 a, the grid line lead L1-Lp is directly to electrically connect with the driving chip IC, for example, grid line draws
Line L1 is directly electrically connected with driving chip IC.Grid line G11-Gm2 is connected with transmission line T1-Tp by the first via H, such as Fig. 2 c or
Shown in Fig. 2 d, transmission line T1-Tp is connected with grid line lead L1-Lp by the second via LH, as shown in Figure 4 b, so as to realize transmission
Line T1-Tp is electrically connected with by the grid line lead L1-Lp with the driving chip IC, and then realizes grid line G11-Gm2 and institute
State driving chip IC electrical connections.
Example IV
A pair of grid line type array base palte disclosed by the invention, the size of tft array substrate resolution ratio is satisfied by resolution ratio bar
Part：M is the columns of pixel, and n is the line number of pixel, and m, n are positive integer.
On the basis of the invention described above disclosed embodiment one, two, three, the invention also discloses a kind of double grid line style battle array
Row substrate, i.e.,：Transmission line T1-Tq number is less than data wire D1-Dx（WhereinX, n take positive integer, the i.e. x to be（n+
1）The integer part of/2 acquired results）.
Concrete structure is as shown in figure 5, transmission line T number is q bars（Q is positive integer）, for example, in data wire D3, data
Transmission line T is not provided between line D4, but its size for meeting tft array substrate resolution ratio is satisfied by resolution condition：M is the columns of pixel, and n is the line number of pixel, and m, n are positive integer.
Shown by Fig. 5, only when transmission line T1-Tq number is less than data wire D1-Dx numbers, transmission line T1-
A kind of embodiment of Tq arrangements, the present invention includes this embodiment but not limited to this.
Embodiment five
A pair of grid line type array base palte disclosed by the invention, its described plurality of transmission lines T is corresponding with a plurality of grid line G electric
Connection, i.e. transmission line T quantity cannot be less than grid line G quantity, i.e., wherein p >=m, m, p are positive integer.Work as q>During m, that is, pass
Defeated quantity of the line T than grid line G is more, then all at least a transmission line T is connected electrically each grid line G, but due to transmission line T's
Quantity is more, can have some transmission line T not electrically connected with any grid line G.
On the basis of the invention described above disclosed embodiment one, two, three, four, the invention discloses another double grid line style
Array base palte, as shown in fig. 6, the quantity of the transmission line T1-Tq is more than grid line G11-Gm2 quantity, i.e. q>M, q, m are just whole
Number, therefore transmission line T1-Tq is not to correspond to electrically connect with grid line G11-Gm2, thus some transmission line T it is indirect or not with it is any
Grid line G is electrically connected.
For example, as shown in fig. 6, transmission line T2' and T2 is electrically connected with same grid line G, transmission line T2 passes through with transmission line T2'
Via connection is merged into same transmission line T and is electrically connected on driving chip IC.This connected mode can be prevented if transmission line
T2 breaks down, and transmission line T2' can still transmit signal, reduces the frequency that failure occurs.Certainly, transmission line T2' can also
Do not electrically connected with any grid line, only suspending is set.
Shown by Fig. 6, only when transmission line T1-Tq quantity is more than grid line G11-Gm2 quantity, transmission line
A kind of embodiment of T1-Tq arrangements, the present invention includes this embodiment but not limited to this.
In the double grid linear array substrate of the above-mentioned present invention disclosed of implementation one to five, described is dual gate knots
A kind of design of structure, but such a dual gate structures are not limited to, also apply to other enforceable dual gate structures.
Dual gate structures as shown in Figure 8, are to be connected to be connected on two grid lines with one-row pixels, adjacent
Two pixel columns are electrically connected to same data line, same grid line, i.e., two adjacent pixel columns, both TFT grid electrical connection
Onto same grid line, the TFT of all pixels therein source/drain is electrically connected to same data wire.For example, pixel PX2 with
The grid of pixel PX3, pixel PX2 TFT grid and pixel PX3 TFT is all electronically connected on grid line G12, pixel PX2 source
Pole/drain electrode and pixel PX3 source/drain are connected to data wire D2；The first row pixel is connected respectively to grid line G11（The first grid
Pole）, grid line G12（Second grid）On.
Plurality of transmission lines T in Fig. 8, each transmission line T is arranged between two pixel column, and, each biography
Defeated line is arranged between the adjacent data wire.For example, transmission line T1 is arranged between the first pixel column and the second pixel column；Pass
Defeated line T2 is arranged between the second pixel column and the 3rd pixel column；Transmission line T3 be arranged on the 3rd pixel column and the 4th pixel column it
Between；The like.
Various pieces are described by the way of progressive in this specification, and what each some importance illustrated is and other parts
Difference, between various pieces identical similar portion mutually referring to.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
Embodiment illustrated herein is not intended to be limited to, and is to fit to consistent with principles disclosed herein and features of novelty
Most wide scope.
Claims (12)
1. a kind of tft array substrate, including,
One substrate；
A plurality of grid line and a plurality of data lines that the insulation being arranged on the substrate intersects, the grid line are configured by row, the number
Configured according to line by row；
Pel array, each pixel is arranged at the infall of the grid line and the data wire, and two are electrically connected to one-row pixels
Bar grid line, two adjacent pixel columns are electrically connected to same data line；
It is characterized in that：The tft array substrate also includes, plurality of transmission lines, and each transmission line is arranged at adjacent institute
State between two pixel columns；And each transmission line is arranged between the adjacent data wire；
The plurality of transmission lines is corresponding with a plurality of grid line to be electrically connected；The number of the transmission line is less than the number of the data wire
Mesh.
2. tft array substrate as claimed in claim 1, it is characterised in that the size of described tft array substrate resolution ratio is needed
Meet resolution condition：M is the columns of pixel, and n is the line number of pixel, and m, n are positive integer.
3. tft array substrate as claimed in claim 1, it is characterised in that the tft array substrate also includes being located at the grid
Between line and data wire, and the first insulating barrier for making the two be electrically insulated；Through the first via of the insulating barrier.
4. the tft array substrate described in claim 3, it is characterised in that the transmission line by first via with it is described
Grid line is connected.
5. tft array substrate as claimed in claim 1, it is characterised in that described transmission line is with data line bit in same layer.
6. tft array substrate as claimed in claim 1, it is characterised in that described transmission line is with data line bit in different layers.
7. tft array substrate as claimed in claim 1, it is characterised in that the tft array substrate also includes data-driven core
Piece, grid drive chip, it is characterised in that the grid drive chip is electrically connected with the transmission line；The data-driven core
Piece is electrically connected with data wire；Described grid drive chip is arranged on the offside of data driving chip.
8. tft array substrate as claimed in claim 1, it is characterised in that the tft array substrate also includes a driving core
Piece, the driving chip is electrically connected with the data wire, the transmission line.
9. tft array substrate as claimed in claim 7 or 8, it is characterised in that the tft array substrate is also included positioned at outer
The grid line lead in region is enclosed, the grid line lead is located at same layer with the grid line；The transmission line passes through the grid line lead
Electrically connected with the driving chip.
10. tft array substrate as claimed in claim 9, it is characterised in that the tft array substrate is also included through described
Second via of insulating barrier；
The grid line lead is connected with described transmission line by the second via.
11. a kind of display panel, it is characterised in that including the tft array substrate as described in claim any one of 1-10.
12. a kind of display device, it is characterised in that including display panel as claimed in claim 11.
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| CN201310081939.0A CN103926764B (en) | 2013-03-14 | 2013-03-14 | A kind of tft array substrate and display panel, display device |
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| CN201310081939.0A CN103926764B (en) | 2013-03-14 | 2013-03-14 | A kind of tft array substrate and display panel, display device |
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| CN109387965A (en) * | 2017-08-03 | 2019-02-26 | 中华映管股份有限公司 | Image element array substrates |
| CN109283757A (en) * | 2018-07-31 | 2019-01-29 | 信利半导体有限公司 | A kind of novel display panel and electronic equipment |
| CN109143706A (en) * | 2018-09-18 | 2019-01-04 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel and display device |
| CN110010100B (en) * | 2019-05-10 | 2020-08-04 | 深圳市华星光电技术有限公司 | Pixel driving method |
| CN115793332B (en) * | 2022-11-29 | 2023-11-24 | 长沙惠科光电有限公司 | Display panel and display device |
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| CN101561596B (en) * | 2008-04-18 | 2011-08-31 | 群康科技(深圳)有限公司 | Active matrix display device |
| CN101487962B (en) * | 2009-01-20 | 2012-07-04 | 友达光电股份有限公司 | Display equipment with narrow frame structure and its driving method |
| CN102081246A (en) * | 2009-12-01 | 2011-06-01 | 群康科技(深圳)有限公司 | Liquid crystal display panel and liquid crystal display device |
| KR101717076B1 (en) * | 2010-11-20 | 2017-03-17 | 엘지디스플레이 주식회사 | Narrow bezel type array substrate and liquid crystal display device using the same |
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