CN103916123B - A kind of difference high-frequency clock frequency divider and method - Google Patents
A kind of difference high-frequency clock frequency divider and method Download PDFInfo
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Abstract
A kind of high speed multi-modulus frequency divider of low-power consumption, including level translator, 2/3 divider unit of mutually cascade.Overall structure of the invention is that traditional high speed multi-modulus frequency divider is optimized, and 2/3 frequency divider of TSPC structures is mainly added by level translator.And corrective measure is done on 2/3 frequency divider of level translator and TSPC structures, the characteristics of realize high-speed low-power-consumption.Fraction frequency device of the invention is succinct, has low-power consumption advantage to high-speed-differential small-signal frequency dividing, and such as 5G frequencies or so incoming frequency, frequency dividing ratio is more than 10, power consumption more than 50% can be saved than traditional SCL structures.
Description
Technical field
The present invention is a kind of high-speed wideband multi-modulus frequency divider, more particularly to ∑ Δ multi-modulus frequency divider field.It is used for decimal
Frequency dividing phase-locked loop and its digital communicating field being related to.
Background technology
Traditional fractional phase locked loop as shown in figure 1, including：Phase frequency detector (PFD), for comparison reference frequency and frequency divider
Export the phase difference of feedback frequency；Charge pump (CP) and loop filter (LPF), control is converted into by the phase difference that PFD is produced
Voltage is to voltage controlled oscillator；Voltage controlled oscillator (VCO), frequency is needed according to control voltage output；Multi-modulus frequency divider (MMD) is used for
Feedback frequency is produced to compare with reference frequency.
Multi-modulus frequency divider is formed by the cascade of 2/3 frequency divider, as shown in Figure 2.Each 2/3 frequency dividing in a dividing cycle
Device can do 3 frequency dividings under the control of control bit, remaining when do 2 frequency dividings, so as to reach 2nTo 2(n+1)- 1 continuous frequency dividing.It is conventional
Fractional modulation device be generally ∑ Δ structure, have shaping operation to quantizing noise, shift most of quantizing noise onto high frequency, pass through
Cycle of phase-locked loop low-pass characteristic is filtered.
In current conventional high-speed phase-locked loop, multi-modulus divider is realized using SCL structures more, as shown in Figure 3.Its structure is answered
Miscellaneous, dynamic power consumption is big, has generally taken up most of power consumption of phaselocked loop, so the power consumption for reducing multi-modulus frequency divider is whole for reducing
Individual phaselocked loop power consumption is most important.
The content of the invention
1. goal of the invention
For the problems of above-mentioned multi-modulus frequency divider and deficiency, it is an object of the invention to provide a kind of simple structure,
The multi-modulus frequency divider structure of high-speed low-power-consumption.The present invention is suitable for difference high-frequency clock frequency dividing.
2. technical scheme
According to the present invention, multi-modulus frequency divider includes：Level translator, 2/3 divider unit of mutually cascade.In order to reduce
Power consumption, multi-modulus frequency divider overall structure of the invention is simplified on the basis of Fig. 3, and the structure after optimization is only by level conversion
It is as shown in Figure 4 that device adds 2/3 frequency divider of TSPC structures to constitute.Because the level translator commonly used adds the 2/3 of TSPC structures to divide
Device is difficult to realize at a high speed, it is characteristic of the invention that having done optimization processing to level translator and 2/3 frequency divider internal structure, makes it
Realize high-speed data communication.
Conventional level shifter, is converted into single-ended signal, then change into by reverser using discharge circuit by differential signal
The signal of the full amplitude of oscillation, as shown in Figure 5.This structure is very sensitive to the DC-offset of input signal, when differential signal has direct current inclined
During shifting, it is exaggerated by operational amplifier, signal is deviateed the threshold voltage of reverser, output high level becomes burr, such as Fig. 5
Shown in output, can only be reduced by reduction of speed is influenceed.The present invention increased electricity between operational amplifier and reverser as shown in Figure 6
Hold and resistance, electric capacity has isolated DC to act on, and resistance plays direct current biasing, makes the DC-offset of reverser and input signal
Unrelated, such level translator can just support higher frequency.
2/3 conventional frequency divider general T SPC latch and logic unit as shown in fig. 7, be made up of.This 2/3 frequency divider
Speed restricted jointly by the time delay of TSPC latch and logic unit time delay.Be fused to for logic unit as shown in Figure 8 by the present invention
In TSPC latch, specific fusion process is as follows：
1) metal-oxide-semiconductor MN8_1 in Fig. 8, metal-oxide-semiconductor MN8_2 connect with metal-oxide-semiconductor MN8_3, metal-oxide-semiconductor MP8_1, metal-oxide-semiconductor MP8_2
Parallel connection, the drain electrode of serial module structure is mutually connected into inverter version with the drain electrode of parallel module, realizes logical AND gate device 31 in Fig. 7
The function of being latched with the first order in TSPC latch devices 32；Wherein metal-oxide-semiconductor MP8_1 is with the grid of metal-oxide-semiconductor MN8_1 by latching
The output end B controls of device 39；The grid of metal-oxide-semiconductor MP8_2 and metal-oxide-semiconductor MN8_2 is controlled by the output terminals A of latch 37；Metal-oxide-semiconductor
The grid of MN8_3 is controlled by input clock CLK.
2) metal-oxide-semiconductor MN8_4 in Fig. 8, metal-oxide-semiconductor MN8_5 connect with metal-oxide-semiconductor MN8_6, the drain electrode of serial module structure and metal-oxide-semiconductor
MP8_3 drain electrodes are mutually connected into inverter version, realize first in Fig. 7 in logical AND gate device 33 and TSPC latch devices 34
The function that level is latched.By the output A of traditional TSPC latch devices 34, reversely rear signal is controlled the grid of metal-oxide-semiconductor MN8_4；MOS
The grid of pipe MN8_5 is controlled (see multi-modulus frequency divider by carry-out MO (being MI for this level) signal of the frequency divider of upper level 2/3
Signal cascade relation in Fig. 2)；The grid of metal-oxide-semiconductor MP8_3 and metal-oxide-semiconductor MN8_6 is controlled by input clock CLK.
3) connected with MP8_6 again after metal-oxide-semiconductor MP8_4, metal-oxide-semiconductor MP8_5 parallel connection in Fig. 8, the wherein source electrode of MP8_6 connects electricity
Source, metal-oxide-semiconductor MP8_4, the drain electrode of metal-oxide-semiconductor MP8_5 and metal-oxide-semiconductor MN8_7 drain electrode is mutually connected into inverter version, realizes and patrol in Fig. 7
Collect the function of being latched with the first order in door gear 35 and TSPC latch devices 36.The grid of metal-oxide-semiconductor MP8_4 is latched by TSPC
The output Mo signals control of device device 38；The grid of metal-oxide-semiconductor MP8_5 is controlled by except 3 frequency dividings enable signal P；Metal-oxide-semiconductor MP8_6 with
The grid of metal-oxide-semiconductor MN8_7 is controlled by input clock CLK.
Prolonging for logic unit part is reduced after 1) 2) 3) be fused to for logic unit in TSPC latch by step above
When, improve operating rate.
3. beneficial effect
Using the present invention, 2/3 frequency divider of TSPC structures can be added to realize dividing at a high speed using simple level translator,
Power consumption is 50% or so of conventional high rate multi-modulus frequency divider structure under same frequency.
Brief description of the drawings
Below in conjunction with the accompanying drawings, the present invention will be described in detail
Fig. 1 represents fractional phase-lock ring structure
Fig. 2 represents multi-modulus frequency divider structure
Fig. 3 represents traditional multi-modulus frequency divider link structure
Fig. 4 represents multi-modulus frequency divider link structure of the invention
Fig. 5 represents conventional level shifter
Fig. 6 represents level translator of the invention
Fig. 7 represents conventional 2/3 frequency divider internal circuit
Fig. 8 represents 2/3 frequency divider internal circuit of the invention
Specific embodiment
The mode that current basic multi-modulus frequency divider chain route traditional 2/3 frequency divider cascade realizes, as shown in Figure 2.Pattern
Control signal Mo feedovers step by step, so with stronger speed advantage, and easily PLC technology.In order to utilize the structure
Advantage, the characteristics of can realize low-power consumption and high speed again, we pass through to simplify the side of link structure and 2/3 frequency divider internal circuit
Method is realized.Advantage of the invention is divided mainly for high-speed-differential small-signal, first by the small-signal of high-speed-differential by electricity
Flat turn parallel operation is converted into full swing signal, then is divided by 2/3 frequency divider of TSPC structures, such as Fig. 4.
As shown in fig. 6, increased electric capacity CO and resistance Rf between operational amplifier in traditional architectures and reverser.Electricity
Holding CO has isolated DC to act on, and makes the direct current of amplifier output signal and will not pass to the input of direction device, and direct current offset is also
Reverser is not interfered with to have input.Resistance plays direct current biasing, and new direct current biasing point is provided to reverser, biases it
In the half of supply voltage.So level translator speed is only influenceed by reverser speed and next stage driving.
Fig. 7 is 2/3 frequency divider inside basic structure, and it includes four latch and three and door, a TSPC latch
32 constitute basic except 2 frequency dividing patterns, and the 3rd latch (34) and the 4th latch (36) are gulped down for preceding two stage latch is provided
Pulse signal, such frequency divider can be just operated in except 3 frequency dividing patterns.As frequency dividing control position P=0, latch 36 is output as height
Level, realizes except 2 frequency dividings；As frequency dividing control position P=1, and during the feedback signal MI=1 of next stage, latch 4 is output as
0, the input pulse of latch 1 is told a cycle, realize except 3 frequency dividings.
Fig. 8 is 2/3 frequency divider internal circuit of the invention, identical with the function that 2/3 frequency divider (Fig. 7) is realized, only
It is that logic unit is dissolved into TSPC latch.It is real by latch in Fig. 8 (37) with door (31), latch (32) in Fig. 7
It is existing；Realized by latch in Fig. 8 (38) with door (33), latch (34)；With door (35), latch (36) by latch in Fig. 8
(39) realize.Said structure increases circuit compactness, reduces number of tubes, and each need to only increase a metal-oxide-semiconductor with door.While this
The signal lag that structure reduces logic unit is planted, so as to improve operating rate.
Claims (9)
1. a kind of high speed multi-modulus frequency divider of low-power consumption, circuit includes level translator and mutually 2/3 frequency divider of cascade, level
Converter includes operational amplifier and reverser, and 2/3 frequency divider is made up of TSPC latch and logic unit, it is characterised in that
Electric capacity C0 and resistance Rf is increased between the operational amplifier and reverser of level translator, and logic unit is fused to TSPC
In latch, metal-oxide-semiconductor MN8_1, metal-oxide-semiconductor MN8_2 are connected with metal-oxide-semiconductor MN8_3, metal-oxide-semiconductor MP8_1, metal-oxide-semiconductor MP8_2 are in parallel, string
The drain electrode of gang mould block is mutually connected into inverter version with the drain electrode of parallel module, realizes logical AND gate dress in first order latch devices
Put the function of being latched with the first order of TSPC latch devices；Metal-oxide-semiconductor MN8_4, metal-oxide-semiconductor MN8_5 connect with metal-oxide-semiconductor MN8_6, string
The drain electrode of gang mould block is mutually connected into inverter version with metal-oxide-semiconductor MP8_3 drain electrodes, realizes logical AND gate dress in the latch devices of the second level
Put the function of being latched with the second level of TSPC latch devices；Gone here and there with MP8_6 again after metal-oxide-semiconductor MP8_4, metal-oxide-semiconductor MP8_5 parallel connection
Connection, the wherein source electrode of MP8_6 connect power supply, and metal-oxide-semiconductor MP8_4, the drain electrode of metal-oxide-semiconductor MP8_5 are mutually connected into anti-with metal-oxide-semiconductor MN8_7 drain electrodes
Phase device form, realizes the work(that the third level of logical AND gate device and TSPC latch devices in third level latch devices is latched
Energy；The output of first order latch devices controls MN8_4 grids after negating as the input of second level latch devices；Latch the second level
The output of device device is used as third level latch devices input control MP8_4 grids；Third level latch devices are exported as first
Level latch devices input control MP8_1 grids；Three-level latch cascade feed back, realizes divider function；Except 3 frequency dividings enable letter
MP8_5 grids in number P control third level latch.
2. frequency divider as claimed in claim 1, it is characterised in that the grid of metal-oxide-semiconductor MP8_1 and metal-oxide-semiconductor MN8_1 is by the third level
The output end control of latch devices；The grid of metal-oxide-semiconductor MP8_2 and metal-oxide-semiconductor MN8_2 by first order latch devices output end
Control；The grid of metal-oxide-semiconductor MN8_3 is controlled by input clock CLK.
3. frequency divider as claimed in claim 1, it is characterised in that the grid of metal-oxide-semiconductor MN8_4 is by first order latch devices
Signal control after output reversely；The grid of metal-oxide-semiconductor MN8_5 is controlled by the carry output signals of the frequency divider of upper level 2/3；Metal-oxide-semiconductor
The grid of MP8_3 and metal-oxide-semiconductor MN8_6 is controlled by input clock CLK.
4. frequency divider as claimed in claim 1, it is characterised in that the grid of metal-oxide-semiconductor MP8_4 is by second level latch devices
Output signal is controlled；The grid of metal-oxide-semiconductor MP8_5 is controlled by except 3 frequency dividings enable signal；The grid of metal-oxide-semiconductor MP8_6 and metal-oxide-semiconductor MN8_7
Pole is controlled by input clock CLK.
5. frequency divider as claimed in claim 1, it is characterised in that electric capacity C0 plays isolated DC, resistance Rf plays direct current biasing
Effect, new direct current biasing point, the half for making it be biased in supply voltage are provided to reverser.
6. frequency divider as claimed in claim 1, it is characterised in that logic unit is fused in TSPC latch, reduces logic
The time delay of cell mesh, improves operating rate.
7. a kind of difference high-frequency clock dividing method, is applied in the circuit described in claim 1, it is characterised in that at a high speed
Differential small-signal is divided, and high-speed-differential small-signal first is converted into full swing signal by level translator, then pass through
2/3 frequency divider of TSPC structures is divided.
8. method as claimed in claim 7, it is characterised in that in order that level translator can support higher frequency, put in computing
Big to increase electric capacity and resistance between device and reverser, electric capacity has isolated DC to act on, and resistance plays direct current biasing, makes reverser
Direct current offset with input signal is unrelated.
9. method as claimed in claim 7, it is characterised in that in order to reduce the time delay of logic unit part, improves work speed
Degree, takes following steps：
1) metal-oxide-semiconductor MN8_1, metal-oxide-semiconductor MN8_2 are connected with metal-oxide-semiconductor MN8_3, metal-oxide-semiconductor MP8_1, metal-oxide-semiconductor MP8_2 are in parallel, series connection
The drain electrode of module is mutually connected into inverter version with the drain electrode of parallel module, realizes logical AND gate device in first order latch devices
The function of being latched with the first order of TSPC latch devices；
2) metal-oxide-semiconductor MN8_4, metal-oxide-semiconductor MN8_5 connect with metal-oxide-semiconductor MN8_6, the drain electrode of serial module structure and metal-oxide-semiconductor MP8_3 drain electrode phases
Inverter version is connected into, logical AND gate device is latched with the second level of TSPC latch devices in realizing second level latch devices
Function；
3) connected with MP8_6 again after metal-oxide-semiconductor MP8_4, metal-oxide-semiconductor MP8_5 parallel connection, wherein the source electrode of MP8_6 connects power supply, metal-oxide-semiconductor
MP8_4, the drain electrode of metal-oxide-semiconductor MP8_5 and metal-oxide-semiconductor MN8_7 drain electrode are mutually connected into inverter version, in realizing third level latch devices
The function that logical AND gate device is latched with the third level of TSPC latch devices.
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| CN201210595912.9A CN103916123B (en) | 2012-12-28 | 2012-12-28 | A kind of difference high-frequency clock frequency divider and method |
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| CN201210595912.9A CN103916123B (en) | 2012-12-28 | 2012-12-28 | A kind of difference high-frequency clock frequency divider and method |
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| CN103916123B true CN103916123B (en) | 2017-07-11 |
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| CN105262478B (en) * | 2015-11-16 | 2017-11-07 | 东南大学 | A kind of divider circuit of low-power consumption 2/3 based on E TSPC structures |
| CN114710149B (en) * | 2022-04-22 | 2024-05-07 | 西安微电子技术研究所 | All-N-channel depletion type D latch based on feedback type level conversion technology |
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| CN101789786A (en) * | 2009-01-22 | 2010-07-28 | 中国科学院半导体研究所 | Full-difference bimodule prescalar with low power consumption |
| CN102394642A (en) * | 2011-10-17 | 2012-03-28 | 重庆西南集成电路设计有限责任公司 | Phase-locked loop type frequency synthesizer and radio frequency program-controlled frequency divider |
| CN102497201A (en) * | 2011-12-21 | 2012-06-13 | 东南大学 | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption |
| CN102739239A (en) * | 2012-06-15 | 2012-10-17 | 江苏物联网研究发展中心 | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider |
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Patent Citations (4)
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| CN101789786A (en) * | 2009-01-22 | 2010-07-28 | 中国科学院半导体研究所 | Full-difference bimodule prescalar with low power consumption |
| CN102394642A (en) * | 2011-10-17 | 2012-03-28 | 重庆西南集成电路设计有限责任公司 | Phase-locked loop type frequency synthesizer and radio frequency program-controlled frequency divider |
| CN102497201A (en) * | 2011-12-21 | 2012-06-13 | 东南大学 | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption |
| CN102739239A (en) * | 2012-06-15 | 2012-10-17 | 江苏物联网研究发展中心 | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider |
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| High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers;Wu-Hsin Chen等;《IEEE Transactions on Circuits and Systems-II: Express Briefs》;20110314;第58卷(第3期);第144-148页 * |
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