CN103916123A - Difference high-speed clock frequency divider and method - Google Patents
Difference high-speed clock frequency divider and method Download PDFInfo
- Publication number
- CN103916123A CN103916123A CN201210595912.9A CN201210595912A CN103916123A CN 103916123 A CN103916123 A CN 103916123A CN 201210595912 A CN201210595912 A CN 201210595912A CN 103916123 A CN103916123 A CN 103916123A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- oxide
- metal
- latch
- tspc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
A low-power-consumption high-speed multi-mode frequency divider comprises a level converter and mutually-cascaded 2/3 frequency divider units. The overall structure of the frequency divider is obtained by carrying out optimization on a conventional high-speed multi-mode frequency divider and is mainly composed of a level converter and TSPC-structure 2/3 frequency dividers. The level converter and the TSPC-structure 2/3 frequency dividers are improved through improvement measures, and thus the characteristic of high speed and low power consumption is achieved. The frequency divider in the invention is concise in structure and has the advantages of low power consumption for high-speed difference small signal frequency division, for example: for an input frequency about 5G frequencies, frequency dividing ratio being larger than 10, the frequency divider can save more than 50% power compared with a conventional SCL-structure divider.
Description
Technical field
The present invention is a kind of high-speed wideband multi-modulus frequency divider, particularly ∑ Δ multi-modulus frequency divider field.The digital communicating field that is used for fractional frequency-division phase-locked loop and relates to.
Background technology
Tradition fractional phase locked loop as shown in Figure 1, comprising: phase frequency detector (PFD), for comparing the phase difference of reference frequency and frequency divider output feedback frequency; Charge pump (CP) and loop filter (LPF), the phase difference that PFD is produced converts to controls voltage to voltage controlled oscillator; Voltage controlled oscillator (VCO), needs frequency according to controlling Voltage-output; Multi-modulus frequency divider (MMD) is for generation of feedback frequency and reference frequency comparison.
Multi-modulus frequency divider is formed by 2/3 frequency divider cascade, as shown in Figure 2.Within a frequency division cycle, each 2/3 frequency divider can do 3 frequency divisions under the control at control bit, remaining time do 2 frequency divisions, thereby reach 2
nto 2
(n+1)-1 continuous frequency division.Conventional mark modulator is generally ∑ Δ structure, and quantizing noise is had to shaping operation, shifts most of quantizing noise onto high frequency, by cycle of phase-locked loop low-pass characteristic by its filtering.
In at present conventional high-speed phase-locked loop, adopt SCL structure to realize multimode divider, as shown in Figure 3 more.Its complex structure, dynamic power consumption is large, has conventionally occupied most of power consumption of phase-locked loop, so it is most important for reducing whole phase-locked loop power consumption to reduce the power consumption of multi-modulus frequency divider.
Summary of the invention
1. goal of the invention
For the existing problems and shortcomings of above-mentioned multi-modulus frequency divider, the object of this invention is to provide a kind of multi-modulus frequency divider structure of simple in structure, high-speed low-power-consumption.The present invention is applicable to difference high-frequency clock frequency division.
2. technical scheme
According to the present invention, multi-modulus frequency divider comprises: 2/3 divider unit of level translator, mutual cascade.In order to reduce power consumption, multi-modulus frequency divider overall structure of the present invention is to simplify on Fig. 3 basis, and 2/3 frequency divider that the structure after optimization only adds TSPC structure by level translator forms as shown in Figure 4.2/3 frequency divider that adds TSPC structure due to conventional level translator is difficult to realize at a high speed, and feature of the present invention is that level translator and 2/3 frequency divider internal structure have been done to optimization process, achieves high-speed data communication.
Tradition level translator, uses discharge circuit to convert differential signal to single-ended signal, then changes into the signal of the full amplitude of oscillation by reverser, as shown in Figure 5.This structure is very sensitive to the DC-offset of input signal, in the time that differential signal has direct current offset, is exaggerated by operational amplifier, make the threshold voltage of signal offset direction device, output high level becomes burr, as shown in Fig. 5 output, can only reduce impact by reduction of speed.The present invention has increased electric capacity and resistance as shown in Figure 6 between operational amplifier and reverser, electric capacity has isolated DC effect, resistance plays direct current biasing effect, makes the DC-offset of reverser and input signal irrelevant, and level translator just can be supported higher frequency like this.
2/3 conventional frequency divider as shown in Figure 7, is made up of general T SPC latch and logic unit.The speed of this 2/3 frequency divider is restricted by the time delay of TSPC latch and logical block time delay jointly.The present invention is fused to logical block in TSPC latch as shown in Figure 8, and concrete fusion process is as follows:
1) the metal-oxide-semiconductor MN8_1 in Fig. 8, metal-oxide-semiconductor MN8_2 connect with metal-oxide-semiconductor MN8_3, metal-oxide-semiconductor MP8_1, metal-oxide-semiconductor MP8_2 parallel connection, the source electrode of serial module structure is connected into inverter form mutually with the source electrode of parallel module, realized the function of the first order latch in logical AND gate device 31 and TSPC trigger device 32 in Fig. 7; Wherein the grid of metal-oxide-semiconductor MP8_1 and metal-oxide-semiconductor MN8_1 is controlled by the output B of latch 39; The grid of metal-oxide-semiconductor MP8_2 and metal-oxide-semiconductor MN8_2 is by the output terminals A control of trigger 37; The grid of metal-oxide-semiconductor MN8_3 is controlled by input clock CLK.
2) the metal-oxide-semiconductor MN8_4 in Fig. 8, metal-oxide-semiconductor MN8_5 connect with metal-oxide-semiconductor MN8_6, the source electrode of serial module structure is connected into inverter form mutually with metal-oxide-semiconductor MP8_3 source electrode, realized the function of the first order latch in logical AND gate device 33 and TSPC latch devices 34 in Fig. 7.The grid of metal-oxide-semiconductor MN8_4 is by the oppositely rear signal controlling of output A of traditional TSPC latch devices 34; The grid of metal-oxide-semiconductor MN8_5 is by carry output MO (being MI for the corresponding levels) signal controlling (seeing the signal cascade relation in multi-modulus frequency divider Fig. 2) of upper level 2/3 frequency divider; The grid of metal-oxide-semiconductor MP8_3 and metal-oxide-semiconductor MN8_6 is controlled by input clock CLK.
3) after the metal-oxide-semiconductor MP8_4 in Fig. 8, metal-oxide-semiconductor MP8_5 parallel connection, connect with MP8_6 again, wherein the drain electrode of MP8_6 connects power supply, the source electrode of metal-oxide-semiconductor MP8_4, metal-oxide-semiconductor MP8_5 is connected into inverter form mutually with metal-oxide-semiconductor MN8_7 source electrode, realized the function of the first order latch in logical AND gate device 35 and TSPC latch devices 36 in Fig. 7.The grid of metal-oxide-semiconductor MP8_4 is by the output Mo signal controlling of TSPC latch devices 38; The grid of metal-oxide-semiconductor MP8_5 is by controlling except 3 frequency division enable signal P; The grid of metal-oxide-semiconductor MP8_6 and metal-oxide-semiconductor MN8_7 is controlled by input clock CLK.
Through above 1) 2) 3) step reduced the time delay of logical block part after logical block is fused in TSPC latch, improved operating rate.
3. beneficial effect
Utilize the present invention, 2/3 frequency divider that can adopt simple level translator to add TSPC structure is realized high speed frequency division, and under same frequency, power consumption is 50% left and right of traditional high speed multi-modulus frequency divider structure.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, describe the present invention
Fig. 1 represents fractional phase locked loop structure
Fig. 2 represents multi-modulus frequency divider structure
Fig. 3 represents traditional multi-modulus frequency divider link structure
Fig. 4 represents multi-modulus frequency divider link structure of the present invention
Fig. 5 represents traditional level translator
Fig. 6 represents level translator of the present invention
Fig. 7 represents conventional 2/3 frequency divider internal circuit
Fig. 8 represents 2/3 frequency divider internal circuit of the present invention
Embodiment
The mode of current basic multi-modulus frequency divider chain route tradition 2/3 frequency divider cascade realizes, as shown in Figure 2.Mode control signal Mo feedovers step by step, thus there is stronger speed advantage, and very convenient control able to programme.In order to utilize the advantage of this structure, can realize again low-power consumption and feature at a high speed, we realize by the method for reducible chain line structure and 2/3 frequency divider internal circuit.Advantage of the present invention is carried out frequency division mainly for high-speed-differential small-signal, first converts the small-signal of high-speed-differential to full swing signal by level translator, then carries out frequency division by 2/3 frequency divider of TSPC structure, as Fig. 4.
As shown in Figure 6, capacitor C 0 and resistance R _ f between the operational amplifier in traditional structure and reverser, have been increased.Capacitor C 0 has isolated DC effect, makes the direct current of amplifier output signal can not pass to the input of direction device, and direct current offset also just can not have influence on reverser and input.Resistance plays direct current biasing effect, provides new direct current biasing point to reverser, makes it be biased in the half of supply voltage.Level translator speed is driven by reverser speed and next stage only like this affects.
Fig. 7 is the inner basic structure of 2/3 frequency divider, it comprises four latchs and three and door, the one TSPC trigger 32 has formed the basic 2 frequency division patterns of removing, the 3rd latch (34) and quad latch (36) provide swallow pulse signal for front two stage latch, and frequency divider just can be operated in except 3 frequency division patterns like this.In the time of the P=0 of frequency dividing control position, latch 36 is output as high level, realizes except 2 frequency divisions; In the time of the P=1 of frequency dividing control position, and when the feedback signal MI=1 of next stage, latch 4 is output as 0, and latch 1 input pulse is told to one-period, realizes except 3 frequency divisions.
Fig. 8 is 2/3 frequency divider internal circuit of the present invention, identical with the function that 2/3 frequency divider (Fig. 7) is realized, and just logic unit is dissolved in TSPC latch.Being realized by trigger in Fig. 8 (37) with door (31), trigger (32) in Fig. 7; Realized by trigger in Fig. 8 (38) with door (33), latch (34); Realized by trigger in Fig. 8 (39) with door (35), latch (36).Said structure increases circuit compactedness, reduces number of tubes, and each and door only needs to increase a metal-oxide-semiconductor.The signal lag of this structure decrease logic unit simultaneously, thus operating rate improved.
Claims (9)
1. the high speed multi-modulus frequency divider of a low-power consumption, comprise 2/3 frequency divider of level translator and mutual cascade, level translator comprises operational amplifier and reverser, 2/3 frequency divider is made up of TSPC latch and logic unit, it is characterized in that having increased capacitor C 0 and resistance R _ f between the operational amplifier of level translator and reverser, and logical block is fused in TSPC latch, by metal-oxide-semiconductor MN8_1, metal-oxide-semiconductor MN8_2 connects with metal-oxide-semiconductor MN8_3, metal-oxide-semiconductor MP8_1, metal-oxide-semiconductor MP8_2 parallel connection, the source electrode of serial module structure is connected into inverter form mutually with the source electrode of parallel module, realize the function of the first order latch of logical AND gate device and TSPC trigger device in TSPC latch, metal-oxide-semiconductor MN8_4, metal-oxide-semiconductor MN8_5 connect with metal-oxide-semiconductor MN8_6, and the source electrode of serial module structure is connected into inverter form mutually with metal-oxide-semiconductor MP8_3 source electrode, realize the function of the first order latch of logical AND gate device and TSPC latch devices in TSPC latch, after metal-oxide-semiconductor MP8_4, metal-oxide-semiconductor MP8_5 parallel connection, connect with MP8_6 again, wherein the drain electrode of MP8_6 connects power supply, the source electrode of metal-oxide-semiconductor MP8_4, metal-oxide-semiconductor MP8_5 is connected into inverter form mutually with metal-oxide-semiconductor MN8_7 source electrode, realizes the function of the first order latch of logical AND gate device and TSPC latch devices in TSPC latch.
2. frequency divider as claimed in claim 1, is characterized in that the grid of metal-oxide-semiconductor MP8_1 and metal-oxide-semiconductor MN8_1 is by the output control of latch; The grid of metal-oxide-semiconductor MP8_2 and metal-oxide-semiconductor MN8_2 is by the output control of trigger; The grid of metal-oxide-semiconductor MN8_3 is controlled by input clock CLK.
3. frequency divider as claimed in claim 1, is characterized in that the grid of metal-oxide-semiconductor MN8_4 is by the oppositely rear signal controlling of output of TSPC latch devices; The grid of metal-oxide-semiconductor MN8_5 is by the carry output signals control of upper level 2/3 frequency divider; The grid of metal-oxide-semiconductor MP8_3 and metal-oxide-semiconductor MN8_6 is controlled by input clock CLK.
4. frequency divider as claimed in claim 1, is characterized in that the grid of metal-oxide-semiconductor MP8_4 is by the output signal control of TSPC latch devices 38; The grid of metal-oxide-semiconductor MP8_5 is by removing 3 frequency division enable signal controls; The grid of metal-oxide-semiconductor MP8_6 and metal-oxide-semiconductor MN8_7 is controlled by input clock CLK.
5. frequency divider as claimed in claim 1, is characterized in that capacitor C 0 plays isolated DC effect, and resistance R _ f plays direct current biasing effect, provides new direct current biasing point to reverser, makes it be biased in the half of supply voltage.
6. frequency divider as claimed in claim 1, is characterized in that logical block to be fused in TSPC latch, reduces the time delay of logical block part, improves operating rate.
7. a difference high-frequency clock dividing method, be applied in circuit claimed in claim 1, it is characterized in that carrying out frequency division for high-speed-differential small-signal, first convert high-speed-differential small-signal to full swing signal by level translator, then carry out frequency division by 2/3 frequency divider of TSPC structure.
8. method as claimed in claim 7, it is characterized in that, in order to make level translator can support higher frequency, increasing electric capacity and resistance between operational amplifier and reverser, electric capacity has isolated DC effect, resistance plays direct current biasing effect, makes the direct current offset of reverser and input signal irrelevant.
9. method as claimed in claim 7, is characterized in that the time delay in order to reduce logical block part, improves operating rate, takes following steps:
1) metal-oxide-semiconductor MN8_1, metal-oxide-semiconductor MN8_2 are connected with metal-oxide-semiconductor MN8_3, metal-oxide-semiconductor MP8_1, metal-oxide-semiconductor MP8_2 parallel connection, the source electrode of serial module structure is connected into inverter form mutually with the source electrode of parallel module, realizes the function of the first order latch of logical AND gate device and TSPC trigger device in TSPC latch;
2) metal-oxide-semiconductor MN8_4, metal-oxide-semiconductor MN8_5 connect with metal-oxide-semiconductor MN8_6, and the source electrode of serial module structure is connected into inverter form mutually with metal-oxide-semiconductor MP8_3 source electrode, realize the function of the first order latch of logical AND gate device and TSPC latch devices in TSPC latch;
3) after metal-oxide-semiconductor MP8_4, metal-oxide-semiconductor MP8_5 parallel connection, connect with MP8_6 again, wherein the drain electrode of MP8_6 connects power supply, the source electrode of metal-oxide-semiconductor MP8_4, metal-oxide-semiconductor MP8_5 is connected into inverter form mutually with metal-oxide-semiconductor MN8_7 source electrode, realizes the function of the first order latch of logical AND gate device and TSPC latch devices in TSPC latch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210595912.9A CN103916123B (en) | 2012-12-28 | 2012-12-28 | A kind of difference high-frequency clock frequency divider and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210595912.9A CN103916123B (en) | 2012-12-28 | 2012-12-28 | A kind of difference high-frequency clock frequency divider and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103916123A true CN103916123A (en) | 2014-07-09 |
| CN103916123B CN103916123B (en) | 2017-07-11 |
Family
ID=51041557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210595912.9A Active CN103916123B (en) | 2012-12-28 | 2012-12-28 | A kind of difference high-frequency clock frequency divider and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103916123B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105262478A (en) * | 2015-11-16 | 2016-01-20 | 东南大学 | E-TSPC structure-based low-power 2/3 frequency divider circuit |
| CN114710149A (en) * | 2022-04-22 | 2022-07-05 | 西安微电子技术研究所 | Full N-channel depletion type D latch based on feedback type level conversion technology |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789786B (en) * | 2009-01-22 | 2013-06-12 | 中国科学院半导体研究所 | Full-difference bimodule prescalar with low power consumption |
| CN102394642B (en) * | 2011-10-17 | 2013-09-18 | 重庆西南集成电路设计有限责任公司 | Phase-locked loop type frequency synthesizer and radio frequency program-controlled frequency divider |
| CN102497201A (en) * | 2011-12-21 | 2012-06-13 | 东南大学 | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption |
| CN102739239B (en) * | 2012-06-15 | 2014-11-05 | 江苏物联网研究发展中心 | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider |
-
2012
- 2012-12-28 CN CN201210595912.9A patent/CN103916123B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105262478A (en) * | 2015-11-16 | 2016-01-20 | 东南大学 | E-TSPC structure-based low-power 2/3 frequency divider circuit |
| CN105262478B (en) * | 2015-11-16 | 2017-11-07 | 东南大学 | A kind of divider circuit of low-power consumption 2/3 based on E TSPC structures |
| CN114710149A (en) * | 2022-04-22 | 2022-07-05 | 西安微电子技术研究所 | Full N-channel depletion type D latch based on feedback type level conversion technology |
| CN114710149B (en) * | 2022-04-22 | 2024-05-07 | 西安微电子技术研究所 | All-N-channel depletion type D latch based on feedback type level conversion technology |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103916123B (en) | 2017-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7859345B2 (en) | Semiconductor integrated circuit | |
| US8406271B2 (en) | Spread spectrum clock generating circuit | |
| CN103312319B (en) | Be applied to the spurious reduction phase frequency detector circuit in integer-N PLL | |
| CN106067787A (en) | A kind of clock generation circuit being applied to charge pump system | |
| US20110156782A1 (en) | Onion waveform generator and spread spectrum clock generator using the same | |
| CN101888244B (en) | Low-power consumption phase-locked loop circuit | |
| CN106788400A (en) | The dutycycle quadrature divider of broadband programmable 50% of high-speed low-power-consumption | |
| CN103532522B (en) | Dutyfactor adjustment circuit, Double-end-to-singlecircuit circuit and oscillator | |
| CN103684445A (en) | Multiphase high-resolution phase locked loop | |
| CN202617065U (en) | Low voltage voltage-controlled oscillator capable of restraining power supply noise | |
| CN103916123A (en) | Difference high-speed clock frequency divider and method | |
| CN103078498B (en) | A kind of voltage conversion circuit and using method thereof | |
| CN102340308B (en) | Fractional-N frequency synthesizer | |
| CN102394642B (en) | Phase-locked loop type frequency synthesizer and radio frequency program-controlled frequency divider | |
| CN105281760B (en) | Voltage-controlled oscillator based on even nonlinear amplitude feedback | |
| CN102035545A (en) | Common mode point controllable annular voltage-controlled oscillator | |
| CN203747754U (en) | 1/2 frequency divider circuit based on current mirror switching logic and frequency divider | |
| US8824615B2 (en) | Frequency tracing circuit and method thereof | |
| CN101630957A (en) | Dual-mode prescaler with adaptive dormancy | |
| CN102142837A (en) | Inductance-capacitance voltage-controlled oscillator capable of lowering phase noise near carrier | |
| CN106788421B (en) | Frequency synthesizer | |
| CN204304986U (en) | A kind of high-speed phase-locked loop loop oscillator circuit | |
| CN205811975U (en) | It is applied to the clock generation circuit of charge pump system | |
| CN105337591A (en) | Circuit structure and method for realizing clock recovery on the basis of USB device | |
| CN115133764A (en) | Low EMI high frequency Buck controller circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Applicant after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Applicant before: Beijing CEC Huada Electronic Design Co., Ltd. |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |