CN103916102B - A kind of embedded digital low power consuming clock of FPGA produces circuit - Google Patents

Abstract

An all-digital low-power clock generation circuit embedded in FPGA, including a digitally controlled oscillator and a control code generation circuit. Through the improved design of the traditional all-digital adjustable oscillator circuit, the delay unit of the delay chain in the digital control oscillator is changed to a controlled three-state delay unit, and the enable control code is added to the control code generation circuit The generating circuit closes the unused tri-state delay unit in the delay chain, completely eliminating the invalid dynamic power consumption of the oscillator circuit. With this structure of low-power all-digital adjustable oscillator circuit, the power consumption of the high-frequency output working state is reduced to one tenth of the original, and the wider the working frequency range of the delay chain, the more obvious the improvement effect, making the technology When designing a clock generating circuit, personnel can simultaneously take into account a wide range of adjustable oscillation frequency indicators and low power consumption indicators.

Description

An all-digital low-power clock generation circuit embedded in FPGA

technical field

The invention relates to an FPGA embedded all-digital clock generation circuit, in particular to an all-digital low-power clock generation circuit optimized for FPGA embedded application requirements, belonging to the field of integrated circuits.

Background technique

FIG. 1 is a schematic diagram of a traditional all-digital clock generating circuit, which is mainly composed of a delay chain 110, a multiplexer 120, and a control decoding circuit 130. The delay chain is composed of a plurality of basic delay units 111. The delay chain 110 generates different clock delays and sends them to the multiplexer 120 for selection, and the multiplexer (120) outputs the selected delayed clock under the control of the selection control signal (132) (121) is sent to the input end of the delay chain to form a feedback oscillator structure; in this process, the specific delay value is adjusted by the selection control signal (132) output by the multiplexing control decoding generation circuit (130), and the complex The input of the control decoding generating circuit (130) is the control signal (131) sent from the outside.

There is an obvious disadvantage in using the traditional clock generation circuit in Fig. 1. When the delay chain (110) is in the high-frequency working state, the required delay is relatively small, and only a small number of delay units (such as 110-1 ) into the feedback oscillating loop, other delay units (110-2 to 110-N) are invalid circuits at this time, high-frequency clocks will also produce rapid flips on these invalid circuits, which will produce very large dynamic Power consumption, the increase of dynamic power consumption shows an exponential upward trend with the increase of frequency, which greatly limits the upper limit of the operating frequency of the clock generation circuit.

Therefore, it is necessary to propose a clock generation circuit structure optimized for low power consumption, so as to obtain a wide range of upper and lower operating frequencies with controllable power consumption.

Contents of the invention

The problem solved by the technology of the present invention is: to overcome the deficiencies of the prior art, provide an all-digital low-power clock generation circuit structure, and solve the problem of excessive dynamic power consumption of the traditional clock generation circuit under high-frequency operation And the problem of limiting the upper limit of the highest operating frequency.

Technical solution of the present invention is:

An all-digital low-power clock generation circuit embedded in an FPGA, including: a digitally controlled oscillator and a control code generating circuit; the digitally controlled oscillator includes a multiplexer, a NAND gate, and a delay chain; the control code generating circuit includes Enable control code generation circuit and multiplexing control decoding generation circuit;

The multiplexing control decoding generation circuit receives the control signal input from the outside, generates the selection control signal and the shift control signal, the selection control signal is sent to the selection end of the multiplexer, and the shift control signal is sent to the enable control code generation circuit The selection end of the enable control code generation circuit is under the control of the shift control signal, and the shift generates the enable control code, which is sent to the enable end of the delay chain, and the invalid delay unit is closed;

The delay chain is composed of a plurality of basic three-state delay units connected end to end; the input end of the delay chain is connected with the output end of the NAND gate, and the output end of the delay chain is connected with the input end of the multiplexer;

The multiplexer receives each phase clock from the delay chain, and simultaneously receives the selection control signal of the multiplexing control decoding generation circuit, and outputs the selected delayed clock from the clock output terminal as the output of the clock generation circuit, At the same time, the selected delayed clock is also fed back to one input terminal of the NAND gate, and the other input terminal of the NAND gate accepts an externally input reset signal;

The enable control code generation circuit includes a plurality of shift register units connected in series, and shifts the sequence of 1 and 0 under the control of the shift control signal to generate a digital enable control code.

The shift register unit includes a two-to-one multiplexer MUX, a storage unit SRAM, a first transmission control tube, a second transmission control tube and an inverter;

The two input terminals of the two-to-one multiplexer MUX are respectively connected to the output of the previous shift register unit and the output of the next shift register unit, and the output of the two-to-one multiplexer MUX is sent to the storage unit SRAM, and the storage unit The output of the SRAM is sent to the inverter through the first transmission control tube for reverse processing, and then output to the input of the two-choice multiplexer MUX in the previous shift register unit and the next shift through the second transmission control tube The input of the one-of-two multiplexer MUX in the register unit; the output terminal of the inverter is taken as the input of the enabling terminal of the corresponding delay unit in the delay chain.

The first transmission control transistor and the second transmission control transistor use NMOS transistors or PMOS transistors.

The delay chain includes a plurality of three-state delay units connected in series, and the three-state delay unit includes an inverter, an equivalent capacitor and a NAND gate, and the externally input clock signal is reversed by the inverter It is fed into one input terminal of the NAND gate, and at the same time, the output terminal of the inverter is also grounded through an equivalent capacitance, and the other input terminal of the NAND gate receives the enable control code output by the enable control code generating circuit.

The beneficial effect of the present invention compared with prior art is:

(1) The all-digital low-power clock generation circuit of the present invention can greatly reduce the dynamic power consumption of the oscillator of the clock generation circuit under high-frequency operation. Compared with the clock generation circuit with traditional structure, the high-frequency dynamic power consumption can be reduced as low as one-tenth;

(2) The clock generating circuit of the present invention can be equipped with a phase detector, a frequency divider and an algorithm control circuit to form a low-power all-digital phase-locked loop, and a full-digital lock using the clock generating circuit structure 11111111111111 The phase loop does not need to consider too much dynamic power consumption under high frequency conditions, nor does it need to be equipped with a power network with high current capability, which saves area for chip design.

Description of drawings

Fig. 1 is the schematic diagram of the clock generation circuit of traditional structure;

Fig. 2 is a schematic diagram of an all-digital low-power clock generating circuit of the present invention;

Fig. 3 is a structural diagram of a delay unit with a control terminal;

Fig. 4 is a structural diagram of the circuit module for enabling control code generation;

Fig. 5 is a detailed structural schematic diagram of a shift register unit;

FIG. 6 is a schematic diagram of the working sequence of the shift register unit.

detailed description

The present invention is a digital low-power clock generation circuit embedded in FPGA, which includes: a digital control oscillator 200 and a control code generation circuit 300 . Specifically, the digitally controlled oscillator 200 is composed of a multiplexer 220, a NAND gate 240 and a delay chain 210; the control code generation circuit 300 includes an enable control code generation circuit 340 and a multiplexing control decoding generation circuit 330 . The relationship between these circuit blocks can be seen in Figure 2:

The multiplexing control decoding generation circuit receives the control signal input from the outside, generates the selection control signal and the shift control signal, the selection control signal is sent to the selection end of the multiplexer, and the shift control signal is sent to the enable control code generation circuit The selection end of the enable control code generation circuit is under the control of the shift control signal, and the shift generates the enable control code, which is sent to the enable end of the delay chain, and the invalid delay unit is closed;

The delay chain is composed of a plurality of basic three-state delay units connected end to end; the input end of the delay chain is connected with the output end of the NAND gate, and the output end of the delay chain is connected with the input end of the multiplexer;

The multiplexer receives each phase clock from the delay chain, and simultaneously receives the selection control signal of the multiplexing control decoding generation circuit, and outputs the selected delayed clock from the clock output terminal as the output of the clock generation circuit, At the same time, the selected delayed clock is also fed back to one input terminal of the NAND gate, and the other input terminal of the NAND gate receives an externally input reset signal.

The shift register unit includes a two-to-one multiplexer MUX, a storage unit SRAM, a first transmission control tube, a second transmission control tube and an inverter;

The two input terminals of the two-to-one multiplexer MUX are respectively connected to the output of the previous shift register unit and the output of the next shift register unit, and the output of the two-to-one multiplexer MUX is sent to the storage unit SRAM, and the storage unit The output of the SRAM is sent to the inverter through the first transmission control tube for reverse processing, and then output to the input of the two-choice multiplexer MUX in the previous shift register unit and the next shift through the second transmission control tube The input of the one-of-two multiplexer MUX in the register unit; the output terminal of the inverter is taken as the input of the enabling terminal of the corresponding delay unit in the delay chain.

The delay chain includes a plurality of three-state delay units connected in series. The three-state delay units include inverters, equivalent capacitors and NAND gates. The externally input clock signal is sent to One input terminal of the NAND gate, meanwhile, the output terminal of the inverter is also grounded through an equivalent capacitor, and the other input terminal of the NAND gate receives the enable control code output by the enable control code generating circuit.

The delay chain 200 delays the clock after the reset terminal 211 fails. N delay units can generate N different delays. Under the control of the selection control signal 232, a suitable one is selected through the multiplexer 220. The delayed clock is sent to the clock output terminal 221, and also fed back to the delay chain 210 as the clock input, thus forming a closed-loop oscillation structure, that is, the digitally controlled oscillator 200, which can adjust different delay values by changing the control code to generate oscillating clocks of different frequencies.

The improvement of the circuit architecture in the present invention includes the use of a turn-off delay unit and enabling control codes for dynamic adjustment, blocking the clock inversion of most of the delay units in the non-working state when generating high-frequency clocks, To achieve the purpose of reducing dynamic power consumption, take a 500-level delay chain as an example. When the generated clock is at the upper limit of the operating frequency range of the delay chain, no more than 25 delay units are used, and the other 475 delay units The time units are driven by high-frequency clocks to perform invalid actions, resulting in more than 90% of dynamic power consumption.

In order to realize the improvement of the circuit structure of the present invention, the traditional delay unit is firstly improved, and an enable control terminal is added, as shown in FIG. 3 . In the present invention, the delay unit 500 with an enabling control terminal mainly includes an inverter, an equivalent capacitor and a NAND gate, collectively referred to as a delay device 510, in addition to a clock input 511 and a clock delay output 512, there are Enable the control terminal 513, when the enable control terminal 513 inputs a high level, the delay unit 500 is in an active state, the clock delay output terminal 512 follows the clock input 511 for delayed output, when the enable control terminal 513 inputs a low level , the delay unit is turned off, and the clock delay output 512 is always at a high level, saving the dynamic power consumption of subsequent cascaded delay units.

In order to realize the control of the digitally controlled oscillator 200 of the present invention, the control code generation circuit 300 is improved on the basis of the traditional design, and the multiplexing control decoding generation circuit 330 is still used to generate the selection control signal 232 to the multiplexer 220 On this basis, an enabling control code generation circuit 340 is additionally designed, under the control of the shift control signal 333, an N-bit enabling control code is generated to dynamically disable invalid delay units.

The enabling control code generation circuit 340 is used to generate a sequence composed of N bits of 1 or 0, and the circuit structure is equivalent to a chain of left and right shift registers. If the boundary point between 1 and 0 in the enabling control code is defined as the adjustment point, Then the enabling control codes on the left side of the adjustment point (including the adjustment point) are all 1, and on the right side of the adjustment point are all 0, and the position of the adjustment point is dynamically adjusted according to the control of the shift control signal 333 . The shift control signal 333 includes an addition and subtraction signal 341, a shift control signal 1 and a shift control signal 2. Under the common control of the three signals, the sequence composed of 1 and 0 is properly shifted left and right, and the left and right shifts are performed during the shift process. The side is padded with 1s, and the right side is padded with 0s. For example, the N-bit control signal at the initial moment may be 11111111111...110000, and after multiple dynamic adjustments, it becomes 11100000000...000000. In this process, the delay unit corresponding to "0" in the control signal will be is turned off to achieve the purpose of reducing dynamic power consumption.

The enabling control code generating circuit 340 in the present invention is composed of N shift register units 340-1, 340-2 to 340-N, as shown in FIG. 4 .

Figure 5 is a schematic diagram of the detailed structure of the shift register unit, including a two-to-one multiplexer MUX345, a storage unit SRAM346, a transmission control tube 1 (the first transmission control tube 347), and a transmission control tube 2 (the second transmission control tube 349) And the inverter 348, the transmission control tube 1 and the transmission control tube 2 adopt PMOS tubes or NMOS tubes. One-to-two multiplexer MUX345 can receive the output 603 from the previous unit or the output 604 from the next unit under the control of the addition and subtraction signal (341), as a shift input, and can also send the value in the storage unit SRAM346 to To one input 601 of the mux of the preceding unit or the other input 602 of the mux of the following unit.

Figure 6 is a schematic diagram of the working sequence of the shift register unit. During the shift operation, on the rising edge of each clock cycle, the shift control signal 1 is first reduced to a low level, and the transmission control tube 1 is turned off, and the storage unit SRAM The value depends on the transistor capacitance and temporarily stores in the dynamic storage node A (650), and then the shift control signal 2 rises to high level, turns on the transmission control tube 2, and writes the value stored in this unit into the next unit (specifically sent to The previous unit or the latter unit is controlled by the addition and subtraction signal 341), then turn off the transmission control tube 2 in turn, turn on the transmission control tube 1, update the output value of the enable control code 344-m, and complete a data shift .

Claims (4)

1. An all-digital low-power clock generation circuit embedded in FPGA is characterized in that it comprises: a digitally controlled oscillator and a control code generating circuit; the digitally controlled oscillator includes a multiplexer, a NAND gate and a delay chain; The control code generation circuit includes an enable control code generation circuit and a multiplexing control decoding generation circuit; The multiplexing control decoding generation circuit receives the control signal input from the outside, generates the selection control signal and the shift control signal, the selection control signal is sent to the selection end of the multiplexer, and the shift control signal is sent to the enable control code generation circuit The selection end of the enable control code generation circuit is under the control of the shift control signal, and the shift generates the enable control code, which is sent to the enable end of the delay chain, and the invalid delay unit is closed; The delay chain includes a plurality of three-state delay units connected in series; the input end of the delay chain is connected with the output end of the NAND gate, and the output end of the delay chain is connected with the input end of the multiplexer; The multiplexer receives each phase clock from the delay chain, and simultaneously receives the selection control signal of the multiplexing control decoding generation circuit, and outputs the selected delayed clock from the clock output terminal as the output of the clock generation circuit, At the same time, the selected delayed clock is also fed back to one input terminal of the NAND gate, and the other input terminal of the NAND gate accepts an externally input reset signal; The three-state delay unit includes an inverter, an equivalent capacitor and a NAND gate, and the externally input clock signal is sent to an input terminal of the NAND gate after being reversed by the inverter, and at the same time, the output terminal of the inverter It is also grounded through an equivalent capacitor, and the other input terminal of the NAND gate receives the enable control code output by the enable control code generating circuit. 2. a kind of FPGA embedded all-digital low power consumption clock generation circuit according to claim 1, is characterized in that: described enabling control code generation circuit comprises a plurality of shift register units connected in series, in shift control A sequence of 1s and 0s is shifted under the control of the signal to generate a digital enable control code. 3. a kind of FPGA embedded all-digital low power consumption clock generating circuit according to claim 2, is characterized in that: described shift register unit comprises two to select one multiplexer MUX, storage unit SRAM, the first transmission control tube, second transmission control tube and reverser; The two input terminals of the two-to-one multiplexer MUX are respectively connected to the output of the previous shift register unit and the output of the next shift register unit, and the output of the two-to-one multiplexer MUX is sent to the storage unit SRAM, and the storage unit The output of the SRAM is sent to the inverter through the first transmission control tube for reverse processing, and then output to the input of the two-choice multiplexer MUX in the previous shift register unit and the next shift through the second transmission control tube The input of the one-of-two multiplexer MUX in the register unit; the output terminal of the inverter is taken as the input of the enabling terminal of the corresponding delay unit in the delay chain. 4. A FPGA-embedded all-digital low-power clock generation circuit according to claim 3, characterized in that: the first transmission control tube and the second transmission control tube use NMOS transistors or PMOS transistors.