CN103916102B - A kind of embedded digital low power consuming clock of FPGA produces circuit - Google Patents
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Abstract
一种FPGA内嵌全数字低功耗时钟产生电路,包括数字控制振荡器和控制码产生电路。通过对传统全数字可调振荡器电路的改进设计,将数字控制振荡器中延时链的延时单元改为受控制的三态延时单元,并且在控制码产生电路中加入使能控制码产生电路,将延时链中未使用的三态延时单元关闭,完全消除了振荡器电路的无效动态功耗。采用此结构的低功耗全数字可调震荡器电路,高频输出工作状态的功耗降低至原来的十分之一,并且延时链的工作频率范围越广,改进效果越明显,使技术人员在设计时钟产生电路时能够同时兼顾大范围的可调振荡频率指标和较低的功耗指标。
An all-digital low-power clock generation circuit embedded in FPGA, including a digitally controlled oscillator and a control code generation circuit. Through the improved design of the traditional all-digital adjustable oscillator circuit, the delay unit of the delay chain in the digital control oscillator is changed to a controlled three-state delay unit, and the enable control code is added to the control code generation circuit The generating circuit closes the unused tri-state delay unit in the delay chain, completely eliminating the invalid dynamic power consumption of the oscillator circuit. With this structure of low-power all-digital adjustable oscillator circuit, the power consumption of the high-frequency output working state is reduced to one tenth of the original, and the wider the working frequency range of the delay chain, the more obvious the improvement effect, making the technology When designing a clock generating circuit, personnel can simultaneously take into account a wide range of adjustable oscillation frequency indicators and low power consumption indicators.
Description
技术领域 technical field
本发明涉及一种FPGA内嵌全数字时钟产生电路,特别是一种针对FPGA内嵌应用需求而优化的全数字低功耗时钟产生电路,属于集成电路领域。 The invention relates to an FPGA embedded all-digital clock generation circuit, in particular to an all-digital low-power clock generation circuit optimized for FPGA embedded application requirements, belonging to the field of integrated circuits.
背景技术 Background technique
图1是一个传统的全数字时钟产生电路原理示意图,它主要由延时链110、多路复用器120、控制译码电路130组成,延时链由多个基本的延时单元111构成。延时链110产生不同的时钟延时送至多路复用器120进行选择,多路复用器(120)在选择控制信号(132)的控制下,将所选择的延时后的时钟作为输出(121)送至延时链的输入端,形成反馈振荡器结构;在此过程中,具体的延时值受到复用控制译码产生电路(130)输出的选择控制信号(132)调整,复用控制译码产生电路(130)的输入为外界送入的控制信号(131)。 FIG. 1 is a schematic diagram of a traditional all-digital clock generating circuit, which is mainly composed of a delay chain 110, a multiplexer 120, and a control decoding circuit 130. The delay chain is composed of a plurality of basic delay units 111. The delay chain 110 generates different clock delays and sends them to the multiplexer 120 for selection, and the multiplexer (120) outputs the selected delayed clock under the control of the selection control signal (132) (121) is sent to the input end of the delay chain to form a feedback oscillator structure; in this process, the specific delay value is adjusted by the selection control signal (132) output by the multiplexing control decoding generation circuit (130), and the complex The input of the control decoding generating circuit (130) is the control signal (131) sent from the outside.
使用图1中的传统时钟产生电路有一个明显的缺点,当延时链处(110)于高频工作状态时,所需产生的延时较小,只需要少量延时单元(例如110-1)接入反馈震荡环路,其它延时单元(110-2到110-N)此时都为无效的电路,高频时钟在这些无效电路上也会产生快速的翻转,将产生非常大的动态功耗,动态功耗的增加随着频率上升呈现指数上升的趋势,这大大限制了时钟产生电路的工作频率上限。 There is an obvious disadvantage in using the traditional clock generation circuit in Fig. 1. When the delay chain (110) is in the high-frequency working state, the required delay is relatively small, and only a small number of delay units (such as 110-1 ) into the feedback oscillating loop, other delay units (110-2 to 110-N) are invalid circuits at this time, high-frequency clocks will also produce rapid flips on these invalid circuits, which will produce very large dynamic Power consumption, the increase of dynamic power consumption shows an exponential upward trend with the increase of frequency, which greatly limits the upper limit of the operating frequency of the clock generation circuit.
因而有必要提出一种针对低功耗性能而优化的时钟产生电路结构,以便在功耗可控的情况下获得宽范围的上下限工作频率。 Therefore, it is necessary to propose a clock generation circuit structure optimized for low power consumption, so as to obtain a wide range of upper and lower operating frequencies with controllable power consumption.
发明内容 Contents of the invention
本发明技术解决的问题是:克服现有技术的不足之处,提供了一种全数字的低功耗时钟产生电路结构,解决了传统时钟产生电路在高频工作情况下,动态功耗过大而限制最高工作频率上限的问题。 The problem solved by the technology of the present invention is: to overcome the deficiencies of the prior art, provide an all-digital low-power clock generation circuit structure, and solve the problem of excessive dynamic power consumption of the traditional clock generation circuit under high-frequency operation And the problem of limiting the upper limit of the highest operating frequency.
本发明的技术解决方案是: Technical solution of the present invention is:
一种FPGA内嵌全数字低功耗时钟产生电路,包括:数字控制振荡器和控制码产生电路;数字控制振荡器包括多路复用器、与非门和延时链;控制码产生电路包括使能控制码产生电路和复用控制译码产生电路; An all-digital low-power clock generation circuit embedded in an FPGA, including: a digitally controlled oscillator and a control code generating circuit; the digitally controlled oscillator includes a multiplexer, a NAND gate, and a delay chain; the control code generating circuit includes Enable control code generation circuit and multiplexing control decoding generation circuit;
复用控制译码产生电路接收外部输入的控制信号,生成选择控制信号和移位控制信号,选择控制信号送入多路复用器的选择端,移位控制信号送入使能控制码产生电路的选择端;使能控制码产生电路在所述移位控制信号的控制下,移位产生使能控制码,送入延时链的使能端,关闭无效的延时单元; The multiplexing control decoding generation circuit receives the control signal input from the outside, generates the selection control signal and the shift control signal, the selection control signal is sent to the selection end of the multiplexer, and the shift control signal is sent to the enable control code generation circuit The selection end of the enable control code generation circuit is under the control of the shift control signal, and the shift generates the enable control code, which is sent to the enable end of the delay chain, and the invalid delay unit is closed;
延时链由多个基本的三态延时单元首尾相连组成;延时链的输入端与与非门的输出端相连,延时链的输出端与多路复用器的输入端相连; The delay chain is composed of a plurality of basic three-state delay units connected end to end; the input end of the delay chain is connected with the output end of the NAND gate, and the output end of the delay chain is connected with the input end of the multiplexer;
多路复用器接收来自延时链的各相位时钟,同时接收复用控制译码产生电路的选择控制信号,将选定的延迟时钟从时钟输出端输出,作为所述时钟产生电路的输出,同时,所述选定的延迟时钟还反馈到与非门的一个输入端,与非门的另一个输入端接受外部输入的复位信号; The multiplexer receives each phase clock from the delay chain, and simultaneously receives the selection control signal of the multiplexing control decoding generation circuit, and outputs the selected delayed clock from the clock output terminal as the output of the clock generation circuit, At the same time, the selected delayed clock is also fed back to one input terminal of the NAND gate, and the other input terminal of the NAND gate accepts an externally input reset signal;
所述使能控制码产生电路包括多个串联连接的移位寄存器单元,在移位控制信号的控制下移动1和0序列,生成数字使能控制码。 The enable control code generation circuit includes a plurality of shift register units connected in series, and shifts the sequence of 1 and 0 under the control of the shift control signal to generate a digital enable control code.
所述移位寄存器单元包括二选一复用器MUX、存储单元SRAM、第一传输控制管、第二传输控制管和反向器; The shift register unit includes a two-to-one multiplexer MUX, a storage unit SRAM, a first transmission control tube, a second transmission control tube and an inverter;
二选一复用器MUX的两个输入端分别连接前一个移位寄存器单元的输出和后一个移位寄存器单元的输出,二选一复用器MUX的输出送入存储单元SRAM中,存储单元SRAM的输出通过第一传输控制管送入反向器进行反向处理,之后再通过第二传输控制管输出至前一个移位寄存器单元中二选一复用器MUX的输入和后一个移位寄存器单元中二选一复用器MUX的输入;反向器的输出端引出作为所述延时链中对应延时单元使能端的输入。 The two input terminals of the two-to-one multiplexer MUX are respectively connected to the output of the previous shift register unit and the output of the next shift register unit, and the output of the two-to-one multiplexer MUX is sent to the storage unit SRAM, and the storage unit The output of the SRAM is sent to the inverter through the first transmission control tube for reverse processing, and then output to the input of the two-choice multiplexer MUX in the previous shift register unit and the next shift through the second transmission control tube The input of the one-of-two multiplexer MUX in the register unit; the output terminal of the inverter is taken as the input of the enabling terminal of the corresponding delay unit in the delay chain.
所述第一传输控制管和第二传输控制管采用NMOS晶体管或者PMOS晶体管。 The first transmission control transistor and the second transmission control transistor use NMOS transistors or PMOS transistors.
所述延时链包括串联在一起的多个三态延时单元,所述三态延时单元包括反向器、等效电容和与非门,外部输入的时钟信号经过反向器反向后送入与非门的一个输入端,同时,反向器的输出端还通过等效电容接地,与非门的另一个输入端接收使能控制码产生电路输出的使能控制码。 The delay chain includes a plurality of three-state delay units connected in series, and the three-state delay unit includes an inverter, an equivalent capacitor and a NAND gate, and the externally input clock signal is reversed by the inverter It is fed into one input terminal of the NAND gate, and at the same time, the output terminal of the inverter is also grounded through an equivalent capacitance, and the other input terminal of the NAND gate receives the enable control code output by the enable control code generating circuit.
本发明与现有技术相比的有益效果是: The beneficial effect of the present invention compared with prior art is:
(1)本发明的全数字低功耗时钟产生电路,能大幅降低时钟产生电路的振荡器在高频工作情况下的动态功耗,相对于传统结构的时钟产生电路,高频动态功耗可低至十分之一; (1) The all-digital low-power clock generation circuit of the present invention can greatly reduce the dynamic power consumption of the oscillator of the clock generation circuit under high-frequency operation. Compared with the clock generation circuit with traditional structure, the high-frequency dynamic power consumption can be reduced as low as one-tenth;
(2)本发明所述的时钟产生电路可以配以鉴相器、分频器和算法控制电路构成低功耗全数字锁相环,采用本发明所述的时钟产生电路结构11111111111111的全数字锁相环,不需要过多考虑高频情况下的动态功耗,也不需要为其配备大电流能力的电源网络,为芯片设计节省了面积。 (2) The clock generating circuit of the present invention can be equipped with a phase detector, a frequency divider and an algorithm control circuit to form a low-power all-digital phase-locked loop, and a full-digital lock using the clock generating circuit structure 11111111111111 The phase loop does not need to consider too much dynamic power consumption under high frequency conditions, nor does it need to be equipped with a power network with high current capability, which saves area for chip design.
附图说明 Description of drawings
图1是传统结构的时钟产生电路示意图; Fig. 1 is the schematic diagram of the clock generation circuit of traditional structure;
图2是本发明全数字低功耗时钟产生电路示意图; Fig. 2 is a schematic diagram of an all-digital low-power clock generating circuit of the present invention;
图3是带有控制端的延时单元结构图; Fig. 3 is a structural diagram of a delay unit with a control terminal;
图4是使能控制码产生电路模块结构图; Fig. 4 is a structural diagram of the circuit module for enabling control code generation;
图5是移位寄存器单元的详细结构示意图; Fig. 5 is a detailed structural schematic diagram of a shift register unit;
图6为移位寄存器单元的工作时序示意图。 FIG. 6 is a schematic diagram of the working sequence of the shift register unit.
具体实施方式 detailed description
本发明是一种FPGA内嵌的数字低功耗时钟产生电路,包括:数字控制振荡器200和控制码产生电路300。具体来讲,数字控制振荡器200由多路复用器220、与非门240和延时链210组成;控制码产生电路300包括使能控制码产生电路340和复用控制译码产生电路330。在图2中可见这些电路模块之间的关系: The present invention is a digital low-power clock generation circuit embedded in FPGA, which includes: a digital control oscillator 200 and a control code generation circuit 300 . Specifically, the digitally controlled oscillator 200 is composed of a multiplexer 220, a NAND gate 240 and a delay chain 210; the control code generation circuit 300 includes an enable control code generation circuit 340 and a multiplexing control decoding generation circuit 330 . The relationship between these circuit blocks can be seen in Figure 2:
复用控制译码产生电路接收外部输入的控制信号,生成选择控制信号和移位控制信号,选择控制信号送入多路复用器的选择端,移位控制信号送入使能控制码产生电路的选择端;使能控制码产生电路在所述移位控制信号的控制下,移位产生使能控制码,送入延时链的使能端,关闭无效的延时单元; The multiplexing control decoding generation circuit receives the control signal input from the outside, generates the selection control signal and the shift control signal, the selection control signal is sent to the selection end of the multiplexer, and the shift control signal is sent to the enable control code generation circuit The selection end of the enable control code generation circuit is under the control of the shift control signal, and the shift generates the enable control code, which is sent to the enable end of the delay chain, and the invalid delay unit is closed;
延时链由多个基本的三态延时单元首尾相连组成;延时链的输入端与与非门的输出端相连,延时链的输出端与多路复用器的输入端相连; The delay chain is composed of a plurality of basic three-state delay units connected end to end; the input end of the delay chain is connected with the output end of the NAND gate, and the output end of the delay chain is connected with the input end of the multiplexer;
多路复用器接收来自延时链的各相位时钟,同时接收复用控制译码产生电路的选择控制信号,将选定的延迟时钟从时钟输出端输出,作为所述时钟产生电路的输出,同时,所述选定的延迟时钟还反馈到与非门的一个输入端,与非门的另一个输入端接受外部输入的复位信号。 The multiplexer receives each phase clock from the delay chain, and simultaneously receives the selection control signal of the multiplexing control decoding generation circuit, and outputs the selected delayed clock from the clock output terminal as the output of the clock generation circuit, At the same time, the selected delayed clock is also fed back to one input terminal of the NAND gate, and the other input terminal of the NAND gate receives an externally input reset signal.
移位寄存器单元包括二选一复用器MUX、存储单元SRAM、第一传输控制管、第二传输控制管和反向器; The shift register unit includes a two-to-one multiplexer MUX, a storage unit SRAM, a first transmission control tube, a second transmission control tube and an inverter;
二选一复用器MUX的两个输入端分别连接前一个移位寄存器单元的输出和后一个移位寄存器单元的输出,二选一复用器MUX的输出送入存储单元SRAM中,存储单元SRAM的输出通过第一传输控制管送入反向器进行反向处理,之后再通过第二传输控制管输出至前一个移位寄存器单元中二选一复用器MUX的输入和后一个移位寄存器单元中二选一复用器MUX的输入;反向器的输出端引出作为所述延时链中对应延时单元使能端的输入。 The two input terminals of the two-to-one multiplexer MUX are respectively connected to the output of the previous shift register unit and the output of the next shift register unit, and the output of the two-to-one multiplexer MUX is sent to the storage unit SRAM, and the storage unit The output of the SRAM is sent to the inverter through the first transmission control tube for reverse processing, and then output to the input of the two-choice multiplexer MUX in the previous shift register unit and the next shift through the second transmission control tube The input of the one-of-two multiplexer MUX in the register unit; the output terminal of the inverter is taken as the input of the enabling terminal of the corresponding delay unit in the delay chain.
延时链包括串联在一起的多个三态延时单元,所述三态延时单元包括反向器、等效电容和与非门,外部输入的时钟信号经过反向器反向后送入与非门的一个输入端,同时,反向器的输出端还通过等效电容接地,与非门的另一个输入端接收使能控制码产生电路输出的使能控制码。 The delay chain includes a plurality of three-state delay units connected in series. The three-state delay units include inverters, equivalent capacitors and NAND gates. The externally input clock signal is sent to One input terminal of the NAND gate, meanwhile, the output terminal of the inverter is also grounded through an equivalent capacitor, and the other input terminal of the NAND gate receives the enable control code output by the enable control code generating circuit.
延时链200在复位端211失效之后对时钟进行延时,N个延时单元可以产生N个不同的延时,在选择控制信号232的控制下,通过多路复用器220选出一个合适的延时时钟送至时钟输出端221,同时也反馈到延时链210作为时钟输入,这样形成一个闭环震荡的结构,即数字控制振荡器200,它可以通过改变控制码调整不同的延时值以产生不同频率的震荡时钟。 The delay chain 200 delays the clock after the reset terminal 211 fails. N delay units can generate N different delays. Under the control of the selection control signal 232, a suitable one is selected through the multiplexer 220. The delayed clock is sent to the clock output terminal 221, and also fed back to the delay chain 210 as the clock input, thus forming a closed-loop oscillation structure, that is, the digitally controlled oscillator 200, which can adjust different delay values by changing the control code to generate oscillating clocks of different frequencies.
本发明中对电路架构进行的改进包括,采用可关闭的延时单元和使能控制码进行动态调整,在产生高频时钟时阻断了绝大多数处于非工作状态延时单元的时钟翻转,以达到降低动态功耗的目的,以一条500级的延时链为例,当产生的时钟处于延时链工作频率范围的上限时,所用到的延时单元不超过25个,其它475个延时单元都在高频时钟的驱动下进行无效的动作,产生超过90%的动态功耗。 The improvement of the circuit architecture in the present invention includes the use of a turn-off delay unit and enabling control codes for dynamic adjustment, blocking the clock inversion of most of the delay units in the non-working state when generating high-frequency clocks, To achieve the purpose of reducing dynamic power consumption, take a 500-level delay chain as an example. When the generated clock is at the upper limit of the operating frequency range of the delay chain, no more than 25 delay units are used, and the other 475 delay units The time units are driven by high-frequency clocks to perform invalid actions, resulting in more than 90% of dynamic power consumption.
为了实现本发明的电路架构改进,首先对传统的延时单元进行了改进,加入了使能控制端,如图3所示。本发明带有使能控制端的延时单元500主要包括反向器、等效电容和与非门,统称之为延时器件510,除了具有时钟输入511和时钟延时输出512之外,还有使能控制端513,当使能控制端513输入高电平时,延时单元500处于激活状态,时钟延时输出端512跟随时钟输入511进行延时输出,当使能控制端513输入低电平时,延时单元关闭,时钟延时输出512恒为高电平,节省后续级联的延时单元动态功耗。 In order to realize the improvement of the circuit structure of the present invention, the traditional delay unit is firstly improved, and an enable control terminal is added, as shown in FIG. 3 . In the present invention, the delay unit 500 with an enabling control terminal mainly includes an inverter, an equivalent capacitor and a NAND gate, collectively referred to as a delay device 510, in addition to a clock input 511 and a clock delay output 512, there are Enable the control terminal 513, when the enable control terminal 513 inputs a high level, the delay unit 500 is in an active state, the clock delay output terminal 512 follows the clock input 511 for delayed output, when the enable control terminal 513 inputs a low level , the delay unit is turned off, and the clock delay output 512 is always at a high level, saving the dynamic power consumption of subsequent cascaded delay units.
为了实现对本发明数字控制振荡器200的控制,在传统设计的基础上改进了控制码产生电路300,复用控制译码产生电路330仍然用来产生对多路复用器220的选择控制信号232,在此基础上另外设计了使能控制码产生电路340,在移位控制信号333的控制下,产生N比特的使能控制码动态关闭无效的延时单元。 In order to realize the control of the digitally controlled oscillator 200 of the present invention, the control code generation circuit 300 is improved on the basis of the traditional design, and the multiplexing control decoding generation circuit 330 is still used to generate the selection control signal 232 to the multiplexer 220 On this basis, an enabling control code generation circuit 340 is additionally designed, under the control of the shift control signal 333, an N-bit enabling control code is generated to dynamically disable invalid delay units.
使能控制码产生电路340被用来产生一个N比特的1或0组成的序列,电路结构相当于左右移位寄存器链,如果将使能控制码中1和0的分界点定义为调节点,那么在调节点左侧(含调节点)使能控制码全为1,在调节点右侧全为0,根据移位控制信号333的控制来动态调整调节点的位置。移位控制信号333包括加减信号341、移位控制信号1和移位控制信号2,在3个信号的共同控制下,将1和0组成的序列进行适当左右移位,移位过程中左侧由1补齐,右侧由0补齐。例如,在起始时刻N比特的控制信号可能为11111111111……110000,经过多次的动态调整之后变为11100000000……000000,在这一过程中,控制信号中“0”对应的延时单元将被关闭,达到降低动态功耗的目的。 The enabling control code generation circuit 340 is used to generate a sequence composed of N bits of 1 or 0, and the circuit structure is equivalent to a chain of left and right shift registers. If the boundary point between 1 and 0 in the enabling control code is defined as the adjustment point, Then the enabling control codes on the left side of the adjustment point (including the adjustment point) are all 1, and on the right side of the adjustment point are all 0, and the position of the adjustment point is dynamically adjusted according to the control of the shift control signal 333 . The shift control signal 333 includes an addition and subtraction signal 341, a shift control signal 1 and a shift control signal 2. Under the common control of the three signals, the sequence composed of 1 and 0 is properly shifted left and right, and the left and right shifts are performed during the shift process. The side is padded with 1s, and the right side is padded with 0s. For example, the N-bit control signal at the initial moment may be 11111111111...110000, and after multiple dynamic adjustments, it becomes 11100000000...000000. In this process, the delay unit corresponding to "0" in the control signal will be is turned off to achieve the purpose of reducing dynamic power consumption.
本发明中的使能控制码产生电路340由N个移位寄存器单元340-1、340-2至340-N组成,如图4所示。 The enabling control code generating circuit 340 in the present invention is composed of N shift register units 340-1, 340-2 to 340-N, as shown in FIG. 4 .
图5是移位寄存器单元的详细结构示意图,包括二选一复用器MUX345、存储单元SRAM346、传输控制管1(第一传输控制管347)、传输控制管2(第二传输控制管349)和反向器348,传输控制管1和传输控制管2采用PMOS管或者NMOS管。二选一复用器MUX345可在加减信号(341)的控制下接收来自前一单元的输出603或后一单元的输出604,作为移位输入,同时也可将存储单元SRAM346内的值送至前一单元的mux的一个输入端601或后一单元的mux的另一个输入端602。 Figure 5 is a schematic diagram of the detailed structure of the shift register unit, including a two-to-one multiplexer MUX345, a storage unit SRAM346, a transmission control tube 1 (the first transmission control tube 347), and a transmission control tube 2 (the second transmission control tube 349) And the inverter 348, the transmission control tube 1 and the transmission control tube 2 adopt PMOS tubes or NMOS tubes. One-to-two multiplexer MUX345 can receive the output 603 from the previous unit or the output 604 from the next unit under the control of the addition and subtraction signal (341), as a shift input, and can also send the value in the storage unit SRAM346 to To one input 601 of the mux of the preceding unit or the other input 602 of the mux of the following unit.
图6是移位寄存器单元的工作时序示意图,在进行移位操作时,每个时钟周期的上升沿,移位控制信号1首先降为低电平,关闭传输控制管1,将存储单元SRAM内的值依靠晶体管电容暂时存在动态存储节点A(650)内,紧接着移位控制信号2升为高电平,开启传输控制管2,将本单元存储的值写入下一单元(具体送入前一单元还是后一单元,要受加减信号341来控制),再依次关闭传输控制管2,开启传输控制管1,将使能控制码344-m端的输出值更新,完成一次数据移位。 Figure 6 is a schematic diagram of the working sequence of the shift register unit. During the shift operation, on the rising edge of each clock cycle, the shift control signal 1 is first reduced to a low level, and the transmission control tube 1 is turned off, and the storage unit SRAM The value depends on the transistor capacitance and temporarily stores in the dynamic storage node A (650), and then the shift control signal 2 rises to high level, turns on the transmission control tube 2, and writes the value stored in this unit into the next unit (specifically sent to The previous unit or the latter unit is controlled by the addition and subtraction signal 341), then turn off the transmission control tube 2 in turn, turn on the transmission control tube 1, update the output value of the enable control code 344-m, and complete a data shift .
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CN112202425A (en) * | 2020-09-25 | 2021-01-08 | 杭州加速科技有限公司 | Clock generation unit in FPGA chip |
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