CN103916102B - A kind of embedded digital low power consuming clock of FPGA produces circuit - Google Patents
A kind of embedded digital low power consuming clock of FPGA produces circuit Download PDFInfo
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- CN103916102B CN103916102B CN201410086316.7A CN201410086316A CN103916102B CN 103916102 B CN103916102 B CN 103916102B CN 201410086316 A CN201410086316 A CN 201410086316A CN 103916102 B CN103916102 B CN 103916102B
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Abstract
A kind of embedded digital low power consuming clock of FPGA produces circuit, produces circuit including numerically-controlled oscillator and control code.By the Curve guide impeller to traditional digital tunable oscillator circuit, change the delay unit of time delay chain in numerically-controlled oscillator in check tri-state delay unit, and produce circuit adds in control code and enable control code generation circuit, untapped tri-state delay unit in time delay chain is closed, completely eliminates the invalid dynamic power consumption of pierce circuit.Adopt the digital adjustable oscillator circuit of low-power consumption of this structure, the lower power consumption of high frequency output duty is to original 1/10th, and the operating frequency range of time delay chain is more wide, improvement effect is more obvious, enables technical staff to take into account large-scale oscillation frequency adjustable index and relatively low power consumption index when designing clock generation circuit simultaneously.
Description
Technical field
The present invention relates to a kind of embedded digital clock generation circuit of FPGA, particularly a kind of digital low power consuming clock optimized for the embedded application demand of FPGA produces circuit, belongs to integrated circuit fields.
Background technology
Fig. 1 is a traditional digital clock generation circuit principle schematic, and it is mainly made up of time delay chain 110, multiplexer 120, control decoding circuit 130, and time delay chain is made up of multiple basic delay units 111.Time delay chain 110 produces different clock delays and delivers to multiplexer 120 and select, multiplexer (120) is under the control selecting control signal (132), clock after selected time delay is delivered to as output (121) input of time delay chain, forms back-coupled generator structure；In the process, concrete delay value is subject to multiplexing and controls selection control signal (132) adjustment that decoding generation circuit (130) exports, and it is the extraneous control signal (131) sent into that multiplexing control decoding produces inputting of circuit (130).
Use the conventional clock in Fig. 1 to produce circuit and have an obvious shortcoming, when time delay chain place (110) are in high-frequency work state, the required time delay produced is less, have only to a small amount of delay unit (such as 110-1) and access feedback concussion loop, other delay unit (110-2 to 110-N) is all now invalid circuit, high frequency clock also can produce quick upset on these idle circuits, very big dynamic power consumption will be produced, increasing of dynamic power consumption presents, along with frequency rises, the trend that index rises, and which greatly limits the upper operational frequency limit of clock generation circuit.
Thus it is necessary to propose a kind of clock generation circuit structure optimized for low power capabilities, in order to the bound operating frequency of wide scope is obtained when power consumption is controlled.
Summary of the invention
The problem that the technology of the present invention solves is: overcome the deficiencies in the prior art part, provide a kind of digital low power consuming clock and produce circuit structure, solving conventional clock and produce circuit in high-frequency work situation, dynamic power consumption is excessive and the problem that limits the maximum operating frequency upper limit.
The technical solution of the present invention is:
A kind of embedded digital low power consuming clock of FPGA produces circuit, including: numerically-controlled oscillator and control code produce circuit；Numerically-controlled oscillator includes multiplexer, NAND gate and time delay chain；Control code generation circuit includes enabling control code and produces circuit and multiplexing control decoding generation circuit；
Multiplexing controls decoding and produces the control signal of circuit reception externally input, generates and selects control signal and shift control signal, selects control signal to send into the selection end of multiplexer, and shift control signal feeding enables control code and produces the selection end of circuit；Enabling control code and produce circuit under the control of described shift control signal, displacement produces to enable control code, sends into the Enable Pin of time delay chain, closes invalid delay unit；
Time delay chain is joined end to end by multiple basic tri-state delay units and forms；The input of time delay chain is connected with the outfan of NAND gate, and the outfan of time delay chain is connected with the input of multiplexer；
Multiplexer receives each phase clock from time delay chain, receive multiplexing simultaneously and control the selection control signal of decoding generation circuit, selected delayed clock is exported from output terminal of clock, output as described clock generation circuit, simultaneously, described selected delayed clock also feeds back to an input of NAND gate, and another input of NAND gate accepts the reset signal of externally input；
Described enable control code produces circuit and includes multiple shift register cell being connected in series, mobile 1 and 0 sequence under the control of shift control signal, generates numeral and enables control code.
Described shift register cell includes alternative multiplexer MUX, memory element SRAM, the first transmission controls pipe, the second transmission controls pipe and reverser；
Two inputs of alternative multiplexer MUX connect the output of previous shift register cell and the output of later shift register cell respectively, the output of alternative multiplexer MUX is sent in memory element SRAM, the output of memory element SRAM controls pipe feeding reverser by the first transmission and carries out reverse process, afterwards again through the second transmission control pipe output to the input of alternative multiplexer MUX and the input of alternative multiplexer MUX in later shift register cell in previous shift register cell；The input as delay unit Enable Pin corresponding in described time delay chain drawn by the outfan of reverser.
Described first transmission controls pipe and the second transmission controls pipe and adopts nmos pass transistor or PMOS transistor.
Described time delay chain includes the multiple tri-state delay units being cascaded, described tri-state delay unit includes reverser, equivalent capacity and NAND gate, the clock signal of externally input sends into an input of NAND gate after reverser is reverse, simultaneously, the outfan of reverser is also by equivalent capacity ground connection, and another input of NAND gate receives the enable control code enabling control code generation circuit output.
The present invention compared with prior art provides the benefit that:
(1) the digital low power consuming clock of the present invention produces circuit, and the agitator of clock generation circuit dynamic power consumption under high-frequency work situation can be greatly reduced, and relative to the clock generation circuit of traditional structure, high frequency dynamic power consumption can be low to moderate 1/10th；
(2) clock generation circuit of the present invention can be equipped with phase discriminator, frequency divider and algorithm controls circuit composition low-power consumption all-digital phase-locked loop, adopt the all-digital phase-locked loop of clock generation circuit structure 11111111111111 of the present invention, need not too much consider the dynamic power consumption under high frequency situations, also without the electric power network being equipped with big current capacity for it, design for chip and save area.
Accompanying drawing explanation
Fig. 1 is the clock generation circuit schematic diagram of traditional structure；
Fig. 2 is that the digital low power consuming clock of the present invention produces circuit diagram；
Fig. 3 is with the delay unit structure chart controlling end；
Fig. 4 enables control code to produce circuit modular structure figure；
Fig. 5 is the detailed construction schematic diagram of shift register cell；
Fig. 6 is the work schedule schematic diagram of shift register cell.
Detailed description of the invention
The digital low power consuming clock that the present invention is embedded for a kind of FPGA produces circuit, including: numerically-controlled oscillator 200 and control code produce circuit 300.Specifically, numerically-controlled oscillator 200 is made up of multiplexer 220, NAND gate 240 and time delay chain 210；Control code generation circuit 300 includes enabling control code and produces circuit 340 and multiplexing control decoding generation circuit 330.Relation between these circuit modules visible in fig. 2:
Multiplexing controls decoding and produces the control signal of circuit reception externally input, generates and selects control signal and shift control signal, selects control signal to send into the selection end of multiplexer, and shift control signal feeding enables control code and produces the selection end of circuit；Enabling control code and produce circuit under the control of described shift control signal, displacement produces to enable control code, sends into the Enable Pin of time delay chain, closes invalid delay unit；
Time delay chain is joined end to end by multiple basic tri-state delay units and forms；The input of time delay chain is connected with the outfan of NAND gate, and the outfan of time delay chain is connected with the input of multiplexer；
Multiplexer receives each phase clock from time delay chain, receive multiplexing simultaneously and control the selection control signal of decoding generation circuit, selected delayed clock is exported from output terminal of clock, output as described clock generation circuit, simultaneously, described selected delayed clock also feeds back to an input of NAND gate, and another input of NAND gate accepts the reset signal of externally input.
Shift register cell includes alternative multiplexer MUX, memory element SRAM, the first transmission controls pipe, the second transmission controls pipe and reverser；
Two inputs of alternative multiplexer MUX connect the output of previous shift register cell and the output of later shift register cell respectively, the output of alternative multiplexer MUX is sent in memory element SRAM, the output of memory element SRAM controls pipe feeding reverser by the first transmission and carries out reverse process, afterwards again through the second transmission control pipe output to the input of alternative multiplexer MUX and the input of alternative multiplexer MUX in later shift register cell in previous shift register cell；The input as delay unit Enable Pin corresponding in described time delay chain drawn by the outfan of reverser.
Time delay chain includes the multiple tri-state delay units being cascaded, described tri-state delay unit includes reverser, equivalent capacity and NAND gate, the clock signal of externally input sends into an input of NAND gate after reverser is reverse, simultaneously, the outfan of reverser is also by equivalent capacity ground connection, and another input of NAND gate receives the enable control code enabling control code generation circuit output.
Clock was carried out time delay by time delay chain 200 after reset terminal 211 loses efficacy, N number of delay unit can produce N number of different time delay, under the control selecting control signal 232, select a suitable delay clock by multiplexer 220 and deliver to output terminal of clock 221, also feed back to time delay chain 210 to input as clock simultaneously, so form the structure of a closed loop concussion, i.e. numerically-controlled oscillator 200, it can pass through to change control code and adjust different delay values to produce the concussion clock of different frequency.
The improvement in the present invention, circuit framework carried out includes, closable delay unit and enable control code is adopted dynamically to adjust, most clock upset being in off working state delay unit has been blocked when producing high frequency clock, to reduce the purpose of dynamic power consumption, for the time delay chain of 500 grades, when the clock produced is in the upper limit of time delay chain operating frequency range, used delay unit is less than 25, other 475 delay units all carry out invalid action under the driving of high frequency clock, produce the dynamic power consumption more than 90%.
Circuit framework in order to realize the present invention improves, and first traditional delay unit has been improved, and adds enable and controls end, as shown in Figure 3.The present invention mainly includes reverser, equivalent capacity and NAND gate with enabling the delay unit 500 controlling end, system is referred to as time delay device 510, except there is clock input 511 and clock delay output 512, also have to enable and control end 513, when enabling control end 513 input high level, delay unit 500 is active, clock delay outfan 512 is followed clock input 511 and is carried out time delay output, when enabling control end 513 input low level, delay unit is closed, clock delay output 512 perseverances are high level, save the delay unit dynamic power consumption of subsequent cascaded.
In order to realize the control to numerically-controlled oscillator 200 of the present invention, the basis of traditional design improves control code and produces circuit 300, multiplexing controls decoding and produces circuit 330 still for producing the selection control signal 232 to multiplexer 220, additionally devise enable control code on this basis and produce circuit 340, under the control of shift control signal 333, the enable control code producing N-bit dynamically closes invalid delay unit.
Enable control code and produce the sequence that circuit 340 is used to produce 1 or 0 composition of a N-bit, circuit structure is equivalent to left-right shift register chain, if being defined as point of adjustment by enabling the separation of 1 and 0 in control code, so enabling control code on the left of point of adjustment (containing point of adjustment) is 1 entirely, it is 0 entirely on the right side of point of adjustment, dynamically adjusts the position of point of adjustment according to the control of shift control signal 333.Shift control signal 333 includes up-down signal 341, shift control signal 1 and shift control signal 2, under the co-controlling of 3 signals, the sequence that 1 and 0 forms is carried out suitable left and right sidesing shifting, and in shifting process, left side is by 1 polishing, and right side is by 0 polishing.Such as, control signal at initial time N-bit is likely 11111111111 ... 110000, becomes 11100000000 ... 000000, in this course after dynamically adjustment repeatedly, the delay unit that in control signal, " 0 " is corresponding will be closed, and reduce the purpose of dynamic power consumption.
Enable control code in the present invention produces circuit 340 and is made up of N number of shift register cell 340-1,340-2 to 340-N, as shown in Figure 4.
Fig. 5 is the detailed construction schematic diagram of shift register cell, including alternative multiplexer MUX345, memory element SRAM346, transmission control pipe 1(first transmit control pipe 347), transmission control pipe 2(second transmit control pipe 349) and reverser 348, transmission controls pipe 1 and transmission control pipe 2 adopts PMOS or NMOS tube.Alternative multiplexer MUX345 can receive the output 604 of the output 603 from previous unit or a rear unit under the control of up-down signal (341), as displacement input, the value in memory element SRAM346 also can be delivered to an input 601 of the mux of previous unit or another input 602 of the mux of a rear unit simultaneously.
Fig. 6 is the work schedule schematic diagram of shift register cell, when carrying out shifting function, the rising edge of each clock cycle, first shift control signal 1 reduces to low level, closing transmission controls pipe 1, transistor capacitance is relied on to be temporarily present dynamic memory node A(650 the value in memory element SRAM) in, and then shift control signal 2 is upgraded to high level, open transmission and control pipe 2, value write next unit (the previous unit of concrete feeding or the rear unit that this unit is stored, up-down signal 341 is subject to control), closing transmission controls pipe 2 successively again, open transmission and control pipe 1, the output valve enabling control code 344-m end is updated, complete a secondary data displacement.
Claims (4)
1. the embedded digital low power consuming clock of FPGA produces circuit, it is characterised in that including: numerically-controlled oscillator and control code produce circuit；Numerically-controlled oscillator includes multiplexer, NAND gate and time delay chain；Control code generation circuit includes enabling control code and produces circuit and multiplexing control decoding generation circuit；
Multiplexing controls decoding and produces the control signal of circuit reception externally input, generates and selects control signal and shift control signal, selects control signal to send into the selection end of multiplexer, and shift control signal feeding enables control code and produces the selection end of circuit；Enabling control code and produce circuit under the control of described shift control signal, displacement produces to enable control code, sends into the Enable Pin of time delay chain, closes invalid delay unit；
Time delay chain includes the multiple tri-state delay units being cascaded；The input of time delay chain is connected with the outfan of NAND gate, and the outfan of time delay chain is connected with the input of multiplexer；
Multiplexer receives each phase clock from time delay chain, receive multiplexing simultaneously and control the selection control signal of decoding generation circuit, selected delayed clock is exported from output terminal of clock, output as described clock generation circuit, simultaneously, described selected delayed clock also feeds back to an input of NAND gate, and another input of NAND gate accepts the reset signal of externally input；
Described tri-state delay unit includes reverser, equivalent capacity and NAND gate, the clock signal of externally input sends into an input of NAND gate after reverser is reverse, simultaneously, the outfan of reverser is also by equivalent capacity ground connection, and another input of NAND gate receives the enable control code enabling control code generation circuit output.
2. a kind of embedded digital low power consuming clock of FPGA according to claim 1 produces circuit, it is characterized in that: described enable control code produces circuit and includes multiple shift register cell being connected in series, mobile 1 and 0 sequence under the control of shift control signal, generates numeral and enables control code.
3. a kind of embedded digital low power consuming clock of FPGA according to claim 2 produces circuit, it is characterised in that: described shift register cell includes alternative multiplexer MUX, memory element SRAM, the first transmission controls pipe, the second transmission controls pipe and reverser；
Two inputs of alternative multiplexer MUX connect the output of previous shift register cell and the output of later shift register cell respectively, the output of alternative multiplexer MUX is sent in memory element SRAM, the output of memory element SRAM controls pipe feeding reverser by the first transmission and carries out reverse process, afterwards again through the second transmission control pipe output to the input of alternative multiplexer MUX and the input of alternative multiplexer MUX in later shift register cell in previous shift register cell；The input as delay unit Enable Pin corresponding in described time delay chain drawn by the outfan of reverser.
4. a kind of embedded digital low power consuming clock of FPGA according to claim 3 produces circuit, it is characterised in that: described first transmission controls pipe and the second transmission controls pipe and adopts nmos pass transistor or PMOS transistor.
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| CN112272016A (en) * | 2015-03-17 | 2021-01-26 | 华为技术有限公司 | Mixed signal integrated circuit |
| CN106411296A (en) * | 2015-07-30 | 2017-02-15 | 深圳市中兴微电子技术有限公司 | Clock time-delay circuit |
| CN106405387A (en) * | 2016-08-31 | 2017-02-15 | 成都华微电子科技有限公司 | FPGA internal delay measurement method |
| CN106612111B (en) * | 2016-12-30 | 2020-05-08 | 深圳市志奋领科技有限公司 | High-precision delay clock calibration system and method |
| CN106887245A (en) * | 2017-01-04 | 2017-06-23 | 上海华虹宏力半导体制造有限公司 | Charge pump clock controls circuit and method |
| CN107609527B (en) * | 2017-09-21 | 2020-10-27 | 重庆纳尔利科技有限公司 | Low-power-consumption capacitance detection device for fingerprint identification |
| CN109088619B (en) * | 2018-07-24 | 2022-06-28 | 北京时代民芯科技有限公司 | Method and circuit for generating enable signal |
| CN110795899B (en) * | 2019-11-07 | 2023-11-28 | 飞腾信息技术有限公司 | Chip power-on control device |
| CN112202425A (en) * | 2020-09-25 | 2021-01-08 | 杭州加速科技有限公司 | Clock generation unit in FPGA chip |
| CN112929023A (en) * | 2021-01-25 | 2021-06-08 | 深圳市南方硅谷半导体有限公司 | Wide-range ring oscillator |
| CN115250113A (en) * | 2022-09-20 | 2022-10-28 | 旋智电子科技（上海）有限公司 | Delay circuit and control method thereof |
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| CN101478308A (en) * | 2009-01-13 | 2009-07-08 | 北京时代民芯科技有限公司 | Configurable frequency synthesizer circuit based on time-delay lock loop |
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| US6944091B2 (en) * | 2002-07-10 | 2005-09-13 | Samsung Electronics Co., Ltd. | Latency control circuit and method of latency control |
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| CN101478308A (en) * | 2009-01-13 | 2009-07-08 | 北京时代民芯科技有限公司 | Configurable frequency synthesizer circuit based on time-delay lock loop |
| CN102158208A (en) * | 2011-04-02 | 2011-08-17 | 东南大学 | Whole-course adjustable digital pulse width modulator based on oscillation ring circuit |
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