CN106887245A - Charge pump clock controls circuit and method - Google Patents
Charge pump clock controls circuit and method Download PDFInfo
- Publication number
- CN106887245A CN106887245A CN201710003928.9A CN201710003928A CN106887245A CN 106887245 A CN106887245 A CN 106887245A CN 201710003928 A CN201710003928 A CN 201710003928A CN 106887245 A CN106887245 A CN 106887245A
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- clock
- charge pump
- circuit
- frequency
- signal
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of charge pump clock control circuit, the clock signal of charge pump is provided by the output end of clock generation circuit；The input of clock generation circuit is connected with high frequency and enables signal and export clock signal in output end；High frequency enables the input that signal is input to clock generation circuit by clock control circuit, when high frequency enable signal carries out signal switching, clock control circuit makes the frequency of clock signal consecutive variations between first frequency and second frequency by the curtage of consecutive variations, so that the power consumption consecutive variations of charge pump consumption, so as to prevent the output voltage for providing the LDO circuit of operating voltage for charge pump from producing overshoot.The invention also discloses a kind of charge pump clock control method.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacture field, more particularly to a kind of charge pump clock control circuit.This
Invention further relates to a kind of charge pump clock control method.
Background technology
As shown in figure 1, being the application schematic diagram of existing low pressure difference linear voltage regulator (LDO) circuit；Existing LDO circuit 1
Output voltage V_LDO is connected to flash memory module (Flash IP) 2, and flash memory module 2 includes flash memory cell array 3 and peripheral circuit
4, peripheral circuit 4 include charge pump (Charge Pump) 5 and detection amplifier (Sense Amplifier, SA) 6 and other
Control logic circuit 6.
As shown in Fig. 2 being existing LDO circuit；Existing LDO circuit includes difference amplifier, a PMOS PM2 and has electricity
The resistance string of resistance R0 and R1 compositions, the input connection reference voltage VREF of difference amplifier, the connection of another input
By resistance string to the feedback voltage V FD that is formed after LDO output voltage V_LDO partial pressures, the drain electrode output LDO outputs of PMOS PM2
Source electrode connection the voltage VCC, voltage VCC of voltage V_LDO, PMOS PM2 do the input voltage of the main body circuit of LDO circuit.Fig. 1
Shown in difference amplifier include the difference amplifier main body circuit that is made up of NMOS tube NM0 and NM1, by PMOS PM0 and
The active pull-up circuit of PM1 compositions, and the mirror image circuit being made up of NMOS tube NMirr0 and NMirr1, NMOS tube NMirr0's
Drain electrode input current source IB, NMOS tube NMirr1 provide tail current；Benefit is also in series between the grid of PMOS PM2 and drain electrode
Repay resistance Rc and compensating electric capacity Cc.Node NB is the grid tie point of NMOS tube NMirr0 and NMirr1, and node PB is PMOS
The grid tie point of PM0 and PM1, node PG is the grid tie point of PMOS PM2.
As shown in figure 3, being the structural representation of existing charge pump；Charge pump in Fig. 3 individually represents with mark 9, electric charge
The input connection clock signal clk of pump 9, clock signal clk provides by clock generation circuit 8, clock generation circuit 8 it is general by
Ring oscillator is constituted, and the input of clock generation circuit 8 is connected with high frequency and enables signal HFEN, and signal is enabled according to high frequency
The enable of HFEN and do not enable, the frequency of clock signal clk can be different.The working power of existing charge pump is carried by LDO circuit 1
For charge pump 9 can produce power consumption to be mutated in the handoff procedure for enabling and not enabling that high frequency enables signal HFEN, finally can shadow
Ring the output voltage V_LDO to LDO circuit 1.As shown in figure 4, when being existing LDO circuit 1 when high frequency is enabled and do not enabled
The curve of clock signal and output voltage；HFEN=" 1 " represents that high frequency enables the enable of signal HFEN, and HFEN=" 0 " represents high frequency
Not enabling for signal HFEN is enabled, from the curve of clock signal clk, the frequency of clock signal clk during HFEN=" 1 " is big
The frequency of clock signal clk when HFEN=" 0 "；As seen from Figure 4, enable the enable of signal HFEN in high frequency and do not make
The output voltage V_LDO of LDO circuit 1 can be made to produce overshoot in the handoff procedure of energy, overshoot is respectively as at dotted line circle 101 and 102
Shown, this corresponds respectively to a upward overshoot and a downward overshoot at two, and corresponds respectively to HFEN and switched by " 1 "
The position of " 1 " is switched to for " 0 " and by " 0 ".
From the foregoing, it will be observed that existing LDO circuit 1 is in different modes, it may occur that the mutation of clock frequency is so as to cause LDO circuit
1 output voltage V_LDO unstable problem.As bank card application can bring extra holding to LDO circuit in low-power consumption application
Pin.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of charge pump clock control circuit, can make what charge pump was consumed
Power consumption consecutive variations, reduce the overshoot of working power such as LDO output voltages.Therefore, the present invention also provides a kind of charge pump clock
Control method.
In order to solve the above technical problems, the present invention provide charge pump clock control circuit charge pump clock signal by
The output end of clock generation circuit is provided.
The input of the clock generation circuit is connected with high frequency and enables signal and export the clock signal in output end.
The clock signal that clock generation circuit output when signal is enabled is enabled in the high frequency is first frequency；
The clock signal for enabling clock generation circuit output when signal is not enabled in the high frequency is second frequency, described the
Two frequencies are less than the first frequency.
The high frequency enables the input that signal is input to the clock generation circuit by clock control circuit, described
When high frequency enable signal carries out signal switching, the clock control circuit makes the clock by the curtage of consecutive variations
The frequency of signal consecutive variations between the first frequency and the second frequency, so that the power consumption of charge pump consumption
Consecutive variations.
Further improvement is that the clock generation circuit is ring oscillator.
Further improvement be, the ring oscillator of the clock generation circuit by the anti-phase delay unit of odd number output
End and input head and the tail are sequentially connected composition.
Further improvement is that the clock control circuit is made up of a delay unit, and the delay unit makes the height
Frequency enables rising edge and trailing edge the continuously smooth change of signal.
Further improvement is that the high frequency enables signal by being connected to the ring oscillator after the delay unit
Control end, the rising edge and trailing edge continuously smooth for enabling signal by the high frequency change exports the ring oscillator
The clock signal frequency between the first frequency and the second frequency consecutive variations.
Further improvement is that the control end of the ring oscillator is by the current path with each anti-phase extension apparatus
The grid composition of connected MOS transistor.
Further improvement is that the corresponding MOS transistor of control end of the ring oscillator is NMOS tube, the NMOS
The source ground of pipe, the current path of the corresponding anti-phase extension apparatus of drain electrode connection.
Further improvement is that the corresponding MOS transistor of control end of the ring oscillator is PMOS, the PMOS
The source electrode of pipe connects supply voltage, the current path of the corresponding anti-phase extension apparatus of drain electrode connection.
Further improvement is that the working power of the charge pump is provided by LDO circuit, is consumed by making the charge pump
Power consumption consecutive variations reduce the LDO circuit output voltage overshoot.
Further improvement is that the charge pump is the peripheral circuit of the flash memory module, and the flash memory module includes dodging
Deposit receipt element array and peripheral circuit, the peripheral circuit also include detection amplifier；The output voltage of the LDO circuit is provided
To the flash memory module.
In order to solve the above technical problems, the charge pump clock control method that the present invention is provided comprises the following steps：
The high frequency enables the input that signal is input to the clock generation circuit by clock control circuit, described
When high frequency enable signal carries out signal switching, the clock control circuit makes the clock by the curtage of consecutive variations
The frequency of signal consecutive variations between the first frequency and the second frequency, so that the power consumption of charge pump consumption
Consecutive variations.
The high frequency is enabled after the completion of signal switching：
The clock of the clock generation circuit output with first frequency when signal is enabled is enabled in the high frequency to believe
Number；
When the high frequency enables described with second frequency of clock generation circuit output when signal is not enabled
Clock signal, the second frequency is less than the first frequency.
The present invention sets clock control circuit by enabling the input of signal in the high frequency of clock generation circuit, in high frequency
When enable signal carries out signal switching, clock control circuit can make the frequency of clock signal by the curtage of consecutive variations
The consecutive variations between first frequency and second frequency, so as to make pump voltage signal consecutive variations, so as to prevent LDO circuit
Output voltage produces overshoot, so as to reduce in low-power consumption application as brought extra opening to LDO circuit in bank card application
Pin.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the application schematic diagram of existing LDO circuit；
Fig. 2 is the main body circuit figure of existing LDO circuit；
Fig. 3 is the structural representation of existing charge pump；
Fig. 4 is the curve of clock signal and output voltage of the existing LDO circuit when high frequency is enabled and do not enabled；
Fig. 5 is the structural representation that embodiment of the present invention charge pump clock controls circuit；
Fig. 6 is clock signal and output electricity of the LDO circuit when high frequency is enabled and do not enabled in embodiment of the present invention circuit
The curve of pressure；
Fig. 7 is that the high frequency in embodiment of the present invention circuit enables signal and its postpones signal curve；
Fig. 8 is the circuit diagram of the ring oscillator in embodiment of the present invention circuit.
Specific embodiment
The operating voltage of the charge pump corresponding to embodiment of the present invention charge pump clock control circuit uses LDO circuit, LDO
The application schematic diagram of circuit is referring also to shown in Fig. 1；The output voltage V_LDO of LDO circuit 1 is connected to flash memory module 2, flash memory mould
Block 2 includes flash memory cell array 3 and peripheral circuit 4, and peripheral circuit 4 includes charge pump 5 and detection amplifier 6 and other controls
Logic circuit processed 6.
As shown in figure 5, being the structural representation that embodiment of the present invention charge pump clock controls circuit；The clock of charge pump 9
Signal is provided by the output end of clock generation circuit 8, and charge pump is individually represented with mark 9 in Fig. 5, when charge pump applications to Fig. 1
Then represented using mark 5 when in described flash memory module 2.The input of the clock generation circuit 8 is connected with high frequency and enables letter
Number HFEN simultaneously exports clock signal clk in output end.
Enabling the clock signal clk that the clock generation circuit 8 is exported when signal HFEN is enabled in the high frequency is
First frequency；The clock signal clk of the output of the clock generation circuit 8 when signal HFEN is not enabled is enabled in the high frequency
It is second frequency, the second frequency is less than the first frequency.LDO circuit in embodiment of the present invention circuit is shown in Fig. 6
Enabled and clock signal curve when not enabling in high frequency, in figure 6 the frequency of the clock signal clk different side of density
Wave table shows.
The clock generation circuit 8 includes clock control circuit 10, and enabling signal HFEN in the high frequency carries out signal
During switching, the clock control circuit 10 makes the frequency of the clock signal clk in institute by the curtage of consecutive variations
Consecutive variations between first frequency and the second frequency are stated, so that the power consumption consecutive variations of the consumption of the charge pump 9, and then
Can prevent the working power of the charge pump 9 from producing overshoot.In embodiment of the present invention circuit, the working power of the charge pump 9
There is provided by LDO circuit 1, the output voltage of the LDO circuit 1 is reduced by the power consumption consecutive variations for consuming the charge pump 9
Overshoot.
As shown in figure 8, be the circuit diagram of the ring oscillator of embodiment of the present invention circuit, it is described in the embodiment of the present invention
Clock generation circuit 8 is ring oscillator.The ring oscillator of the clock generation circuit 8 is by the anti-phase delay unit of odd number
10301 output end and input head and the tail are sequentially connected composition.
Preferably selection is that the clock control circuit 10 is made up of a delay unit 10, and the delay unit 10 makes described
High frequency enables rising edge and trailing edge the continuously smooth change of signal HFEN.
The high frequency enables signal HFEN by exporting postpones signal VB after the delay unit 10 and being connected to the ring
The control end of shape oscillator, the rising edge and trailing edge continuously smooth for enabling signal HFEN by the high frequency change makes the ring
The frequency of the clock signal clk of shape oscillator output consecutive variations between the first frequency and the second frequency.
As shown in fig. 7, being high frequency enable signal HFEN and its postpones signal VB curves in embodiment of the present invention circuit, postpones signal VB
The rising edge and trailing edge for enabling signal HFEN in the high frequency change in continuously smooth.As can be seen that the embodiment of the present invention
In preferable selection mode, the voltage that the clock control circuit 10 passes through consecutive variations is that postpones signal VB makes the clock signal
The frequency of CLK consecutive variations between the first frequency and the second frequency.
As shown in fig. 6, be in the embodiment of the present invention circuit clock signal of the LDO circuit when high frequency is enabled and do not enabled and
The curve of output voltage；As can be seen that postpones signal VB enables the rising edge and trailing edge of signal HFEN in company in the high frequency
Continuous smooth change causes that clock signal clk is not mutation when frequency changes, but is continuously changed to by a frequency another
Individual frequency, the clock signal clk at the position as shown in braces 203 is gradually lowered to second frequency, braces by first frequency
Clock signal clk at position shown in 204 progressively increases to first frequency by second frequency, and the gradually consecutive variations of frequency also make
No longer there is overshoot phenomenon in the output voltage V_LDO of last LDO circuit 1, but the void in smoother structure, such as Fig. 6
It is different for all no longer occurring overshoot occur at the position of dotted line circle 101 and 102 in overshoot, this and Fig. 4 at the position of coil 201 and 202
's.
In the embodiment of the present invention, the control end of the ring oscillator is by the current path with each anti-phase extension apparatus
The grid composition of connected MOS transistor 302.The corresponding MOS transistor 302 of control end of the ring oscillator is NMOS
Pipe, the source ground of the NMOS tube, the current path of the corresponding anti-phase extension apparatus of drain electrode connection.In other embodiments
In also can be：The corresponding MOS transistor 302 of control end of the ring oscillator is PMOS, and the source electrode of the PMOS connects
The current path of supply voltage, the corresponding anti-phase extension apparatus of drain electrode connection.
Control method using embodiment of the present invention charge pump clock circuit comprises the following steps：
The high frequency enables the input that signal HFEN is input to the clock generation circuit 8 by clock control circuit 10
End, when high frequency enable signal HFEN carries out signal switching, the electric current that the clock control circuit 10 passes through consecutive variations
Or voltage makes the frequency of clock signal clk consecutive variations between the first frequency and the second frequency, so that
The power consumption consecutive variations of the consumption of the charge pump 9.Preferably selection be, the voltage that the clock control circuit 10 passes through consecutive variations
That is postpones signal VB makes the frequency of clock signal clk consecutive variations between the first frequency and the second frequency.
The high frequency is enabled after the completion of signal HFEN switchings：
When the high frequency enables described with first frequency of the output of the clock generation circuit 8 when signal HFEN is enabled
Clock signal CLK.
Institute of the output of the clock generation circuit 8 with second frequency when signal HFEN is not enabled is enabled in the high frequency
Clock signal clk is stated, the second frequency is less than the first frequency.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (20)
1. a kind of charge pump clock controls circuit, it is characterised in that：The clock signal of charge pump by clock generation circuit output
End provides；
The input of the clock generation circuit is connected with high frequency and enables signal and export the clock signal in output end；
The clock signal that clock generation circuit output when signal is enabled is enabled in the high frequency is first frequency；Institute
It is second frequency to state high frequency and enable the clock signal that the clock generation circuit is exported when signal is not enabled, second frequency
Rate is less than the first frequency；
The high frequency enables the input that signal is input to the clock generation circuit by clock control circuit, in the high frequency
When enable signal carries out signal switching, the clock control circuit makes the clock signal by the curtage of consecutive variations
Frequency between the first frequency and the second frequency consecutive variations so that the charge pump consumption power consumption it is continuous
Change.
2. charge pump clock as claimed in claim 1 controls circuit, it is characterised in that：The clock generation circuit shakes for annular
Swing device.
3. charge pump clock as claimed in claim 2 controls circuit, it is characterised in that：The annular of the clock generation circuit is shaken
Device is swung to be sequentially connected and constituted by output end and the input head and the tail of the anti-phase delay unit of odd number.
4. charge pump clock as claimed in claim 3 controls circuit, it is characterised in that：The clock control circuit is by a time delay
Unit is constituted, and the delay unit changes rising edge and trailing edge continuously smooth that the high frequency enables signal.
5. charge pump clock as claimed in claim 4 controls circuit, it is characterised in that：The high frequency enables signal by described
The control end of the ring oscillator is connected to after delay unit, the rising edge and trailing edge for enabling signal by the high frequency connect
Continuous smooth change makes the frequency of the clock signal of the ring oscillator output in the first frequency and second frequency
Consecutive variations between rate.
6. charge pump clock as claimed in claim 5 controls circuit, it is characterised in that：The control end of the ring oscillator by
The grid composition of the MOS transistor being connected with the current path of each anti-phase extension apparatus.
7. charge pump clock as claimed in claim 5 controls circuit, it is characterised in that：The control end pair of the ring oscillator
The MOS transistor answered is NMOS tube, the source ground of the NMOS tube, the electricity of the corresponding anti-phase extension apparatus of drain electrode connection
Flow path.
8. charge pump clock as claimed in claim 5 controls circuit, it is characterised in that：The control end pair of the ring oscillator
The MOS transistor answered is PMOS, and the source electrode of the PMOS connects supply voltage, the corresponding anti-phase extension list of drain electrode connection
The current path of unit.
9. charge pump clock as claimed in claim 1 controls circuit, it is characterised in that：The working power of the charge pump by
LDO circuit is provided, and the mistake of the output voltage of the LDO circuit is reduced by the power consumption consecutive variations for consuming the charge pump
Punching.
10. charge pump clock as claimed in claim 9 controls circuit, it is characterised in that：The charge pump is the flash memory mould
The peripheral circuit of block, the flash memory module includes flash memory cell array and peripheral circuit, and the peripheral circuit also includes detection
Amplifier；The output voltage of the LDO circuit is supplied to the flash memory module.
11. control methods that circuit is controlled using charge pump clock as claimed in claim 1, it is characterised in that including as follows
Step：
The high frequency enables the input that signal is input to the clock generation circuit by clock control circuit, in the high frequency
When enable signal carries out signal switching, the clock control circuit makes the clock signal by the curtage of consecutive variations
Frequency between the first frequency and the second frequency consecutive variations so that the charge pump consumption power consumption it is continuous
Change；
The high frequency is enabled after the completion of signal switching：
The clock signal of the clock generation circuit output with first frequency when signal is enabled is enabled in the high frequency；
The clock of the clock generation circuit output with second frequency when signal is not enabled is enabled in the high frequency to believe
Number, the second frequency is less than the first frequency.
12. charge pump clock control methods as claimed in claim 11, it is characterised in that：The clock generation circuit is annular
Oscillator.
13. charge pump clock control methods as claimed in claim 12, it is characterised in that：The annular of the clock generation circuit
Oscillator is sequentially connected by output end and the input head and the tail of the anti-phase delay unit of odd number and constituted.
14. charge pump clock control methods as claimed in claim 13, it is characterised in that：The clock control circuit is prolonged by one
Shi Danyuan is constituted, and the delay unit changes rising edge and trailing edge continuously smooth that the high frequency enables signal.
15. charge pump clock control methods as claimed in claim 14, it is characterised in that：The high frequency enables signal by institute
The control end that the ring oscillator is connected to after delay unit is stated, the rising edge and trailing edge of signal are enabled by the high frequency
Continuously smooth change makes the frequency of the clock signal of the ring oscillator output in the first frequency and described second
Consecutive variations between frequency.
16. charge pump clock control methods as claimed in claim 15, it is characterised in that：The control end of the ring oscillator
The grid of the MOS transistor being connected by the current path with each anti-phase extension apparatus is constituted.
17. charge pump clock control methods as claimed in claim 15, it is characterised in that：The control end of the ring oscillator
Corresponding MOS transistor is NMOS tube, and the source ground of the NMOS tube, drain electrode connect the corresponding anti-phase extension apparatus
Current path.
18. charge pump clock control methods as claimed in claim 15, it is characterised in that：The control end of the ring oscillator
Corresponding MOS transistor is PMOS, and the source electrode of the PMOS connects supply voltage, the corresponding anti-phase extension of drain electrode connection
The current path of unit.
19. charge pump clock control methods as claimed in claim 11, it is characterised in that：The working power of the charge pump by
LDO circuit is provided, and the mistake of the output voltage of the LDO circuit is reduced by the power consumption consecutive variations for consuming the charge pump
Punching.
20. charge pump clock control methods as claimed in claim 19, it is characterised in that：The charge pump is the flash memory mould
The peripheral circuit of block, the flash memory module includes flash memory cell array and peripheral circuit, and the peripheral circuit also includes detection
Amplifier；The output voltage of the LDO circuit is supplied to the flash memory module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710003928.9A CN106887245A (en) | 2017-01-04 | 2017-01-04 | Charge pump clock controls circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710003928.9A CN106887245A (en) | 2017-01-04 | 2017-01-04 | Charge pump clock controls circuit and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106887245A true CN106887245A (en) | 2017-06-23 |
Family
ID=59176303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710003928.9A Pending CN106887245A (en) | 2017-01-04 | 2017-01-04 | Charge pump clock controls circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106887245A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108388299A (en) * | 2018-02-12 | 2018-08-10 | 上海集成电路研发中心有限公司 | Low pressure difference linear voltage regulator |
| CN111597837A (en) * | 2019-02-21 | 2020-08-28 | 华大半导体有限公司 | Device and method for reducing starting power consumption of charge pump |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080116961A1 (en) * | 2006-11-14 | 2008-05-22 | Sanyo Electric Co., Ltd. | Charge pump circuit |
| CN102088287A (en) * | 2009-12-03 | 2011-06-08 | 卡西欧电子工业株式会社 | Clock signal generating device, electronic device and PLL control device |
| CN102263499A (en) * | 2010-05-27 | 2011-11-30 | 上海宏力半导体制造有限公司 | Clock generation circuit and charge pump system |
| CN103916102A (en) * | 2014-03-10 | 2014-07-09 | 北京时代民芯科技有限公司 | FPGA embedded full-digital low-power-consumption clock generating circuit |
| CN106067787A (en) * | 2016-07-18 | 2016-11-02 | 西安紫光国芯半导体有限公司 | A kind of clock generation circuit being applied to charge pump system |
-
2017
- 2017-01-04 CN CN201710003928.9A patent/CN106887245A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080116961A1 (en) * | 2006-11-14 | 2008-05-22 | Sanyo Electric Co., Ltd. | Charge pump circuit |
| CN102088287A (en) * | 2009-12-03 | 2011-06-08 | 卡西欧电子工业株式会社 | Clock signal generating device, electronic device and PLL control device |
| CN102263499A (en) * | 2010-05-27 | 2011-11-30 | 上海宏力半导体制造有限公司 | Clock generation circuit and charge pump system |
| CN103916102A (en) * | 2014-03-10 | 2014-07-09 | 北京时代民芯科技有限公司 | FPGA embedded full-digital low-power-consumption clock generating circuit |
| CN106067787A (en) * | 2016-07-18 | 2016-11-02 | 西安紫光国芯半导体有限公司 | A kind of clock generation circuit being applied to charge pump system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108388299A (en) * | 2018-02-12 | 2018-08-10 | 上海集成电路研发中心有限公司 | Low pressure difference linear voltage regulator |
| CN111597837A (en) * | 2019-02-21 | 2020-08-28 | 华大半导体有限公司 | Device and method for reducing starting power consumption of charge pump |
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Application publication date: 20170623 |