CN103913915B - A kind of array base palte, display floater and display device - Google Patents
A kind of array base palte, display floater and display device Download PDFInfo
- Publication number
- CN103913915B CN103913915B CN201410121119.4A CN201410121119A CN103913915B CN 103913915 B CN103913915 B CN 103913915B CN 201410121119 A CN201410121119 A CN 201410121119A CN 103913915 B CN103913915 B CN 103913915B
- Authority
- CN
- China
- Prior art keywords
- level signal
- varistor
- control circuit
- grid line
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of array base palte, display floater and display device, it is achieved do not increase the purpose of peak power when driving chip can reduce gated sweep with complicated line.This array base palte provides multiple first control circuits and multiple second control circuit；Gate driver circuit electrically connects with the input of each first control circuit and each second control circuit；All grid line is divided into the first grid line group and the second grid line group, the outfan of each first control circuit is electrically connected with the grid of a line TFT by the grid line in the first grid line group respectively, and the outfan of each second control circuit is electrically connected with the grid of a line TFT by the grid line in the second grid line group respectively；Gate driver circuit, for alternately providing the first level signal and the second electrical level signal opening TFT, and for providing the three level signal turning off TFT with frame alternating synchronization；First control circuit and second control circuit carry out selectivity to the first level signal and second electrical level signal respectively and pass through.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of array base palte, display floater and display
Device.
Background technology
Liquid crystal display, when carrying out gated sweep, is generally the most all scanned to the other end by one end, at this
Scanning process, peak power is higher, easily produces more heat, affects the life-span of liquid crystal display.
In prior art, it is typically employed on array base palte and carries out parity rows separation distribution, increase driving chip
To realize the Time share scanning of parity rows thin film transistor (TFT) (Thin Film Transistor, TFT), peak can be made
Value power reduces, and reduces the generation of heat, extends the service life of liquid crystal display.
But, the Time share scanning that prior art uses, completed by then passing through parity rows separation distribution, need
Increase the more integrated circuit component (Integrate Circuit, IC) for driving.Visible, although one
Determine peak power when degree reduces gated sweep, but hardware cost is significantly increased.
Summary of the invention
It is an object of the invention to provide a kind of array base palte, display floater and display device, to realize not providing
The purpose of peak power when more driving chip and complicated line can reduce gated sweep, thus save into
This.
It is an object of the invention to be achieved through the following technical solutions:
The embodiment of the present invention provides a kind of array base palte, including the pixel cell battle array of multiple pixel cells composition
Row, each described pixel cell includes a thin film transistor (TFT) TFT, also includes gate driver circuit, a plurality of
Grid line, multiple first control circuit and multiple second control circuit；
Described gate driver circuit and each described first control circuit and the input of each described second control circuit
End electrical connection；
Whole described grid lines are divided into the first grid line group and the second grid line group, each described first control circuit
Outfan is respectively by the grid of grid line described in described first grid line group with TFT described in corresponding a line
Pole electrically connects, and the outfan of each described second control circuit is respectively by the institute in described second grid line group
State grid line to electrically connect with the grid of TFT described in corresponding a line；
Described gate driver circuit, for alternately providing the first electricity opening described TFT with frame alternating synchronization
Ordinary mail number and second electrical level signal, and for providing the three level signal turning off described TFT；
Described first control circuit, is used for making described first level signal and described three level signal lead to
Cross；
Described second control circuit, is used for making described second electrical level signal and described three level signal lead to
Cross；
Wherein, described first level signal, described second electrical level signal and the electricity of described three level signal
Put down and be not mutually equal.
In the embodiment of the present invention, described gate driver circuit alternately provides unlatching described with frame alternating synchronization
Described first level signal of TFT and described second electrical level signal, described first control circuit and described
Described first level signal and described second electrical level signal-selectivity are passed through by two control circuits respectively.Realize
During gated sweep, in same frame time, only TFT described in odd-numbered line opens or only TFT described in even number line
Open, thus peak power when reducing gated sweep.
Preferably, each described grid line in described first grid line group is odd-numbered line grid line, described second grid line
Each described grid line in group is even number line grid line；Or,
Each described grid line in described first grid line group is even number line grid line, each in described second grid line group
Described grid line is odd-numbered line grid line.
Preferably, described gate driver circuit, specifically for:
There is provided described first level signal and three level signal successively in odd-numbered frame, carry successively in even frame
For described second electrical level signal and three level signal；Or,
There is provided described first level signal and three level signal successively in even frame, carry successively in odd-numbered frame
For described second electrical level signal and three level signal.
Preferably, described first control circuit, including the first varistor, the second varistor, the 3rd
Varistor and the first storage electric capacity；First end of described first varistor controls electricity as described first
The input on road；Second end of described first varistor respectively with the first end of described second varistor
The first end electrical connection with described 3rd varistor；Second end of described second varistor and described
Second end of three varistors all electrically connects and as described first with the described first the first end storing electric capacity
The outfan of control circuit；Second end ground connection of described first storage electric capacity；
Described second control circuit, including described 3rd varistor, the 4th varistor and the second storage
Electric capacity；First end of described 3rd varistor and the first end of the 4th varistor electrically connect as described
The input of second control circuit；Second end and the second of the 4th varistor of described 3rd varistor
End all electrically connects and as the output of described second control circuit with the described second the first end storing electric capacity
End；Second end ground connection of described second storage electric capacity.
Preferably, the level of described first level signal is less than the level of described second electrical level signal, described
The level of three level signal is less than the level of described first level signal.
Preferably, the level of described first level signal is less than the level of described second electrical level signal, described
The level of three level signal is less than the level of described first level signal.
Preferably, described first varistor is for making level be less than the input letter of described second electrical level signal
Number pass through, and the input signal stoping level to be greater than or equal to described second electrical level signal is passed through；
Described second varistor is greater than or equal to the input signal of described first level signal for making level
Pass through；
Described 3rd varistor is for the input signal making level be less than or equal to described three level signal
Pass through；
The input signal that described 4th varistor is greater than or equal to described second electrical level signal for making level
Pass through.
Preferably, described first varistor is specifically for making described first level signal and described 3rd electricity
Ordinary mail number passes through, and stops described second electrical level signal to pass through；
Described second varistor is specifically for making described first level signal pass through, and stops the described 3rd
Level signal is passed through；
Described 3rd varistor is specifically for making described three level signal pass through, and stops described first
Level signal and described second electrical level signal pass through；
Described 4th varistor is specifically for making described second electrical level signal pass through, and stops described first
Level signal and described three level signal pass through.
The embodiment of the present invention has the beneficial effect that: described gate driver circuit alternately provides with frame alternating synchronization
Open described first level signal and described second electrical level signal, the described first control circuit of described TFT
Respectively described first level signal and described second electrical level signal-selectivity are led to described second control circuit
Cross.When realizing gated sweep, in same frame time, only TFT unlatching described in odd-numbered line or only even number line
Described TFT opens, thus peak power when reducing gated sweep.It is implemented without providing more driving core
The purpose of peak power when sheet and complicated line can reduce gated sweep, thus the few hardware cost of joint.
The embodiment of the present invention also provides for a kind of display floater, the array base palte provided including example performed as described above.
The embodiment of the present invention has the beneficial effect that: the described gate driver circuit of array base palte, replaces with frame
Timed delivery is for providing described first level signal and described second electrical level signal opening described TFT, described
First control circuit and described second control circuit are respectively to described first level signal and described second electrical level
Signal-selectivity passes through.When realizing gated sweep, in same frame time, only odd-numbered line TFT open or
Only even number line TFT is opened, thus peak power when reducing gated sweep.It is implemented without providing more to drive
The purpose of peak power when dynamic chip and complicated line can reduce gated sweep, thus the few hardware of joint becomes
This.
The embodiment of the present invention also provides for a kind of display device, the display floater provided including example performed as described above.
The embodiment of the present invention has the beneficial effect that: the described gate driver circuit of array base palte, described grid
Drive circuit and frame alternating synchronization alternately provide described first level signal and described the opening described TFT
Two level signals, described first control circuit and described second control circuit are respectively to described first level letter
Number and described second electrical level signal-selectivity pass through.When realizing gated sweep, in same frame time, only
TFT described in TFT unlatching described in odd-numbered line or only even number line opens, thus its peak work when reducing gated sweep
Rate.Peak power when being implemented without providing more driving chip and complicated line can reduce gated sweep
Purpose, thus the few hardware cost of joint.
Accompanying drawing explanation
The schematic diagram of the array base palte that Fig. 1 provides for the embodiment of the present invention；
The schematic diagram of the first control circuit that Fig. 2 provides for the embodiment of the present invention；
The schematic diagram of the second control circuit that Fig. 3 provides for the embodiment of the present invention；
First control circuit that Fig. 4 provides for the embodiment of the present invention and second control circuit input input signal
Schematic diagram.
Detailed description of the invention
Below in conjunction with Figure of description, the embodiment of the present invention is realized process to be described in detail.Should be noted that
, the most same or similar label represents same or similar element or has same or like merit
The element of energy.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining the present invention,
And be not considered as limiting the invention.Obviously, described embodiment is only that a part of the present invention is real
Execute example rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art exist
The every other embodiment obtained on the premise of not paying creative work, broadly falls into present invention protection
Scope.
Seeing Fig. 1, the embodiment of the present invention provides a kind of array base palte, forms including multiple pixel cells 104
Pixel cell 104 array, each pixel cell 104 includes a thin film transistor (TFT) TFT 105, also includes
Gate driver circuit 103；A plurality of grid line, being designated as G1 to G2n, n is natural number；Multiple first controls electricity
Road 101 and multiple second control circuit 102.
Gate driver circuit 103 and each first control circuit 101 and the input of each second control circuit 102
Electrical connection.
All grid lines are divided into the first grid line group and the second grid line group, each grid line in the first grid line group and the
Grid line in two grid line groups is intervally arranged.
The outfan of each first control circuit 101 is respectively by the grid line and corresponding in the first grid line group
The grid electrical connection of row TFT 105, the outfan of each second control circuit 102 is respectively by the second grid line group
In the grid an of grid line and corresponding a line TFT 105 electrically connect.
Gate driver circuit 103, for alternately providing the first level opening TFT 105 with frame alternating synchronization
Signal and second electrical level signal, and for providing the three level signal turning off TFT 105.
First control circuit 101, is used for making the first level signal and three level signal pass through；Second control
Circuit 102 processed, is used for making second electrical level signal and three level signal pass through；Wherein, the first level letter
Number, the level of second electrical level signal and three level signal is not mutually equal.
In the embodiment of the present invention, gate driver circuit 103 alternately provides with frame alternating synchronization and opens TFT 105
The first level signal and second electrical level signal, first control circuit 101 and second control circuit 102 are respectively
First level signal and second electrical level signal-selectivity are passed through.When realizing gated sweep, when same frame
In, only odd-numbered line TFT 105 is opened or only even number line TFT 105 is opened, thus when reducing gated sweep
Peak power.
Preferably, each grid line in the first grid line group is odd-numbered line grid line, each grid line in the second grid line group
For even number line grid line；Or,
Each grid line in first grid line group is even number line grid line, and each grid line in the second grid line group is odd-numbered line
Grid line.
Such as, using grid line G1, grid line G3..... grid line G2n-3 and grid line G2n-3 as the first grid line
Group, using grid line G2, grid line G4..... grid line G2n-2 and grid line G2n as the second grid line group, specifically joins
Examine shown in Fig. 1.Or, using grid line G2, grid line G4..... grid line G2n-2 and grid line G2n as first
Grid line group, using grid line G1, grid line G3..... grid line G2n-3 and grid line G2n-3 as the second grid line group,
This kind of mode is similar to that shown in Fig. 1, does not repeats them here.
Preferably, gate driver circuit 103, specifically for: provide the first level signal successively in odd-numbered frame
With three level signal, provide second electrical level signal and three level signal successively in even frame；Or,
There is provided the first level signal and three level signal successively in even frame, provide the second electricity successively in odd-numbered frame
Ordinary mail number and three level signal.In the present embodiment, varying level can be carried out at different frame as required
The offer of signal.It should be noted that due to first control circuit 101 and second control circuit 102
So that three level signal passes through, therefore, no matter each row TFT all can be carried out by odd-numbered frame or even frame
Turn off.
Such as: gate driver circuit 103 is controlled to the input and second of first control circuit 101 in odd-numbered frame
The input of circuit 102 processed provides the first level signal, in even frame to the input of first control circuit 101
End and second control circuit 102 provide second electrical level signal.Gate driver circuit 103 is carried in odd-numbered frame
First level signal of confession and three level signal, first control circuit 101 is passed to；But for grid
Second electrical level signal that pole drive circuit 103 provides in even frame and three level signal, owing to first controls
Circuit 101 can stop second electrical level signal to pass through, and therefore in even frame, first control circuit 101 can only make
Three level signal passes through.In like manner, the first level letter gate driver circuit 103 provided in odd-numbered frame
Number and three level signal, owing to second control circuit 102 can stop the first level signal to be passed through, therefore exist
Odd-numbered frame, second control circuit 102 can only make three level signal pass through；For gate driver circuit 103
At second electrical level signal and the three level signal of even frame offer, second control circuit 102 is passed to.
Therefore, the present embodiment is opened in odd-numbered frame only odd-numbered line TFT 105, in even frame only even number line TFT
105 open.Additionally, generally often driven a line TFT 105, all provide the 3rd to this row TFT 105
Level signal is with the shutoff told people to carry out orders.The present embodiment is intended merely to illustrate, and the present invention is not limited to this.
The array base palte provided for more detailed description the present embodiment, it is provided that the first more specific control electricity
Road 101 and second control circuit 102, see Fig. 2 and Fig. 3 respectively.
As in figure 2 it is shown, first control circuit 101, including the first varistor RC1, the second varistor
RC2, the 3rd varistor RC3 and the first storage electric capacity C1；First end of the first varistor RC1 is made
Input IN1 for first control circuit 101；Second end of the first varistor RC1 is pressed with second respectively
First end of quick resistance RC2 and the first end electrical connection of the 3rd varistor RC3；Second varistor
Second end of RC2 and the 3rd varistor RC3 the second end all with first end of the first storage electric capacity C1
Electrical connection, and as the outfan OUT1 of first control circuit 101, this outfan OUT1 and an odd number
Row grid line electrically connects；The second end earthing power supply GND of the first storage electric capacity C1.
As it is shown on figure 3, second control circuit 102, including the 3rd varistor RC3, the 4th varistor
RC4 and second storage electric capacity C2；First end of the 3rd varistor RC3 and the 4th varistor RC4's
First end electrical connection is as the input IN2 of second control circuit 102；The second of 3rd varistor RC3
Second end of end and the 4th varistor RC4 all electrically connects and conduct with the second the first end storing electric capacity C2
The outfan OUT2 of second control circuit 102；The second end earthing power supply of the second storage electric capacity C2
GND。
For the unblocked level of TFT 105, in the range of higher than the safety level of this unblocked level, it is stipulated that with
First level signal opens odd-numbered line TFT 105, opens even number line TFT 105 with second electrical level signal；Or
Person, second electrical level signal is opened odd-numbered line TFT 105, is opened even number line TFT with the first level signal
105.The effect of each element of first control circuit 101 and second control circuit 102 is as follows:
First varistor RC1 is used for, and the input signal making level be less than second electrical level signal VG2 is led to
Cross, and the input signal stoping level to be greater than or equal to second electrical level signal VG2 is passed through.Visible, first
Level signal VG1 and three level signal VGL can pass through, and second electrical level signal VG2 cannot lead to
Cross.
Second varistor RC2 is used for, and makes level be greater than or equal to the input letter of the first level signal VG1
Number pass through.Owing to the second varistor RC2 is to select on the basis of the first varistor RC1 output
Select, and by the first varistor RC1 be only the first level signal VG1 and three level signal
VGL, therefore the first level signal VG1 and three level signal VGL are entered by the second varistor RC2
Row selects, and makes the first level signal VG1 pass through, and makes three level signal VGL to pass through.
3rd varistor RC3 is used for, and the input signal making level be less than or equal to three level signal is led to
Cross.
When the 3rd varistor RC3 is applied to first control circuit 101, due to the 3rd varistor RC3
It is to select on the basis of the first varistor RC1 output, and by the first varistor RC1's
Being only the first level signal VG1 and three level signal VGL, therefore the 3rd varistor RC3 is to
One level signal VG1 and three level signal VGL select, and make three level signal VGL lead to
Cross, and make the first level signal VG1 to pass through.
When the 3rd varistor RC3 is applied to second control circuit 102, the 3rd varistor RC3 makes
Three level signal VGL passes through, and makes the first level signal VG1 and the second electrical level signal VG2 cannot
Pass through.
4th varistor RC4 is used for, and makes the input letter that level is greater than or equal to second electrical level signal VG2
Number pass through.That is, make second electrical level signal VG2 pass through, and make the first level signal VG1 and the 3rd level
Signal VGL cannot pass through.
Such as: based on the first control circuit 101 shown in Fig. 2 and Fig. 3 and second control circuit 102 show
It is intended to, in order to realize in odd-numbered frame time sweep odd-numbered line TFT 105, even frame time sweep even number line
TFT 105, scanning odd-numbered line and even number line TFT 105 time different in i.e. one frame time, the first electricity can be made
The level of ordinary mail number is less than the first level less than the level of second electrical level signal, the level of three level signal
The level of signal.
See Fig. 4, first control circuit 101 and the signal hint of second control circuit 102 input input
Figure.Wherein, gate driver circuit 103 provides defeated to first control circuit 101 and second control circuit 102
Enter signal S1, S2 ... S (2n-1), S2n.It should be noted that in a frame time, only to the first control
The input of circuit 101 processed and second control circuit 102 provides the first level signal VG1 and the 3rd level
Signal VGL；Or, only provide the to the input of first control circuit 101 and second control circuit 102
Two level signals VG1 and three level signal VGL, and need first control circuit 101 and second to control
Circuit 102 exports after selecting the level signal of input.Three level signal VGL shown in Fig. 4
Level less than 0 level represented by dotted line.
By upper available, the concrete effect of each element of first control circuit 101 and second control circuit 102
As follows:
First varistor RC1 is specifically for making the first level signal and three level signal pass through, and hinders
Only second electrical level signal passes through.
Second varistor RC2 is specifically for making the first level signal pass through, and stops three level signal
Pass through.
3rd varistor RC3 is specifically for making three level signal pass through, and stops the first level signal
Pass through with second electrical level signal.
4th varistor RC4 is specifically for making second electrical level signal pass through, and stops the first level signal
Pass through with three level signal.
From the foregoing, it will be observed that for first control circuit 101 and second control circuit 102, at a frame time
In, no matter gate driver circuit provides the first level signal VG1 or second electrical level signal VG2, inevitable
Only open odd-numbered line TFT 105 or even number line TFT 105.
And for cut-off signals VGL as shown in Figure 4, it is provided that give the most scanned TFT, specifically
Scanning process can realize according to embodiments of the present invention, does not repeats them here.
The embodiment of the present invention has the beneficial effect that: described gate driver circuit alternately provides with frame alternating synchronization
Open described first level signal and described second electrical level signal, the described first control circuit of described TFT
Respectively described first level signal and described second electrical level signal-selectivity are led to described second control circuit
Cross.When realizing gated sweep, in same frame time, only TFT unlatching described in odd-numbered line or only even number line
Described TFT opens, thus peak power when reducing gated sweep.It is implemented without providing more driving core
The purpose of peak power when sheet and complicated line can reduce gated sweep, thus the few hardware cost of joint.
The embodiment of the present invention also provides for a kind of display floater, the array base palte provided including example performed as described above.
The embodiment of the present invention has the beneficial effect that: described gate driver circuit alternately provides with frame alternating synchronization
Open described first level signal and described second electrical level signal, the described first control circuit of described TFT
Respectively described first level signal and described second electrical level signal-selectivity are led to described second control circuit
Cross.When realizing gated sweep, in same frame time, only TFT unlatching described in odd-numbered line or only even number line
Described TFT opens, thus peak power when reducing gated sweep.It is implemented without providing more driving core
The purpose of peak power when sheet and complicated line can reduce gated sweep, thus the few hardware cost of joint.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. an array base palte, including the pixel unit array of multiple pixel cells composition, each described
Pixel cell includes a thin film transistor (TFT) TFT, it is characterised in that also include gate driver circuit, a plurality of grid
Line, multiple first control circuit and multiple second control circuit；
Described gate driver circuit and each described first control circuit and the input of each described second control circuit
End electrical connection；
Whole described grid lines are divided into the first grid line group and the second grid line group, each described first control circuit defeated
Go out end respectively by the grid of grid line described in described first grid line group with TFT described in corresponding a line
Electrical connection, the outfan of each described second control circuit is respectively by grid described in described second grid line group
Line electrically connects with the grid of TFT described in corresponding a line；
Described gate driver circuit, for alternately providing the first level opening described TFT with frame alternating synchronization
Signal and second electrical level signal, and for providing the three level signal turning off described TFT；
Described first control circuit, is used for making described first level signal and described three level signal pass through；
Described second control circuit, is used for making described second electrical level signal and described three level signal pass through；
Wherein, described first level signal, described second electrical level signal and the level of described three level signal
It is not mutually equal.
2. array base palte as claimed in claim 1, it is characterised in that each in described first grid line group
Described grid line is odd-numbered line grid line, and each described grid line in described second grid line group is even number line grid line；Or,
Each described grid line in described first grid line group is even number line grid line, each institute in described second grid line group
Stating grid line is odd-numbered line grid line.
3. array base palte as claimed in claim 1, it is characterised in that described gate driver circuit, tool
Body is used for:
There is provided described first level signal and three level signal successively in odd-numbered frame, provide successively in even frame
Described second electrical level signal and three level signal；Or,
There is provided described first level signal and three level signal successively in even frame, provide successively in odd-numbered frame
Described second electrical level signal and three level signal.
4. the array base palte as described in any one of claims 1 to 3, it is characterised in that:
Described first control circuit, including the first varistor, the second varistor, the 3rd varistor and
First storage electric capacity；First end of described first varistor is as the input of described first control circuit；
Second end of described first varistor is pressed with the first end of described second varistor and the described 3rd respectively
First end electrical connection of quick resistance；Second end of described second varistor and the of described 3rd varistor
Two ends all the first ends with described first storage electric capacity electrically connect and as the output of described first control circuit
End；Second end ground connection of described first storage electric capacity；
Described second control circuit, including described 3rd varistor, the 4th varistor and the second storage electricity
Hold；First end of described 3rd varistor and the first end of the 4th varistor electrically connect as described second
The input of control circuit；Second end of described 3rd varistor and the second end of the 4th varistor all with
First end electrical connection the outfan as described second control circuit of described second storage electric capacity；Described
Second end ground connection of two storage electric capacity.
5. array base palte as claimed in claim 4, it is characterised in that the electricity of described first level signal
The flat level less than described second electrical level signal, the level of described three level signal is less than described first level
The level of signal.
6. array base palte as claimed in claim 5, it is characterised in that:
Described first varistor is used for, and the input signal making level be less than described second electrical level signal is passed through,
And the input signal stoping level to be greater than or equal to described second electrical level signal passes through；
Described second varistor is used for, and makes level be greater than or equal to the input signal of described first level signal
Pass through；
Described 3rd varistor is used for, and makes level be less than or equal to the input signal of described three level signal
Pass through；
Described 4th varistor is used for, and makes level be greater than or equal to the input signal of described second electrical level signal
Pass through.
7. array base palte as claimed in claim 6, it is characterised in that:
Described first varistor specifically for, make described first level signal and described three level signal lead to
Cross, and stop described second electrical level signal to pass through；
Described second varistor specifically for, make described first level signal pass through, and stop the described 3rd
Level signal is passed through；
Described 3rd varistor specifically for, make described three level signal pass through, and stop described first
Level signal and described second electrical level signal pass through；
Described 4th varistor specifically for, make described second electrical level signal pass through, and stop described first
Level signal and described three level signal pass through.
8. a display floater, it is characterised in that include the battle array as described in any one of claim 1 to 7
Row substrate.
9. a display device, it is characterised in that include display floater as claimed in claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410121119.4A CN103913915B (en) | 2014-03-27 | 2014-03-27 | A kind of array base palte, display floater and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410121119.4A CN103913915B (en) | 2014-03-27 | 2014-03-27 | A kind of array base palte, display floater and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103913915A CN103913915A (en) | 2014-07-09 |
| CN103913915B true CN103913915B (en) | 2016-08-17 |
Family
ID=51039706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410121119.4A Active CN103913915B (en) | 2014-03-27 | 2014-03-27 | A kind of array base palte, display floater and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103913915B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104240631B (en) * | 2014-08-18 | 2016-09-28 | 京东方科技集团股份有限公司 | GOA circuit and driving method, display device |
| CN104361856B (en) * | 2014-10-27 | 2017-04-12 | 京东方科技集团股份有限公司 | Driving circuit and driving method of active matrix OLED (organic light emitting diode) pixel circuit |
| CN106875890B (en) | 2017-04-27 | 2021-01-12 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and driving method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1375812A (en) * | 2001-03-15 | 2002-10-23 | 株式会社日立制作所 | Liquid crystal display device with low-voltage driving circuit |
| CN101105585A (en) * | 2006-07-12 | 2008-01-16 | 三星电子株式会社 | Display device and method of driving thereof |
| TWI413089B (en) * | 2010-03-12 | 2013-10-21 | Chunghwa Picture Tubes Ltd | Method for driving liquid crystal display |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3750734B2 (en) * | 2001-07-27 | 2006-03-01 | セイコーエプソン株式会社 | Scan line driving circuit, electro-optical device, electronic apparatus, and semiconductor device |
-
2014
- 2014-03-27 CN CN201410121119.4A patent/CN103913915B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1375812A (en) * | 2001-03-15 | 2002-10-23 | 株式会社日立制作所 | Liquid crystal display device with low-voltage driving circuit |
| CN101105585A (en) * | 2006-07-12 | 2008-01-16 | 三星电子株式会社 | Display device and method of driving thereof |
| TWI413089B (en) * | 2010-03-12 | 2013-10-21 | Chunghwa Picture Tubes Ltd | Method for driving liquid crystal display |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103913915A (en) | 2014-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107750377A (en) | display panel redundancy scheme | |
| CN107490912A (en) | A kind of array base palte, display panel and display device | |
| CN103700354B (en) | Grid electrode driving circuit and display device | |
| CN206194295U (en) | Data line demultiplexer , display substrates , display panel and display device | |
| CN106297680A (en) | Display floater | |
| CN104536224B (en) | Thin-film transistor array base-plate and display panel | |
| CN105047155B (en) | Liquid crystal display device and its GOA scanning circuits | |
| CN103198804B (en) | A kind of liquid crystal indicator and driving method thereof | |
| CN105869599B (en) | A kind of array substrate and its driving method and display panel | |
| CN102621758A (en) | Liquid crystal display device and driving circuit thereof | |
| CN101216650A (en) | Liquid crystal display device array substrate and driving method thereof | |
| CN103913915B (en) | A kind of array base palte, display floater and display device | |
| CN105185332A (en) | Liquid crystal display panel, driving circuit thereof and manufacturing method thereof | |
| CN110136630A (en) | A kind of display panel and its driving method, display device | |
| CN106128384A (en) | Gate drive apparatus and display floater | |
| CN105372892A (en) | Array substrate and liquid crystal display panel | |
| CN202886797U (en) | Array substrate, display panel and display device | |
| CN103926735A (en) | Colored film substrate and manufacturing method thereof and display panel and display device | |
| CN106710501A (en) | Drive circuit structure of display panel and display device | |
| CN105244002A (en) | Array substrate, liquid crystal display and drive method of liquid crystal display | |
| CN109256081A (en) | A kind of source electrode drive circuit, display panel | |
| CN206096714U (en) | Display panel and display device | |
| CN106297630A (en) | Scan drive circuit and there is the flat display apparatus of this circuit | |
| CN202473182U (en) | Flat panel display device | |
| CN106991955A (en) | Scan drive circuit, display panel and driving method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |