CN103904866A - Primary side detection method for output voltage of flyback converter in critical intermittent and intermittent modes - Google Patents
Primary side detection method for output voltage of flyback converter in critical intermittent and intermittent modes Download PDFInfo
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Abstract
The invention discloses a primary side detection method for output voltage of a flyback converter in critical intermittent and intermittent modes. A self-study module and the like are included. The method comprises the steps that firstly, the self-study module receives auxiliary or primary side winding voltage Vcr, analyzes the waveform of the voltage Vcr and then outputs one-half resonance oscillation fall time Td and a sampling keeping signal CPs/h; secondly, a time shift circuit with controllable time shift receives the auxiliary or primary side winding voltage Vcr, corresponding time shift one-half resonance oscillation fall time Td is conducted on the auxiliary or primary side winding voltage Vcr according to the one-half resonance oscillation fall time Td output by the self-study module, and Vtd is output; thirdly, when the self-study module outputs the sampling keeping signal CPs/h, a sampling circuit conducts sampling keeping on the Vtd output by the time shift circuit with the controllable time shift, and outputs voltage Vs/h; the output voltage Vs/h is the reflection voltage Vo-refl of a primary side winding, and the output voltage Vo of the flyback power converter can be accurately represented through the reflection voltage Vo-refl of the primary side winding.
Description
Technical field
The present invention relates to power inverter topology detection and control in application electric technology field, especially a kind of detection method for flyback power converter output voltage, the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous, discontinuous mode is surveyed; accurately detect flyback power converter and be operated in the output voltage in critical discontinuous and discontinuous mode lower time by the detection of former limit winding voltage.
Background technology
Because having by coupling inductance transformer cheaply, flyback power converter completes input and output isolation feature, so in middle low power DC-to-DC, very extensive in the application of AC-DC.The output voltage of flyback power converter can have been surveyed by the former frontier inspection of its coupling inductance transformer, and simplify the feedback circuit being formed by photoelectrical coupler and other components and parts in flyback power converter, can further reduce the cost of flyback power converter.
Flyback power converter is operated in critical discontinuous and discontinuous mode lower time, as output diode D
ooutput current I
dOdecay at 1 o'clock by maximum, the reflected voltage V on coupling inductance transformer primary side winding
o_REFLit is its secondary output voltage V
obe multiplied by former secondary winding turns ratio N, that is, now, the reflected voltage V on coupling inductance transformer primary side winding
o_REFLcan accurately characterize the output voltage V of flyback power converter
o.
For realizing by the reflected voltage V on the former limit winding of coupling inductance transformer
o_REFLaccurately characterize the output voltage V of flyback power converter
oexisting considerable patent has proposed various implementation methods, as the patent No. is respectively US6853563B1, US7463497B2, the patent of US8213192B2 and US20120140531A1 has all proposed similar concept, before the flex point declining in former limit winding voltage, former limit winding voltage is sampled, sampled voltage can accurately characterize the output voltage V of flyback power converter
o.
Before the flex point declining in former limit winding voltage, former limit winding voltage is sampled,, this sampling operation of sampled point before flex point, be the operation of a kind of non-causal, but non-causal operation is many than cause and effect complicated operation, as the patent No. is respectively US6853563B1, US7463497B2, the patent of US8213192B2 and US20120140531A1 has all proposed corresponding method for this non-causal operation.But in these schemes that propose, there is no the enough impact of resonance Td fall time on sampled point that be concerned about.
General flyback power converter is operated in critical discontinuous and discontinuous mode lower time, and after the winding voltage flex point of former limit, declining is with former limit magnetizing inductance L
mparasitic capacitance C with power switch
rresonance declines.This resonance Td(fall time is as shown in Figure 1) be and former limit magnetizing inductance L
mparasitic capacitance C with power switch
rrelevant:
To different power grades and input and output voltage application, corresponding L
mand C
rhave sizable variation, corresponding Td also has sizable variation.Paying close attention to and solving resonance Td fall time is object of the present invention on the impact of sampled point.
Summary of the invention
The technical problem to be solved in the present invention is to provide the former frontier inspection of output voltage of a kind of inverse excitation type converter critical discontinuous, discontinuous mode and surveys.
In order to solve the problems of the technologies described above, the invention provides the former frontier inspection of the output voltage of a kind of inverse excitation type converter critical discontinuous, discontinuous mode and survey, comprise time shift circuit and the sample circuit of self-learning module, controlled time shift; The first step: self-learning module receives auxiliary or former limit winding voltage V
cR, and to V
cRafter voltage waveform is analyzed, output 1/2nd resonance Td fall time and sampling inhibit signal CP
s/H; Second step: the time shift circuit of controlled time shift receives auxiliary or former limit winding voltage V
cR, and will assist or former limit winding voltage V according to 1/2nd resonance Td fall time of self-learning module output
cRcarry out corresponding time shift 1/2nd resonance Td fall time, output V
tD; The 3rd step: sample circuit is at self-learning module output sampling inhibit signal CP
s/Htime, the V that the time shift circuit of controlled time shift is exported
tDsample maintenance output voltage V
s/H; Described output voltage V
s/Hthe reflected voltage V on the winding of former limit
o_REFL, by the reflected voltage V on the winding of former limit
o_REFLcan accurately characterize the output voltage V of flyback power converter
o.
Improvement as the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous of the present invention, discontinuous mode is surveyed: described self-learning module is by comparator C OMP1, comparator C OMP2, logical AND gate and differential circuit form; Described differential circuit is by capacitor C, and resistance R and amplifier OP form; Assist or former limit winding voltage V
cRthrough " 1 " signal of comparator C OMP2 export resonance decline zero passage; Assist or former limit winding voltage V
cRthrough differential circuit output V
cRthe negative slope that resonance declines; Because amplifier OP negative function is exported positive slope value, make comparator C OMP1 be output as level"1"; Comparator C OMP1, COMP2 output is level"1", and logical AND gate output keeps level"1"; Work as V
cRthe negative slope that resonance declines is zero or while transferring positive slope to, comparator C OMP1 is output as " 0 ", and makes one of logical AND gate be input as " 0 ", and makes logical AND gate be output as " 0 "; Logical AND gate output closes by being opened to 1/2nd resonance Td fall time pulsewidths that corresponding pulsewidth is exactly correspondence.
Further improvement as the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous of the present invention, discontinuous mode is surveyed: the time shift circuit of described controlled time shift comprises sampling input distributor circuit, a N storage unit circuit and output select circuit; Described
described Tdmax is maximum resonance Td fall time, and described Tcp is the sampling pulse cycle; Described sampling input distributor circuit is made up of amplifier and switching network; Described each storage unit circuit forms by an electric capacity; Described output select circuit is made up of the switching network of other amplifier and controlled time shift; To input amplifier input signal, complete the conversion of high input impedance to low output impedance by input amplifier; By input switch network by through conversion sampled signal cycle assignment in N electric capacity; Described output switch network is after Td/2 time delay, and circulation is exported V from N electric capacity
tD; Output amplifier completes the conversion of high input impedance to low output impedance; The switching network of controlled time shift has been used for the output of sampled signal signal after Td/2 time delay to select, thereby reaches the time shift circuit function of controlled time shift.
Further improvement as the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous of the present invention, discontinuous mode is surveyed: the time shift circuit of described controlled time shift comprises sampling input distributor circuit, a N storage unit circuit and output select circuit; The N frequency doubling clock C that described self-learning module is Td/2N according to the time span generation cycle of Td/2 pulse width signal
pN; Described N frequency doubling clock C
pNfor the clock of sampling input distributor circuit and output select circuit; The clock of described output select circuit started than the input clock postponement N cycle of sampling input distributor circuit, and corresponding output signal ratio input signal has postponed the Td/2 time; The concrete N value of described N frequency multiplier circuit is determined by the number of storage unit circuit.
Further improvement as the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous of the present invention, discontinuous mode is surveyed: described controlled time shift time shift circuit by N sampling holder S/H and accordingly when N controllable pulse shift circuit CTD form with tube shaped; Described
described Tdmax is maximum resonance Td fall time, and described Tcp is the sampling pulse cycle; When described controllable pulse, shift circuit CTD receives the time shift of input pulse rising edge startup Δ T pulse on the one hand; Receive on the other hand Td/2/N order, make the corresponding Td/2/N of Δ T pulse time shift; When described controllable pulse, shift circuit CTD, on the one hand according to receiving input pulse rising edge output sampling pulse, makes corresponding sampling holder S/H carry out sampling and keeps operation; On the other hand according to receiving the input of input pulse rising edge output through the pulse of Δ T time delay shift circuit CTD during as next controllable pulse.
Further improvement as the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous of the present invention, discontinuous mode is surveyed: receive Td/2/N order and make the mode of circuit of the corresponding Td/2/N of Δ T pulse time shift as follows: fixing current source Is is charged to capacitor C c, by the capacitance voltage V in charging process
ccthrough the comparator voltage V corresponding with Td/2/N pulse-width control signal
td/2/Nrelatively; As capacitance voltage V
ccbe greater than V
td/2/N, comparator is level"1" by level "0" saltus step, produces the pulse through Δ T time delay; Described capacitance voltage V
ccdepositing switch short circuit by the state of comparator control is zero, deposits switch and opens fixed current source Is to capacitor C c charging operations until receive input pulse rising edge reset mode.
Further improvement as the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous of the present invention, discontinuous mode is surveyed: described S/H sampling hold circuit is made up of the maintained switch of sampling, electric capacity and amplifier; Described amplifier has been used for input and output impedance transformation, i.e. input is high resistant and to export be low-resistance.
Further improvement as the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous of the present invention, discontinuous mode is surveyed: described controlled time shift time shift circuit by N sampling holder S/H and accordingly when N controllable pulse shift circuit CTD form with tube shaped; Time shift circuit and M sampling holder S/H and corresponding M the TD of shift circuit when fixing of described controlled time shift form weighted average circuit with tube shaped; Described controlled time shift time shift circuit the total time shift of maximum of controlled time shift be N × TCP, weighted average is the weighted average of M sampling holder S/H output; Described M is that required average is determined.
Advantage of the present invention is as follows:
One, be the impact of resonance Td fall time on sampled point that takes into full account the existing non-causal operation after the flex point that former limit winding voltage declines and introduce the precision problem of sampled voltage.
Two, obtain accurate Td/2 value by the self study process of a switch periods and accurately revise output sampled voltage.Because resonance Td fall time is by former limit magnetizing inductance L
mparasitic capacitance C with power switch
rdetermine, this Td/2 value obtaining by the self study process of a switch periods is quite stable.
Three, can be when existing shift circuit be weighted average to output sampled voltage and improve the reliability and stability of sampling and outputting voltage.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
Fig. 1 flyback power converter is operated in the U under critical discontinuous mode
cRand I
lMtime-domain diagram;
Corresponding auxiliary (or former limit) the winding voltage V of Fig. 2 the present invention
cRwith through time shift circuit output voltage V
tD;
Fig. 3 functional block block diagram of the present invention;
Fig. 4 self-learning module instantiation of the present invention circuit diagram;
The time shift circuit instantiation circuit diagram of the controlled time shift of Fig. 5 the present invention;
Fig. 6 sample circuit instantiation of the present invention circuit diagram;
Fig. 7 weighted average instantiation of the present invention circuit diagram;
Fig. 8 instantiation 1 circuit diagram of the present invention;
Fig. 9 instantiation 2 circuit diagrams of the present invention;
The time shift circuit instantiation circuit two of the controlled time shift of Figure 10;
Figure 11 adopts the time shift circuit instantiation circuit of N times of frequency delay.
Embodiment
Obtain accurate 1/2nd resonance Td fall time, i.e. Td/2 by auxiliary (or former limit) winding voltage self study flyback power converter being operated under critical discontinuous and discontinuous mode.By the known Td of formula (1) only with former limit magnetizing inductance L
mparasitic capacitance C with power switch
rrelevant.In the time obtaining accurate Td/2, by auxiliary correspondence (or former limit) winding voltage V
cRwaveform is more than or equal to Td/2(as shown in Figure 2 through the time shift circuit time shift of controlled time shift).At auxiliary (or former limit) the winding voltage V of correspondence
cRwhen waveform decline zero passage, to controlled time shift time shift circuit output voltage V
tDsample.103 moment sampling and outputting voltage V as shown in Figure 2
s/Hbe the reflected voltage V on the winding of former limit
o_REFL, the reflected voltage V on the winding of former limit
o_REFLcan accurately characterize the output voltage V of this flyback power converter
o.
The output voltage being operated under critical discontinuous and discontinuous mode for flyback power converter of the present invention can be made up of following functional block by assisting the detection of (or former limit) winding voltage carry out accurately detection scheme: self-learning module 1, and by flyback power converter being operated in to auxiliary (or former limit) the winding voltage V under critical discontinuous and discontinuous mode
cRself study obtains accurate 1/2nd resonance Td fall time, i.e. Td/2; The time shift circuit 2 of controlled time shift, can be controlled by the output Td/2 of self-learning module 1; Sample circuit 3, be controlled by self-learning module 1 and to controlled time shift time shift circuit 2 output V
tDoutput V samples
s/H.
Main performing step is as follows:
The first step, self-learning module 1 receive auxiliary (or former limit) winding voltage V
cR, and to V
cRvoltage waveform is analyzed, and the Td/2 of this place output of output Td/2(is pulsewidth amount Td/2) and sampling inhibit signal CP
s/H;
The time shift circuit 2 of second step, controlled time shift receives auxiliary (or former limit) winding voltage V
cR, and the pulsewidth amount Td/2 exporting according to self-learning module 1 will assist (or former limit) winding voltage V
cRcarry out corresponding time shift and export V
tD;
The 3rd step, sample circuit 3 are at self-learning module 1 output sampling inhibit signal CP
s/Htime, the V that the time shift circuit 2 of controlled time shift is exported
tDthe maintenance of sampling, its output voltage V
s/Hthe reflected voltage V on the winding of former limit
o_REFL, the reflected voltage V on the winding of former limit
o_REFLcan accurately characterize the output voltage V of flyback power converter
o.
By following narration, the former frontier inspection of the output voltage of more concrete description inverse excitation type converter critical discontinuous of the present invention, discontinuous mode is surveyed.
As shown in Fig. 4 (the instantiation circuit diagram of self-learning module 1 of the present invention), self-learning module 1 is by there being two comparator C OMP1, COMP2, and logical AND gate and differential circuit form; Differential circuit is by C(electric capacity), R(resistance) and OP(amplifier) form.
Auxiliary (or former limit) winding voltage V
cRthrough " 1 " signal (104 points in Fig. 2) of comparator C OMP2 export resonance decline zero passage, comparator C OMP2 is output as level"1", comparator C OMP2 output sampled signal CP
s/Hand open logical AND gate and export Td/2 pulsewidth rising edge.
Auxiliary (or former limit) winding voltage V
cRthrough differential circuit output V
cRthe negative slope (because the negative function of amplifier OP is exported positive slope value, this also makes comparator C OMP1 be output as level"1") of resonance decline (at Fig. 2 from 102 to 105).Comparator C OMP1, COMP2 output is level"1", and logical AND gate output keeps level"1".
Work as V
cRthe negative slope that resonance declines is zero or while transferring positive slope (105 points in Fig. 2) to, comparator C OMP1 is output as " 0 ", and makes one of logical AND gate be input as " 0 ", so that logical AND gate is output as " 0 "; To close corresponding pulsewidth be exactly corresponding Td/2 pulsewidth by being opened to for logical AND gate output.
The input signal of above-described self-learning module 1 is auxiliary (or former limit) winding voltage V
cRvoltage, the output signal of self-learning module 1 is respectively sampled signal CP
s/H(comparator C OMP2 output sampled signal CP
s/H) and Td/2 pulsewidth (logical AND gate output is closed corresponding pulsewidth by being opened to).
As shown in Fig. 5 (the controlled time shift of the present invention time shift circuit 2 instantiation circuit diagrams); Controlled time shift time shift circuit 2 by N(Fig. 5, N=5) in individual sampling holder S/H and corresponding N(Fig. 5, N=5) shift circuit CTD forms with tube shaped when individual controllable pulse; The frequency of sampling pulse CP be according to Nai Kuisi frequency principle select, be sampled the twice of signal highest frequency more than; When the cycle T of sampling pulse CP
cPdetermine, controlled time shift time shift circuit 2 controllable pulse time shift circuit CTD maximum time shift time Δ T
mAXmust be less than T
cP:
△T
MAX≤T
CP （2）
For the maximum output pulse width amount Td requiring
mAX/ 2 and the cycle T of sampling pulse CP
cP, number N is for forming time can be expressed as of shift circuit CTD when sampling holder S/H in shift circuit 2 and controllable pulse of controlled time shift:
When controllable pulse, shift circuit CTD has two inputs, and two outputs are as follows respectively;
The first input is according to the input pulse rising edge receiving, and starts the time shift of Δ T pulse;
The second input is according to the Td/2/N order receiving, and makes the corresponding Td/2/N of Δ T pulse time shift;
The first output is according to the input pulse rising edge output sampling pulse receiving, and makes corresponding sampling holder S/H carry out sampling and keeps operation;
The second output is the pulse through Δ T time delay according to the input pulse rising edge output receiving, the input of shift circuit CTD during as next controllable pulse.
In the above (second input), receive Td/2/N order and make the circuit implementation of Δ T pulse time shift correspondence Td/2/N as follows:
1, a fixed current source Is is charged to a capacitor C c, and produce capacitance voltage VCc;
2, capacitance voltage VCc is through the comparator voltage VTd/2/N comparison corresponding with Td/2/N pulse-width control signal; In the time that VCc is greater than VTd/2/N, comparator is level"1" by level "0" saltus step, produces the pulse through Δ T time delay;
3, to deposit switch short circuit by the state of comparator control be zero to described capacitance voltage VCc, resets until receive input pulse rising edge, and state is deposited switch and just reopened the charging operations of fixed current source Is to capacitor C c.
Instantiation circuit diagram as shown in Fig. 6 (above-described sample circuit 3 is sampling holder S/H); Sample circuit 3 is made up of sampling maintained switch, electric capacity and amplifier.Amplifier has been used for input and output impedance transformation, i.e. input is high resistant and to export be low-resistance.Can realize with the instantiation circuit of the sample circuit 3 shown in Fig. 6 at the S/H sampling holder shown in Fig. 5 (being the time sampling holder S/H in shift circuit 2 of controlled time shift).
As shown in Fig. 7 (time shift of controlled time shift and weighted average instantiation circuit diagram); Controlled time shift time shift circuit 2 by N(Fig. 7, N=3) in individual sampling holder S/H and corresponding N(Fig. 7, N=3) shift circuit CTD forms with tube shaped when individual controllable pulse; Controlled time shift time shift circuit 2 and M(Fig. 7 in, M=2) in individual sampling holder S/H and corresponding M(Fig. 7, M=2) individual when fixing shift circuit TD form weighted average circuit with tube shaped.This controlled time shift time shift circuit 2 the total time shift of maximum of controlled time shift be 3 × TCP, weighted average is the weighted average of two sampling holder S/H outputs.If require the reliability and stability of higher sampling and outputting voltage, can increase M value and reach.Time shift circuit output voltage VTD shown in Fig. 2 is average weighted through M=3, obviously due to average weighted effect, and the ripple of the ripple of output voltage V TD is less than auxiliary (or former limit) winding voltage VCR voltage.
Time the instantiation circuit of shift circuit 2 and the instantiation circuit of sample circuit 3 of the instantiation circuit of self-learning module 1, controlled time shift are connected and just can obtain instantiation circuit diagram 8 of the present invention by the functional block block diagram of the present invention shown in Fig. 3; By the time shift of the instantiation circuit of self-learning module 1, controlled time shift and weighted average instantiation circuit (controlled time shift time shift circuit 2 weighted average circuit) instantiation circuit and the instantiation circuit of sample circuit 3 connect and just can obtain instantiation circuit diagram 9 of the present invention by the functional block block diagram of the present invention shown in Fig. 3.
As shown in figure 10, realize the time shift circuit 2 of the controlled time shift that cost is lower for another; The concept of its realization is to utilize the concept of cycle signal memory.Specific as follows:
The time shift circuit 2 of controlled time shift as shown in figure 10 herein comprises sampling input distributor circuit 21, a N storage unit circuit 22 and output select circuit 23; Sampling input distributor circuit 21 in succession N sampling input sample signal cycle is assigned to this N storage unit circuit 22, thereby output select circuit 23 circulates and selects output to reach the time shift circuit function of controlled time shift this N storage unit circuit 22 after Td/2 time delay.
Above-described sampling input distributor circuit 21 is made up of amplifier and switching network, and wherein amplifier completes the translation function of high input impedance to low output impedance; Switching network has been used for N sampling input sample signal cycle to be assigned to the function that N storage unit circuit goes; Each storage unit circuit 22 is all made up of an electric capacity, and each electric capacity receives sampled input signal through the switching network of sampling input distributor circuit 21 respectively; Output select circuit 23 is made up of the switching network of other amplifier and controlled time shift, described other amplifier has been the translation function of high input impedance to low output impedance, the switching network of controlled time shift is for completing, the output of sampled signal signal after Td/2 time delay to be selected, thereby reaches the time shift circuit function of controlled time shift.
The time time delay of shift circuit 2 in concrete enforcement of controlled time shift, can also realize by the concept of frequency multiplier circuit, shown in Figure 11:
Self-learning module 1(is as shown in Figure 4) obtain Td/2 pulse width signal, give birth to according to the time span Td/2 of this pulse width signal the N frequency doubling clock C that one-period is Td/2N
pN, with this clock C
pNselect the clock of circuit 23 ends as sampling input distributor circuit 21 ends, output, the clock of output select circuit 23 ends started than the clock postponement cycle of sampling input distributor circuit 21 ends, and so corresponding output signal ratio input signal has postponed the Td/2 time.
The concrete N value of N frequency multiplier circuit is determined by the number of storage unit circuit 22.This time shift circuit implementing method ball bearing made using cost is low, and time delay is difficult for makeing mistakes, and storage unit circuit 22 numbers are less.
Finally, it is also to be noted that, what more than enumerate is only a specific embodiment of the present invention.Obviously, the present invention is limited to above embodiment, can also have many distortion.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention, all should think protection scope of the present invention.
Claims (8)
1. the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous, discontinuous mode is surveyed, and comprises time shift circuit (2) and the sample circuit (3) of self-learning module (1), controlled time shift; It is characterized in that: the first step: self-learning module (1) receives auxiliary or former limit winding voltage V
cR, and to V
cRafter voltage waveform is analyzed, output 1/2nd resonance Td fall time and sampling inhibit signal CP
s/H;
Second step: the time shift circuit (2) of controlled time shift receives auxiliary or former limit winding voltage V
cR, and will assist or former limit winding voltage V according to 1/2nd resonance Td fall time of self-learning module (1) output
cRcarry out corresponding time shift 1/2nd resonance Td fall time, output V
tD;
The 3rd step: sample circuit (3) is at self-learning module (1) output sampling inhibit signal CP
s/Htime, the V of time shift circuit (2) output to controlled time shift
tDsample maintenance output voltage V
s/H;
Described output voltage V
s/Hthe reflected voltage V on the winding of former limit
o_REFL, by the reflected voltage V on the winding of former limit
o_REFLcan accurately characterize the output voltage VO of flyback power converter.
2. the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous according to claim 1, discontinuous mode is surveyed, and it is characterized in that: described self-learning module (1) is by comparator C OMP1, comparator C OMP2, and logical AND gate and differential circuit form; Described differential circuit is by capacitor C, and resistance R and amplifier OP form;
Assist or former limit winding voltage V
cRthrough " 1 " signal of comparator C OMP2 export resonance decline zero passage;
Assist or former limit winding voltage V
cRthrough differential circuit output V
cRthe negative slope that resonance declines;
Because amplifier OP negative function is exported positive slope value, make comparator C OMP1 be output as level"1";
Comparator C OMP1, COMP2 output is level"1", and logical AND gate output keeps level"1";
Work as V
cRthe negative slope that resonance declines is zero or while transferring positive slope to, comparator C OMP1 is output as " 0 ", and makes one of logical AND gate be input as " 0 ", and makes logical AND gate be output as " 0 ";
Logical AND gate output closes by being opened to 1/2nd resonance Td fall time pulsewidths that corresponding pulsewidth is exactly correspondence.
3. the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous according to claim 2, discontinuous mode is surveyed, and it is characterized in that: the time shift circuit (2) of described controlled time shift comprises sampling input distributor circuit (21), a N storage unit circuit (22) and output select circuit (23);
Described
described Tdmax is maximum resonance Td fall time, and described Tcp is the sampling pulse cycle;
Described sampling input distributor circuit (21) is made up of amplifier and switching network; Described each storage unit circuit (22) forms by an electric capacity; Described output select circuit (23) is made up of the switching network of other amplifier and controlled time shift;
To input amplifier input signal, complete the conversion of high input impedance to low output impedance by input amplifier;
By input switch network by through conversion sampled signal cycle assignment in N electric capacity;
Described output switch network is after Td/2 time delay, and circulation is exported V from N electric capacity
tD;
Output amplifier completes the conversion of high input impedance to low output impedance;
The switching network of controlled time shift has been used for the output of sampled signal signal after Td/2 time delay to select, thereby reaches the time shift circuit function of controlled time shift.
4. the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous according to claim 2, discontinuous mode is surveyed, and it is characterized in that: the time shift circuit (2) of described controlled time shift comprises sampling input distributor circuit (21), a N storage unit circuit (22) and output select circuit (23);
The N frequency doubling clock C that described self-learning module (1) is Td/2N according to the time span generation cycle of Td/2 pulse width signal
pN;
Described N frequency doubling clock C
pNfor the clock of sampling input distributor circuit (21) and output select circuit (23);
The clock of described output select circuit (23) started than the input clock postponement N cycle of sampling input distributor circuit (21), and corresponding output signal ratio input signal has postponed the Td/2 time;
The concrete N value of described N frequency multiplier circuit is determined by the number of storage unit circuit (22).
5. the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous according to claim 2, discontinuous mode is surveyed, and it is characterized in that: the time shift circuit (2) of described controlled time shift by N sampling holder S/H and accordingly when N controllable pulse shift circuit CTD form with tube shaped;
Described
described Tdmax is maximum resonance Td fall time, and described Tcp is the sampling pulse cycle;
When described controllable pulse, shift circuit CTD receives the time shift of input pulse rising edge startup Δ T pulse on the one hand;
Receive on the other hand Td/2/N order, make the corresponding Td/2/N of Δ T pulse time shift;
When described controllable pulse, shift circuit CTD, on the one hand according to receiving input pulse rising edge output sampling pulse, makes corresponding sampling holder S/H carry out sampling and keeps operation;
On the other hand according to receiving the input of input pulse rising edge output through the pulse of Δ T time delay shift circuit CTD during as next controllable pulse.
6. the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous according to claim 5, discontinuous mode is surveyed, and it is characterized in that: receive Td/2/N order and make the mode of circuit of Δ T pulse time shift correspondence Td/2/N as follows:
Fixing current source Is is charged to capacitor C c, by the capacitance voltage V in charging process
ccthrough the comparator voltage V corresponding with Td/2/N pulse-width control signal
td/2/Nrelatively;
As capacitance voltage V
ccbe greater than V
td/2/N, comparator is level"1" by level "0" saltus step, produces the pulse through Δ T time delay;
Described capacitance voltage V
ccdepositing switch short circuit by the state of comparator control is zero, deposits switch and opens fixed current source Is to capacitor C c charging operations until receive input pulse rising edge reset mode.
7. the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous according to claim 6, discontinuous mode is surveyed, and it is characterized in that: described S/H sampling hold circuit is made up of the maintained switch of sampling, electric capacity and amplifier;
Described amplifier has been used for input and output impedance transformation, i.e. input is high resistant and to export be low-resistance.
8. the former frontier inspection of the output voltage of inverse excitation type converter critical discontinuous according to claim 7, discontinuous mode is surveyed, and it is characterized in that: the time shift circuit (2) of described controlled time shift by N sampling holder S/H and accordingly when N controllable pulse shift circuit CTD form with tube shaped;
The time shift circuit (2) of described controlled time shift and M sampling holder S/H and corresponding M the TD of shift circuit when fixing form weighted average circuit with tube shaped;
The total time shift of maximum of the controlled time shift of the time shift circuit (2) of described controlled time shift is N × TCP, and weighted average is the weighted average of M sampling holder S/H output;
Described M is that required average is determined.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110044076A1 (en) * | 2009-08-20 | 2011-02-24 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for load compensation with primary-side sensing and regulation for flyback power converters |
| CN102801325A (en) * | 2011-05-23 | 2012-11-28 | 广州昂宝电子有限公司 | System and method for regulating switching frequency and peak current of power converter |
| CN203014696U (en) * | 2012-12-20 | 2013-06-19 | 无锡硅动力微电子股份有限公司 | Circuit capable of realizing constant-current controlling in primary-side controlled switching power converter |
-
2014
- 2014-03-04 CN CN201410076760.0A patent/CN103904866B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110044076A1 (en) * | 2009-08-20 | 2011-02-24 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for load compensation with primary-side sensing and regulation for flyback power converters |
| CN102801325A (en) * | 2011-05-23 | 2012-11-28 | 广州昂宝电子有限公司 | System and method for regulating switching frequency and peak current of power converter |
| CN203014696U (en) * | 2012-12-20 | 2013-06-19 | 无锡硅动力微电子股份有限公司 | Circuit capable of realizing constant-current controlling in primary-side controlled switching power converter |
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