CN105515413A - Output voltage sampling circuit and method based on AC-DC converter - Google Patents
Output voltage sampling circuit and method based on AC-DC converter Download PDFInfo
- Publication number
- CN105515413A CN105515413A CN201510895297.7A CN201510895297A CN105515413A CN 105515413 A CN105515413 A CN 105515413A CN 201510895297 A CN201510895297 A CN 201510895297A CN 105515413 A CN105515413 A CN 105515413A
- Authority
- CN
- China
- Prior art keywords
- circuit
- voltage
- output
- signal
- exports
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/145—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/155—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
- H02M7/162—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration
- H02M7/1623—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit
- H02M7/1626—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit with automatic control of the output voltage or current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention relates to an output voltage sampling circuit and method based on an AC-DC converter. The circuit comprises: an output voltage detection circuit, an error amplifier, a pulse width modulation controller, a demagnetizing time detection circuit and a timer; wherein the output voltage detection circuit is used for sampling and maintaining an FB signal and outputting a feedback voltage; the error amplifier can compare the feedback voltage and a reference voltage and output a first voltage; the demagnetizing time detection circuit can detect the demagnetizing time of the FB signal and output a first detection result; the timer can control the pulse width modulation controller according to the first detection result and output a control value; and the pulse width modulation controller can adjust the pulse width of a pulse width modulation signal according to the control value and the first voltage and output a gate signal. Under the condition of outputting constant voltage, the Gate signal opening time can be modulated through a combined effect of the pulse width modulation (PWM) controller, the demagnetizing time detection circuit and the timer, and the FB waveform can be accurately collected in any condition.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, be specifically related to a kind of output voltage sampling circuit based on AC-DC converter and method.
Background technology
In AC-DC converter circuit, can be realized by the voltage of transformer inductance of sampling the detection of output voltage, and primary inductance voltage can assist winding to be transferred to pulse modulation controller by transformer.Fig. 1 is the structural representation of the output voltage sampling circuit in a kind of AC-DC converter of the prior art.As shown in Figure 1, resistance R1 represent the series parasitic resistance of secondary winding and the series parasitic resistance of output lead and.Under the line voltage that input is identical, the load current of different output loading is different, and now the output voltage of secondary winding is distinguishing.
When output loading is heavier, the voltage of each node or current waveform are as shown in Figure 2.Output voltage is obtained by the waveform sampling of the feedback signal FB after auxiliary winding and resistor voltage divider network R2, R3.Within the inductance degaussing time (Tdmg), FB voltage is directly proportional to output voltage, i.e. FB=k*Vout, and scale parameter k is:
wherein, Ns is transformer secondary output umber of turn, and Na is that umber of turn assisted by transformer.Due to the existence of transformer leakage inductance, in the moment that the degaussing time starts, the voltage waveform of FB can produce a decay concussion, carries out detection during this period there will be metrical error to FB waveform.Therefore after the degaussing time starts a period of time (front end blanking time LEB) is needed effective detection time to start.When output loading is lighter, the opening time of gate signal Gate time larger relative to load resistance as shown in Figure 3, Gate now reduces, and the corresponding reduction of peak current of primary inductance, this will make the degaussing time also reduce.When load changes to enough hour, the degaussing time can be reduced to FB waveform does not have the effective sampling time, now cannot detect output voltage.
Summary of the invention
In order to solve the problem, on the one hand, the invention provides a kind of output voltage sampling circuit based on AC-DC converter, this circuit comprises: output voltage detecting circuit, error amplifier, PDM keyer, degaussing time detection circuit and timer, output voltage detecting circuit is used for sampling and keeps FB signal, output feedack voltage; Error amplifier is used for feedback voltage and reference voltage to compare, and exports the first voltage; Degaussing time detection circuit is used for detecting the degaussing time of FB signal, exports the first testing result; Timer is used for controlling PDM keyer according to the first testing result, exports controlling value; PDM keyer is used for according to controlling value and the first voltage, the pulsewidth of adjusting pulsewidth modulation signal, out gate signal.
Further, degaussing time detection circuit detects FB signal, is specially; When the degaussing time is greater than the front end blanking time, the first testing result that degaussing time detection circuit exports is the first level, then the controlling value that timer exports is the first level; When the degaussing time is less than the front end blanking time, the first testing result that degaussing time detection circuit exports is second electrical level, then the controlling value that timer exports is second electrical level.
Further, PDM keyer comprises simulation accumulator circuit; One input of simulation accumulator circuit receives the first voltage of error amplifier circuit output, the controlling value that another input receive counter exports, and output exports the second voltage; PDM keyer is used for according to controlling value and the first voltage, the pulsewidth of adjusting pulsewidth modulation signal, out gate signal; Modulate according to the modulation signal of the second voltage to PDM keyer, out gate signal.
Further, simulate accumulator circuit to comprise: operational amplifier, resistance, variable current source circuit and asynchronous timer circuit; Wherein, in variable current source circuit, every bar branch road is composed in series by a switch and a current source; The controlling value of one input receive counter output of asynchronous timer circuit, another input receives modulation signal, and output exports the control signal controlling variable current source circuit; Switch on each branch road of variable current source circuit is controlled by the control signal that asynchronous timer circuit exports, and one end of variable current source circuit is by current source ground connection, and the other end of variable current source circuit is connected with one end of resistance by switch; The other end of resistance is connected with the output of operational amplifier; Operational amplifier one input receives the first voltage, and another input receives the node voltage of resistance and variable current source circuit, and output exports the second voltage.
Further, asynchronous timer circuit comprises: the trigger corresponding with branch road each in variable current source circuit, NOR gate and with door.
Further, in variable current source circuit, the current source of each branch road arranges by certain coded system.
Further, PDM keyer comprises delay circuit; Delay circuit comprises inverter circuit and asynchronous timer circuit; Inverter circuit comprises: analog inverter, inverter and the parallel circuits be made up of electric capacity and switch; Wherein, analog inverter is for controlling delay time; In parallel circuits, every bar branch road comprises a switch and an electric capacity, and one end of parallel circuits is connected to the input of inverter by switch, the other end of parallel circuits passes through capacity earth; The output of inverter is as the output of delay circuit; The input of analog inverter is as the input of delay circuit, and the output of analog inverter is connected to the input of inverter;
Asynchronous timer circuit one input receives the controlling value that timer exports, and exports control signal, for controlling the break-make of branch road in parallel circuits; Inverter circuit controls the delay time of delay circuit by the charging interval of electric capacity in parallel circuits; By controlling the delay time of delay circuit, the modulation signal of PDM keyer is modulated, out gate signal.
Further, analog inverter comprises current source and switching tube, the grid of switching tube as the input of delay circuit, source ground, drain electrode is connected to the input of inverter with the intersection point of the output of current source, the input termination power of current source; When switching tube conducting, the intersection point output low level of switching tube and current source; When switching tube ends, current source by drain electrode corresponding capacitor charging in parallel circuits of switching tube, switching tube and current source intersection point export high level.
Further, asynchronous timer circuit comprises: the trigger corresponding with each branch road of parallel circuits in inverter circuit, NOR gate and with door.
On the other hand, the invention provides a kind of output voltage method of sampling based on AC-DC converter, the method comprises:
Sampling and maintenance FB signal, output feedack voltage; Feedback voltage and reference voltage are compared, exports the first voltage; The degaussing time of FB signal is detected, exports the first testing result; According to the first testing result, PDM keyer is controlled, export controlling value; According to controlling value and the first voltage, the pulsewidth of adjusting pulsewidth modulation signal, out gate signal.
Further, FB signal is detected, is specially; When the degaussing time is greater than the front end blanking time, the first testing result is the first level, then controlling value is the first level; When the degaussing time is less than the front end blanking time, the first testing result is second electrical level, then controlling value is second electrical level.
The embodiment of the present invention makes this circuit when exporting constant voltage, by the acting in conjunction of pulse-width modulation PWM controller, degaussing time detection circuit and timer, the Gate unblanking time is modulated, achieves this circuit and under any circumstance can carry out collecting work to FB ripple accurately.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the output voltage sampling circuit in a kind of AC-DC converter of the prior art;
Fig. 2 is voltage or the current waveform schematic diagram of Fig. 1 each node when output loading resistance is larger;
Fig. 3 is voltage or the current waveform schematic diagram of Fig. 1 each node when output loading resistance is less;
A kind of output voltage sampling circuit structural representation based on AC-DC converter that Fig. 4 provides for the embodiment of the present invention;
Fig. 5 is the structural representation of Acquisition Circuit in Fig. 4;
The waveform schematic diagram that the degaussing time detection circuit output signal that Fig. 6 provides for the embodiment of the present invention outputs signal with timer;
The waveform schematic diagram that the FB signal that Fig. 7 provides for the embodiment of the present invention, degaussing time detection circuit output signal outputs signal with timer;
Fig. 8 a is a kind of in circuit shown in Fig. 5 specific implementation structural representation of PWM controller circuit;
Fig. 8 b is the specific implementation structural representation of a kind of analog adder circuit in Fig. 8 a;
Fig. 9 is the waveform schematic diagram of pwm signal and opamp-output signal in circuit shown in Fig. 8 b;
Figure 10 is the specific implementation structural representation of PWM controller circuit another kind of in circuit shown in Fig. 5;
The method flow diagram that Figure 11 samples for a kind of output voltage based on AC-DC converter that the embodiment of the present invention provides.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
A kind of output voltage sampling circuit structural representation based on AC-DC converter that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, this circuit comprises: constant-current control circuit and auxiliary winding circuit; Wherein, constant-current control circuit comprises bridge rectifier, electric capacity C1, transformer T1, power switch pipe M1, rectifier diode D1, resistance R1, electric capacity C2 and load RL; Auxiliary winding circuit comprises resistance R2, resistance R3 and sample circuit 401.
In main winding, line voltage is transported on the primary inductance of transformer T1 through bridge rectifier, electric capacity C1, and primary inductance is connected with power switch pipe M1 ground connection.Power switch pipe M1 activates and produces Gate signal by outside start-up circuit, now primary inductance circuit produces main winding current Ip, by the coupling between the primary and secondary level of transformer T1, secondary winding producing induced current Is through the series circuit of rectifier diode D1 and resistance R1 acts on load RL.When secondary winding have electric current I s by time, the voltage waveform of auxiliary winding is proportional to output voltage, and sample circuit 401 gathers the waveform of FB feedback, and obtain output voltage Vout by the relation FB=k*Vout of FB feedback signal and output voltage, wherein scale parameter k is:
Fig. 5 is the structural representation of Acquisition Circuit in Fig. 4.As shown in Figure 5, this sample circuit 401 comprises: output voltage detecting circuit 501, error amplifier 502, pulse-width modulation PWM controller 503, degaussing time detection circuit 504 and timer 505.
Output voltage detecting circuit 501, for sampling and maintenance feedback FB signal, output feedack voltage VFB, its input receives feedback FB signal, and output is connected with the in-phase input end of error amplifier 502;
Error amplifier 502, for feedback voltage V FB and reference voltage Vref being compared, exports DC level signal EAout, its inverting input access reference voltage Vref, and output is connected with an input of WM controller 503,
Another input of PWM controller 503 is connected with the output of timer 505, and the direct current signal EAout for exporting according to error amplifier 502 adjusts the pulse duration of pwm signal, and its output exports Gate signal;
The input of degaussing time detection circuit 504 is connected with the input of output voltage detecting circuit 501, and output is connected with the input of timer 505, for detecting the degaussing time of feedback FB waveform, exports SnHOK level signal.
Further, because load is different, FB waveform may produce decay concussion, and within the degaussing time, form the LEB time period, the degaussing time of degaussing time detection circuit 504 to this FB waveform is detected.
Timer 505, for detecting the output signal of degaussing time detection circuit 504, exports control signal Tdmg.
The course of work of circuit shown in Fig. 5 is as follows:
Output voltage detecting circuit 501 pairs of FB signals are sampled, detect and keep this signal, exporting the voltage VFB of FB signal, and this voltage is exported to the in-phase input end of error amplifier 502, voltage VFB and reference voltage Vref are compared, exports DC level signal EAout; Degaussing time detection circuit 504 pairs of FB signals carry out degaussing time detecting: if the degaussing time be greater than the LEB time period, degaussing time detection circuit 504 exports high level SnHOK=1, timer 505 exports high level Tdmg=1, and the opening time of the Gate signal trigger power switching tube M1 of now PWM controller 503 output is determined by the EAout inputted completely; If the degaussing time is less than the LEB time period, degaussing time detection circuit 501 exports as low level SnHOK=0, timer 505 start-up study function makes Tdmg=1 continue the tf time period, the tf time period is determined by the internal structure of timer 505, can be 10-100 PWM cycle also can be 1-2mS, within the tf time period, the opening time of Gate signal trigger power switching tube M1 is still by EAout signal deciding, after the tf time period, timer 505 exports and becomes low level Tdmg=0, and wave form varies as shown in Figure 6.
After the tf time period, timer 505 exports and becomes low level Tdmg=0, and the opening time of the output Gate signal trigger power switching tube M1 of PWM controller 503 increases gradually, until Tdmg=1 on the basis by EAout signal deciding.
Further, when the degaussing time is less than LEB time period, output voltage detecting circuit 501 can not be sampled to FB signal, it exports SnHOK=0, the output Tdmg=0 of timer 505 after continuing the tf time period, PWM controller 503 forces the opening time of Gate signal is lengthened gradually, be increased to always and make degaussing time long enough, to such an extent as to after output voltage detecting circuit 501 can sample to FB signal, the opening time of Gate signal returns to the state determined by error amplifier in loop, so go round and begin again, waveform as shown in Figure 7.
When Tdmg=0, the scheme that the Gate unblanking time increases gradually is as follows:
Fig. 8 a is a kind of in circuit shown in Fig. 5 specific implementation structural representation of PWM controller circuit.As shown in Figure 8 a, this PWM controller circuit comprises: saw-toothed wave generator 801, comparator 802, with door 803, rest-set flip-flop 804, driver 805 and delay circuit 806 and simulate summation circuit 807
The in-phase input end of comparator 802 is connected to the output of saw-toothed wave generator 801, and inverting input is connected to the output of simulation summation circuit 807; One input of simulation summation circuit 807 receives the EAout of error amplifier 502 output, the Tdmg that another input receive counter 505 exports,
The output of comparator 802 is connected to the input with door 803; The R being connected to rest-set flip-flop 804 with the output of door 803 holds, the S end of rest-set flip-flop 804 is connected with other control circuits in system, the output of rest-set flip-flop 804 is connected with the input of delay circuit 806 with the input of driver 805 respectively, the output of delay circuit 806 is connected to another input with door 803, and the output of driver 805 exports Gate signal.
Simulation summation circuit 807, for improving the average voltage of the EAout signal of error amplifier output, is converted into EAout2 signal; Rest-set flip-flop 804 is for output pwm signal; The minimum opening time of delay circuit 806 control Gate signal, the turn-off time of Gate signal is determined by S end signal.Wherein, according to different control mechanisms, the generation of S end signal can be the set time, also can be determined by external signal.
In one example in which, the specific implementation of PWM is as follows:
If the initial output state of rest-set flip-flop 804 is 0, input state is Set=0, Reset=0.When other control circuits intrasystem trigger S=1, pwm signal is set to 1, and saw-toothed wave generator 801 is discharged into minimum level immediately and charges from minimum level.
When the minimum level that saw-toothed wave generator 801 is discharged is less than or equal to EAout2 level, comparator 802 output low level, other the circuit triggers S=0 in control system, the output signal PWM of rest-set flip-flop remains 1; When the output signal of saw-toothed wave generator 801 is charged to than EAout2 height, comparator 802 exports high level, now exports high level with door 803, and the R end of rest-set flip-flop 804 is input as 1, and pwm signal is reset, PWM=0.When S is triggered 1 next time, the pwm signal of the output of rest-set flip-flop 804 is set to 1 again, and saw-toothed wave generator 801 is again discharged into minimum level immediately and charges from minimum level, and said process repeats again.That is, increase EAout to EAout2, when the minimum level that saw-toothed wave generator is discharged is less than or equal to EAout2 level, the width of pwm signal can increase.Wherein, the periodic triggered RS flip-flop 804 of S end signal, said process periodically repeats, and determines the width of pwm signal in each cycle, and in this process, delay circuit 806 is inoperative.
As PWM=0, no matter the output level of comparator 802 is 1 or 0, and the R being low level rest-set flip-flop 804 with the output of door 803 holds input 0, now keeps PWM=0.Afterwards as S=1, PWM is turned to 1 from 0, and delay circuit 806 can keep output to be 0 in a time period (time of delay) after S=1.
Within above-mentioned time of delay, if the output level of comparator 802 output low level within above-mentioned time of delay, so the course of work of delay circuit on whole PWM does not affect; If the output of comparator 802 is high level, that is, the output of saw-toothed wave generator 801 is higher than EAout2, and so the R=0 of triggered RS flip-flop 804, PWM export as high level.After having crossed above-mentioned delay time, the output level of delay circuit is the R=1 of high level, rest-set flip-flop 804, and now PWM is just set to zero.Determine the minimum opening time of PWM above-mentioned time of delay, therefore, the minimum opening time of delay circuit 806 control Gate signal.
Fig. 8 b is a kind of specific implementation structural representation of simulating summation circuit in Fig. 8 a, and as shown in Figure 8 b, this analog addition circuit 807 comprises operational amplifier op1, resistance R1, variable current source circuit and asynchronous timer circuit.Wherein, in variable current source circuit, every bar branch road is composed in series by a switch and a current source.
The Tdmg of one input receive counter 505 output of asynchronous timer circuit, another input receives the pwm signal that rest-set flip-flop 804 exports, and output exports the control signal controlling variable current source circuit; One end of variable current source circuit is by current source ground connection, and the other end is connected with one end of resistance by switch, and the other end of resistance R1 is connected to the output of operational amplifier op1; The in-phase input end of operational amplifier op1 receives EAout signal, and inverting input receives the node voltage of resistance R1 and variable current source circuit, exports EAout2 signal.
Variable current source circuit comprises current source I0-I4 and interrupteur SW 0-SW4, and be composed in series by a switch and a current source in every bar branch road in this parallel circuits, one end of switch is connected to one end of resistance R1, the other end connect with current source after ground connection.Wherein, current source I0-I4 arranges according to certain coded system, such as, according to 8421 yards of arrangements, i.e. and I4=2*I3=4*I2=8*I1=16*I0.
Asynchronous timer circuit comprise d type flip flop DFF1-DFF5 corresponding with each branch road in variable current source circuit, NOR gate NOR and with door AND; The reversed-phase output of DFF1-DFF5 is connected to self input, the reversed-phase output of DFF1-DFF4 is connected to the clock signal input terminal of next stage, the in-phase output end of DFF1-DFF5 exports the control signal controlling variable current source circuit breaker in middle SW0-SW4, if control signal is that high level switch closes, control signal is that low level switch disconnects, the set end R of DFF1-DFF5 connects, for receiving Tdmg signal.The control signal that DFF1-DFF5 in-phase output end exports is received with the input of door AND, its output is connected to an input of NOR gate NOR, another input of NOR gate NOR receives the pwm signal of rest-set flip-flop 804 output, and output is connected to the clock signal input terminal of DFF1.Wherein, clock signal input terminal input high level is effective.
In one example in which detailed discussion will be done to the course of work of simulation summation circuit 807 below.
The node voltage of the EAout that error amplifier 502 exports by operational amplifier op1 and resistance R1 and variable current source circuit carries out overlap-add procedure, exports EAout2.
As Tdmg=1, show that degaussing time long enough FB signal is correctly sampled, now the R end of asynchronous timer circuit is in high level, DFF1-DFF5 is reset, asynchronous timer circuit does not work, the control signal of in-phase output end output low level, and the interrupteur SW 0-SW4 controlling variable current source circuit disconnects, resistance R1 does not have electric current pass through to produce without pressure drop, now EAout equals EAout2.
As Tdmg=0, show that degaussing time shorter FB signal can not correctly be sampled, now the R end of asynchronous timer circuit is in low level, and the asynchronous timer of DFF1-DFF5 composition is started working.The clock signal of this asynchronous timer circuit is pwm signal, and trailing edge is effective, and namely often through the trailing edge of a PWM, the pressure drop on resistance R1 can increase.Because current source I0-I4 in variable current source circuit arranges according to the order of I4=2*I3=4*I2=8*I1=16*I0, therefore when the output of DFF1-DFF5 in asynchronous timer circuit is by 00000 to 11111 change procedures, the average voltage of EAout2 constantly raises.When the control signal that DFF1-DFF5 exports is all high level, namely when in-phase output end exports and is 1, no matter now pwm signal is high level or low level, by output low level after NOR gate NOR process, asynchronous timer circuit overflows, and the control signal of the now output of DFF1-DFF5 keeps being all high level, until during Tdmg=1, DFF1-DFF5 is reset, then repeats the above-mentioned course of work.
Fig. 9 is the waveform schematic diagram of pwm signal and opamp-output signal in circuit shown in Fig. 8 b.As shown in Figure 9, the trailing edge of pwm signal is effective, and horizontal dotted line represents the EAout signal that operational amplifier op1 exports, and the solid line intersected with it represents EAout2 signal.At initial time, i.e. A point, the voltage waveform of EAout and EAout2 is identical; Within the A-B moment, the trailing edge first time of pwm signal comes interim, the voltage waveform of EAout2 increases certain amplitude on the basis of the voltage waveform of EAout, the trailing edge of each pwm signal arrives afterwards, the voltage waveform of EAout2 all can increase certain amplitude on the basis of previous moment EAout2 voltage waveform, wherein, the size of this amplitude is determined by the pressure drop on resistance R1; Rise in the B moment, the voltage waveform of EAout2 remains unchanged, and now asynchronous timer circuit overflows, the maximum that the pressure drop on resistance R1 can reach for it.
Simulation summation circuit 807 is by variable current source circuit and the acting in conjunction of asynchronous timer circuit, the average voltage of the EAout that error amplifier circuit is exported is forced to be increased to EAout2, EAout2 increases to asynchronous timer circuit always and overflows, when the pressure drop on resistance R1 is its maximum, the operational amplifier op1 output valve EAout2 that adds up also reaches its maximum.Be increased to the process of its maximum at EAout2 from EAout, the pulse duration of PWM is progressively increasing, and namely the opening time of Gate signal increases, and causes the width of degaussing time also progressively increasing accordingly.In this course, if the degaussing time, asynchronous counter was reset when being increased to the sampling Tdmg=1 that can meet FB signal, all current sources quit work, pressure drop on resistance R1 is zero, and the output voltage of operational amplifier op1 returns to its input voltage EAout.Therefore, the maximum that pressure drop on resistance R1 can reach determines the degree that system can regulate, according to the difference of applied environment, such as input voltage range, output voltage, output current scope and transformer turn ratio etc., need the size adjusting the figure place of asynchronous counter, the resistance of R1 and current source I0-I4.When Tdmg signal is in low level again, asynchronous timer circuit again triggers variable current source circuit and carries out work, so goes round and begins again.
Figure 10 is the specific implementation structural representation of PWM controller circuit another kind of in circuit shown in Fig. 5.As shown in Figure 10, this PWM controller circuit comprises: saw-toothed wave generator 1001, comparator 1002, with door 1003, rest-set flip-flop 1004, driver 1005 and delay circuit 1006; Delay circuit 1006 comprises asynchronous timer circuit and inverter circuit 1060.Wherein, inverter circuit 1060 is for carrying pwm signal to door 1003.
Saw-toothed wave generator 1001, comparator 1002, same as above with the course of work with the connected mode of driver 1005 with door 1003, rest-set flip-flop 1004, no longer go to live in the household of one's in-laws on getting married here and tell.
The Tdmg that asynchronous timer circuit one input receive counter 505 exports, another input receives the pwm signal that rest-set flip-flop 1004 exports, and output exports the control signal controlling inverter circuit 1060;
The parallel circuits that inverter circuit 1060 comprises inverter 1061, analog inverter and is made up of electric capacity C0-C4 and interrupteur SW 0-SW4.Wherein, analog inverter comprises current source 1062 and switching tube 1063, for controlling delay time, it should be noted that, in the present embodiment, the minimum value of delay time or initial value can be determined by the parasitic capacitance of current source 1062 self, also can be determined by electric capacity in parallel.
In this parallel circuits, every bar branch road comprises a switch and an electric capacity, and one end of switch is by capacity earth, and the other end is connected to the input of inverter 1061.The output of inverter 1061 is connected to and door 1003 input, the grid of the switching tube 1063 in analog inverter is connected to the output of rest-set flip-flop 1004, source electrode is connected to ground, what drain with the output of current source 1062 is crossing, this intersection point is connected to the input of inverter 1061, the input of current source 1062 is connected to power vd D, and wherein, the course of work of analog inverter is:
When the pwm signal that switching tube 1063 receives is high level, switching tube 1063 drains and conducting between source electrode, because the conducting resistance of switching tube 1063 is very little, therefore its drain electrode output low level, simultaneously because the conducting resistance of 1063 is very little, it is very fast to the velocity of discharge of electric capacity C0-C4, and to be therefore turned to the low level time from high level negligible in the drain electrode of switching tube 1063;
When the pwm signal that switching tube 1063 receives is low level, end between the drain electrode of switching tube 1063 and source electrode, therefore current source 1062 is by the drain electrode of switching tube 1063 to capacitor charging, and drain electrode exports high level.Current source 1062 needs a period of time to capacitor charging, reaches the trigging signal of inverter 1061 after one period of time of delay, and inverter 1061 pairs of incoming levels carry out upset and export.
The control signal that in asynchronous timer circuit, the in-phase output end of DFF1-DFF5 exports controls the disconnection of inverter circuit 1060 breaker in middle SW0-SW4 with closed; Connected mode and the course of work of asynchronous timer circuit are same as above, no longer go to live in the household of one's in-laws on getting married tell at this.
The course of work of delay circuit 1006 is as follows:
As Tdmg=0, asynchronous timer circuit normally works, and exports the level signal from 00000 to 11111, controls the interrupteur SW 0-SW4 in inverter circuit; The pwm signal that rest-set flip-flop 1004 exports is delivered to the input of inverter 1061 by inverter circuit breaker in middle pipe 1063, electric capacity now on the place branch road that closes of current source 1062 pairs of parallel circuits breaker in middle charges, raised by the capacitance voltage charged in charging process, when the voltage of the parallel circuits in inverter circuit reaches trigging signal, as 1/2VDD, inverter 1061 by the level negate of its input signal, and exports to and door 1003;
Delay circuit changes time of delay by asynchronous timer and inverter circuit 1060, to such an extent as to the pulsewidth of pwm signal increases, and namely the opening time of Gate signal increases, and causes the width of degaussing time also progressively increasing accordingly.In this course, if Tdmg=1 when the degaussing time is increased to the sampling that can meet FB signal, asynchronous counter is reset, and electric capacity C0-C4 disconnects, and the time of delay of analog inverter is restored to minimum value or initial value.Therefore, the time length of capacitor charging determines the degree that system can regulate, according to the difference of applied environment, as input voltage range, output voltage, output current scope and transformer turn ratio etc., need the size adjusting the figure place of asynchronous counter, the capacitance of electric capacity C0-C4 and arrangement mode and current source.When Tdmg signal is in low level again, asynchronous timer circuit again trigger inverter circuit carries out work, so goes round and begins again.
The method flow diagram that Figure 11 samples for a kind of output voltage based on AC-DC converter that the embodiment of the present invention provides.Because FB signal is directly proportional to output voltage, thus can obtain output voltage, therefore as shown in figure 11, this method of sampling comprises:
Step S111, reception FB signal, sample to FB signal, output voltage VFB;
Step S112, voltage VFB and reference voltage to be compared, export EAout;
Step S113, reception FB signal, detect the degaussing time of FB signal, export SnHOK;
Be specially, because circuit load is different, FB waveform may produce decay concussion, and within the degaussing time, form the LEB time period, the degaussing time of degaussing time detection circuit to this FB waveform is detected.
Step S114, signal level according to SnHOK, export control signal;
Be specially, when the degaussing time is greater than LEB time period, SnHOK is high level, then the level of control signal is high level; When the degaussing time is less than LEB time period, SnHOK is low level, then the level of control signal is low level.
Step S115, according to control signal and EAout, regulate the pulsewidth of pwm signal, export Gate signal.
The embodiment of the present invention makes this circuit when exporting constant voltage, by the acting in conjunction of pulse-width modulation PWM controller, degaussing time detection circuit and timer, the Gate unblanking time is modulated, achieves this circuit and under any circumstance can carry out collecting work to FB ripple accurately.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. the output voltage sampling circuit based on AC-DC converter, described circuit comprises: output voltage detecting circuit (501), error amplifier (502), it is characterized in that, PDM keyer (503), degaussing time detection circuit (504) and timer (505)
Described output voltage detecting circuit (501), for sampling and maintenance FB signal, output feedack voltage (VBF);
Described error amplifier (502), for described feedback voltage (VBF) and reference voltage (Vref) being compared, exports the first voltage (EAout);
Described degaussing time detection circuit (504), for detecting the degaussing time of described FB signal, exports the first testing result (SnHOK);
Described timer (505), for controlling described PDM keyer (503) according to described first testing result, exports controlling value (Tdmg);
Described PDM keyer (503), for according to described controlling value (Tdmg) and described first voltage, the pulsewidth of adjusting pulsewidth modulation signal, out gate signal (Gate).
2. circuit according to claim 1, is characterized in that, described degaussing time detection circuit (504) is detected described FB signal, is specially;
When the described degaussing time is greater than the front end blanking time, described first testing result (SnHOK) that described degaussing time detection circuit (504) exports is the first level, then the described controlling value (Tdmg) that described timer (505) exports is described first level; When the described degaussing time is less than the described front end blanking time, described first testing result (SnHOK) that described degaussing time detection circuit (504) exports is second electrical level, then the described controlling value (Tdmg) that described timer (505) exports is described second electrical level.
3. circuit according to claim 1, is characterized in that, described PDM keyer (503) comprises simulation accumulator circuit (807); One input of described simulation accumulator circuit (807) receives described first voltage (EAout) that described error amplifier circuit (502) exports, another input receives the described controlling value (Tdmg) that described counter (505) exports, and output exports the second voltage (EAout2);
Described PDM keyer (503), for according to described controlling value (Tdmg) and described first voltage, the pulsewidth of adjusting pulsewidth modulation signal, out gate signal (Gate);
Modulate according to the modulation signal of described second voltage (EAout2) to described PDM keyer (503), export described gate signal (Gate).
4. circuit according to claim 3, is characterized in that, described accumulator circuit comprises: operational amplifier, resistance, variable current source circuit and asynchronous timer circuit; Wherein, in described variable current source circuit, every bar branch road is composed in series by a switch and a current source;
One input of described asynchronous timer circuit receives the described controlling value (Tdmg) that described counter (505) exports, and another input receives described modulation signal, and output exports the control signal controlling described variable current source circuit; Described switch on described each branch road of described variable current source circuit is controlled by the described control signal that described asynchronous timer circuit exports, one end of described variable current source circuit is by described current source ground connection, and the other end of described variable current source circuit is connected with one end of described resistance by described switch; The other end of described resistance is connected with the output of described operational amplifier; Described operational amplifier one input receives described first voltage (EAout), and another input receives the node voltage of described resistance and described variable current source circuit, and output exports described second voltage (EAout2).
5. circuit according to claim 3, is characterized in that, described asynchronous timer circuit comprises: the trigger corresponding with described branch road each in described variable current source circuit, NOR gate and with door.
6. circuit according to claim 4, is characterized in that, described in described variable current source circuit, the described current source of each branch road arranges by certain coded system.
7. circuit according to claim 1, is characterized in that, described PDM keyer (503) comprises delay circuit (1006); Described delay circuit (1006) comprises inverter circuit (1060) and asynchronous timer circuit;
Described inverter circuit comprises: analog inverter, inverter (1061) and the parallel circuits be made up of electric capacity and switch; Wherein, described analog inverter is for controlling delay time; In described parallel circuits, every bar branch road comprises a switch and an electric capacity, and one end of described parallel circuits is connected to the input of described inverter by described switch, and the other end of described parallel circuits is by described capacity earth; The output of described inverter is as the output of described delay circuit (1006); The input of described analog inverter is as the input of described delay circuit (1006), and the output of described analog inverter is connected to the input of described inverter; Described asynchronous timer circuit one input receives the described controlling value that described timer (505) exports, and exports control signal, for controlling the break-make of branch road described in described parallel circuits; Described inverter circuit (1060) controls the described delay time of described delay circuit (1006) by the charging interval of electric capacity described in described parallel circuits;
By controlling the described delay time of described delay circuit (1006), the modulation signal of described PDM keyer (503) being modulated, exporting described gate signal (Gate).
8. circuit according to claim 7, is characterized in that, described analog inverter comprises current source (1062) and switching tube (1063),
The grid of described switching tube (1063) is as the input of described delay circuit (1006), source ground, drain electrode is connected to the input of described inverter (1061) with the intersection point of the output of described current source (1062), the input termination power of described current source (1062);
When described switching tube (1063) conducting, described switching tube (1063) and described current source (1062) intersection point output low level; When described switching tube (1063) ends, described current source (1062) by drain electrode corresponding described capacitor charging in described parallel circuits of described switching tube (1063), described switching tube (1063) and described current source (1062) intersection point export high level.
9. circuit according to claim 7, is characterized in that, described asynchronous timer circuit comprises: the trigger corresponding with each described branch road of parallel circuits described in described inverter circuit, NOR gate and with door.
10., based on an output voltage method of sampling for AC-DC converter, described method comprises:
Sampling and maintenance FB signal, output feedack voltage;
Described feedback voltage and reference voltage are compared, exports the first voltage;
The degaussing time of described FB signal is detected, exports the first testing result;
According to described first testing result, export controlling value;
According to described controlling value and described first voltage, the pulsewidth of adjusting pulsewidth modulation signal, out gate signal.
11. methods according to claim 10, is characterized in that, describedly detect described FB signal, are specially;
When the described degaussing time is greater than the front end blanking time, described first testing result is the first level, then described controlling value is described first level; When the described degaussing time is less than the described front end blanking time, described first testing result is second electrical level, then described controlling value is described second electrical level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510895297.7A CN105515413B (en) | 2015-12-08 | 2015-12-08 | A kind of output voltage sampling circuit and method based on AC-DC converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510895297.7A CN105515413B (en) | 2015-12-08 | 2015-12-08 | A kind of output voltage sampling circuit and method based on AC-DC converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105515413A true CN105515413A (en) | 2016-04-20 |
| CN105515413B CN105515413B (en) | 2018-07-24 |
Family
ID=55723145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510895297.7A Active CN105515413B (en) | 2015-12-08 | 2015-12-08 | A kind of output voltage sampling circuit and method based on AC-DC converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105515413B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265971A (en) * | 2019-07-25 | 2019-09-20 | 杭州必易微电子有限公司 | Control circuit and chip |
| CN113899934A (en) * | 2021-09-08 | 2022-01-07 | 东莞市长工微电子有限公司 | Voltage detection circuit and direct current transformer |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0419724A1 (en) * | 1989-09-29 | 1991-04-03 | Siemens Aktiengesellschaft | Circuit arrangement for a flyback switching power supply |
| CN101924471A (en) * | 2010-08-31 | 2010-12-22 | 深圳市明微电子股份有限公司 | Method for constantly outputting current and device thereof |
| CN102983760A (en) * | 2012-07-18 | 2013-03-20 | 无锡莱士电子科技有限公司 | Flyback switching power system and constant current controller thereof |
| CN103023283A (en) * | 2011-09-22 | 2013-04-03 | Nxp股份有限公司 | Controller for a switched mode power supply |
| CN103248207A (en) * | 2013-05-21 | 2013-08-14 | 苏州智浦芯联电子科技有限公司 | Constant-current and constant-voltage fly-back converter based on primary side feedback |
| CN104578792A (en) * | 2013-10-17 | 2015-04-29 | 比亚迪股份有限公司 | Line loss compensation device, switching power supply system and line loss compensation method |
-
2015
- 2015-12-08 CN CN201510895297.7A patent/CN105515413B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0419724A1 (en) * | 1989-09-29 | 1991-04-03 | Siemens Aktiengesellschaft | Circuit arrangement for a flyback switching power supply |
| CN101924471A (en) * | 2010-08-31 | 2010-12-22 | 深圳市明微电子股份有限公司 | Method for constantly outputting current and device thereof |
| CN103023283A (en) * | 2011-09-22 | 2013-04-03 | Nxp股份有限公司 | Controller for a switched mode power supply |
| CN102983760A (en) * | 2012-07-18 | 2013-03-20 | 无锡莱士电子科技有限公司 | Flyback switching power system and constant current controller thereof |
| CN103248207A (en) * | 2013-05-21 | 2013-08-14 | 苏州智浦芯联电子科技有限公司 | Constant-current and constant-voltage fly-back converter based on primary side feedback |
| CN104578792A (en) * | 2013-10-17 | 2015-04-29 | 比亚迪股份有限公司 | Line loss compensation device, switching power supply system and line loss compensation method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265971A (en) * | 2019-07-25 | 2019-09-20 | 杭州必易微电子有限公司 | Control circuit and chip |
| CN113899934A (en) * | 2021-09-08 | 2022-01-07 | 东莞市长工微电子有限公司 | Voltage detection circuit and direct current transformer |
| CN113899934B (en) * | 2021-09-08 | 2023-12-29 | 东莞市长工微电子有限公司 | Voltage detection circuit and direct-current transformer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105515413B (en) | 2018-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103580000B (en) | Switching Power Supply output over-voltage protection method and circuit and the Switching Power Supply with this circuit | |
| CN103023326B (en) | Constant time control method, control circuit and switching regulator using same | |
| CN102832806B (en) | Switch voltage stabilizing circuit and voltage feedback method thereof | |
| CN103378617B (en) | Lithium battery charging circuit | |
| CN102664525B (en) | Switching power supply circuit | |
| CN101635511B (en) | Switch voltage stabilizing circuit with frequency spectrum shaping function and method | |
| CN103675426B (en) | Inductive current zero-crossing detection method, circuit and switch power supply with circuit | |
| CN102055344B (en) | Switch power supply | |
| CN105375798A (en) | Self-adaptive sampling circuit, primary side feedback constant voltage system and switching power supply system | |
| CN204046448U (en) | Output voltage dynamic sampling circuit in AC-DC converter | |
| CN102904466B (en) | Switching power supply controller | |
| CN103280995A (en) | Quasi-resonance converter synchronous rectification circuit | |
| CN105375777A (en) | Constant voltage output circuit, flyback switching power supply and electronic device thereof | |
| CN103546021A (en) | Current feedback method, current feedback circuit, driving circuit and switching power source | |
| CN104849537A (en) | Switch converter, controller thereof and zero current detection method | |
| CN202840946U (en) | Switch voltage stabilizing circuit and voltage feedback circuit thereof | |
| CN103280963A (en) | Power factor correction (PFC) control circuit for reducing conducting power consumption of power tube | |
| CN102545663B (en) | Over power compensation circuit suitable for switching power supply in current mode | |
| CN105449807A (en) | Charging system on the basis of secondary control and secondary control device thereof | |
| CN104578722A (en) | Zero cross detection circuit of inductive current in power switch chip | |
| CN205160398U (en) | Self -adaptation sampling circuit , printed circuit board , former limit feedback constant voltage system and switching power supply system | |
| CN107742971A (en) | A kind of drive circuit and switching power circuit | |
| CN103472283A (en) | Voltage detection method and circuit and switching power supply with voltage detection circuit | |
| CN105515413A (en) | Output voltage sampling circuit and method based on AC-DC converter | |
| CN104333062A (en) | Charging circuit capable of detecting charging current |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Room 01, 10 / F, block a, Tiangong building, Keda, 30 Xueyuan Road, Haidian District, Beijing 100089 Patentee after: Meixinsheng Technology (Beijing) Co.,Ltd. Address before: 1006, office building, Crowne Plaza, No. 106, Zhichun Road, Haidian District, Beijing 100086 Patentee before: MAXIC TECHNOLOGY (BEIJING) Co.,Ltd. |
|
| CP03 | Change of name, title or address |