CN103873047B

CN103873047B - A kind of two-divider and high speed multiplexer

Info

Publication number: CN103873047B
Application number: CN201410101718.XA
Authority: CN
Inventors: 袁俊; 顾洵; 高鹏
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2014-03-18
Filing date: 2014-03-18
Publication date: 2017-01-04
Anticipated expiration: 2034-03-18
Also published as: CN103873047A

Abstract

Embodiments provide a kind of two-divider and high speed multiplexer, in order to solve owing to the initial phase of the two-divider in existing high speed multiplexer is indefinite, the problem causing sample error.The first setting circuit in this two-divider is when set signal is effective, and the input to the first phase inverter loads the first level signal so that described first outfan is second electrical level；And loading second electrical level signal to the input of the second phase inverter so that described second outfan is the first level；And set signal from effectively become invalid after, this two-divider first of its clock signal received effect along before rear output, second effect edge, its first outfan exports the first level, its second outfan output second electrical level, thus the clock signal after exporting the two divided-frequency determining a phase.

Description

A kind of two-divider and high speed multiplexer

Technical field

The present invention relates to technical field of integrated circuits, particularly relate to a kind of two-divider and high-speed, multi-path multiplexing Device.

Background technology

Current ultra high speed signal generally uses in processing and a road ultra high speed signal is decomposed into multi-path low speed letter Number carrying out Digital Signal Processing, multi-path low speed signal is recovered after terminating by process again through high speed multiplexer It it is a road ultra high speed signal.It is F that high speed multiplexer needs N group, often group M road, every road frequency Low speed signal synthesize N group, often organize 1 tunnel, every road frequency is the ultra high speed signal of M*F, namely Saying, it is the super of M*F that the low speed signal that the M road in often group, every road frequency are F synthesizes 1 tunnel frequency High speed signal.High speed multiplexer is because including multiplexer that multiple speed is relatively the lowest and can be real Show higher speed and gain the name.

But, owing to the d type flip flop (DFF, D Flip-Flop) in high speed multiplexer and multichannel are selected Selecting the device time delay of device, the initial phase of each two-divider in high speed multiplexer is different, may lead Cause high speed multiplexer, during multi-path low speed signal is reverted to a road high speed signal, mistake occurs.

Current a kind of high speed multiplexer uses the binary tree knot being made up of multiple 2:1 multiplexers Structure, wherein, two-way low speed signal can be synthesized a road high speed signal by each 2:1 multiplexer, The structure of each 2:1 multiplexer as it is shown in figure 1, include two d type flip flop D1 and D2, one Latch L, two-divider, MUX MUX, the input D of trigger D1 connects Receive A circuit-switched data signal D_Ain, the input D of trigger D2 receives B circuit-switched data signal D_Bin, trigger The clock signal terminal of D1 and the clock signal terminal of trigger D2 all receive the first clock of two-divider output The input D of signal CLK1, latch L receives the signal of trigger D2 output, latch L time Clock signal end receives the second clock signal CLK2 of two-divider output, the input of MUX MUX End S1 receives the signal of trigger D1 output, and the input S2 of MUX MUX receives latch The signal of L output, the control end C of MUX MUX receives the first clock letter of two-divider output Number CLK1, the two-way that MUX MUX will receive under the control of the first clock signal clk 1 Signal is combined into a road.Wherein, the frequency of the first clock signal clk 1 and the frequency of second clock signal CLK2 Rate is equal, and the first clock signal clk 1 is complementary with second clock signal CLK2, the i.e. first clock signal When CLK1 is high level, second clock signal CLK2 is low level, and the first clock signal clk 1 is low During level, second clock signal CLK2 is high level.First clock signal clk 1 of two-divider output The frequency of frequency and second clock signal CLK2 be equal to the clock signal clk that two-divider receives_in The half of frequency.

When keeping due to trigger data setup time to be met (setup time) and data Between the requirement of (hold time), i.e. input signal in the effect of clock signal along being front and back not allow to become Change.For using the trigger that rising edge triggers, the rising edge of clock signal is effect edge, clock Signal trailing edge is non-active edge；For using the trigger that trailing edge triggers, the decline of clock signal Along for acting on edge, the rising edge of clock signal is non-active edge.Setup time is exactly the effect of clock signal Before arriving, the input signal that trigger receives must keep stablizing constant minimum interval；And After hold time is the effect edge arrival of clock signal, the input signal that trigger receives also should keep steady Fixed constant minimum interval.

Although MUX is not set up the concept of time and retention time, but, connect in MUX Before and after the hopping edge (can be rising edge, it is also possible to trailing edge) of the clock signal received In a period of time, the input signal that MUX receives is if it occur that change, and MUX connects output Signal it may happen that mistake, therefore, near the hopping edge of the clock signal received in MUX, The signal that MUX receives also can not change.Therefore, receive in MUX Before the hopping edge of clock signal, the input signal that MUX receives keeps between constant minimum time The time is set up every may be considered MUX；Saltus step in the clock signal that MUX receives Along afterwards, the input signal that MUX receives keeps constant minimum interval to may be considered many The retention time of road selector.

Above-mentioned high speed multiplexer, an a device (rear device after the time delay of previous device being converted to The input signal received is the output signal of previous device) time of setting up or the retention time, thus solve Determine the delay problem of device.

But the initial phase of the two-divider in above-mentioned high speed multiplexer is indefinite, when above-mentioned high speed During the initial phase difference of the two-divider in multiple 2:1 multiplexers in multiplexer, may Cause sample error.

Summary of the invention

Embodiments provide a kind of two-divider and high speed multiplexer, in order to solve due to existing High speed multiplexer in the initial phase of two-divider indefinite, the problem that causes sample error.

First aspect, the embodiment of the present invention provide a kind of two-divider, including the first gate-controlled switch, second Gate-controlled switch, the 3rd gate-controlled switch, the 4th gate-controlled switch, the first phase inverter, the second phase inverter, the 3rd anti- Phase device, the 4th phase inverter, the first latch, the second latch and the first setting circuit；

One end of described first gate-controlled switch connects the input and described first of described first phase inverter respectively One end of latch, the other end of described first gate-controlled switch connects the outfan of described 4th phase inverter, institute The control end stating the first gate-controlled switch receives the first control signal；

One end of described second gate-controlled switch connects the input and described first of described second phase inverter respectively The other end of latch, the other end of described second gate-controlled switch connects the outfan of described 3rd phase inverter, The control end of described second gate-controlled switch receives described first control signal；

One end of described 3rd gate-controlled switch connects the outfan of described first phase inverter and described two points respectively Frequently the first outfan of device, the other end of described 3rd gate-controlled switch connects the one of described second latch respectively End and the input of described 3rd phase inverter, the control end of described 3rd gate-controlled switch receives the second control letter Number；

One end of described 4th gate-controlled switch connects the outfan of described second phase inverter and described two points respectively Frequently the second outfan of device, the other end of described 4th gate-controlled switch connects the another of described second latch respectively One end and the input of described 4th phase inverter, the control end of described 4th gate-controlled switch receives described second control Signal processed；

Described first setting circuit, for when set signal is effective, loads to the input of the first phase inverter First level signal so that described first outfan is second electrical level；And add to the input of the second phase inverter Carry second electrical level signal so that described second outfan is the first level；And when set invalidating signal, The input stopping the input to described first phase inverter and described second phase inverter loads signal；

Described first control signal is complementary, at set signal from effectively becoming invalid with described second control signal After, described first control signal is clock signal, and described second control signal is that clock hinders signal；

Described first gate-controlled switch is used to described second gate-controlled switch, is in described first control signal Close during one level signal, and disconnect when described first control signal is second electrical level signal；Described 3rd Gate-controlled switch is used to described 4th gate-controlled switch, when described second control signal is the first level signal Guan Bi, and disconnect when described second control signal is second electrical level signal；

Described first latch, for latching the signal of the input of described first phase inverter, and latches described The signal of the input of the second phase inverter；

Described second latch, for described set signal from effectively become invalid after, latch the 3rd anti-phase The signal of the input of device, and latch the signal of the input of described 4th phase inverter.

In conjunction with first aspect, in the implementation that the first is possible, described two-divider also includes that second puts Position circuit；

Described second setting circuit, for when set signal is effective, to the input of described 3rd phase inverter Load the first level signal, and load second electrical level signal to the input of described 4th phase inverter；And During set invalidating signal, stop the input to described 3rd phase inverter and the input of described 4th phase inverter Load signal；

Wherein, to the part of the input loading signal of described 3rd phase inverter in described second setting circuit Driving force, more than the driving force of described first phase inverter, to the described 4th in described second setting circuit The input of phase inverter loads the driving force of the part of signal, more than the driving energy of described second phase inverter Power.

In conjunction with first aspect, in the implementation that the second is possible, when described set signal is effective, institute Stating the first control signal and be set to second electrical level signal, described second control signal is set to the first level letter Number.

Second aspect, a kind of high speed multiplexer that the embodiment of the present invention provides, synthesize including at least one Circuit, one of them combiner circuit includes what k 2:1 multiplexer and the embodiment of the present invention provided Two-divider, one combiner circuit is for by one group 2ⁿRoad low speed signal synthesizes one group of one tunnel letter at a high speed Number circuit, k and n is positive integer,The transmission speed of a described road high speed signal is institute State 2ⁿRoad low speed signal sum；

In a combiner circuit, receive the clock signal of same frequency with one-level 2:1 multiplexer, First order 2:1 multiplexer receives described low speed signal, the output of afterbody 2:1 multiplexer Signal is described high speed signal, the every one-level 2:1 multiplexing in addition to first order 2:1 multiplexer The signal that device receives is the signal of previous stage 2:1 multiplexer output；Except afterbody 2:1 multichannel The clock signal that 2:1 multiplexers at different levels beyond multiplexer receive, is that rear stage 2:1 multichannel is multiple The clock signal clock signal of output after a two-divider frequency dividing received with device；

Each 2:1 multiplexer, is used for when the frequency receiving a two-divider output is f Under the control of clock signal, by the signal syntheses that two-way frequency is f received be a road frequency be the letter of 2*f Number.

In conjunction with second aspect, in the implementation that the first is possible, a 2:1 multiplexer includes First trigger, the second trigger, the 3rd trigger and 2:1 selector；

The input of described first trigger receives the first data signal that frequency is f, described first trigger Clock signal terminal to receive frequency be the clock signal of f, the outfan of described first trigger connects described 2: The first input end of 1 selector；

The input of described second trigger receives the second data signal that frequency is f, described second trigger Clock signal terminal to receive frequency be the clock signal of f, the outfan of described second trigger connects described the The input of three triggers；It is the clock signal of f that the clock signal terminal of described 3rd trigger receives with frequency Complementary clock signal, the outfan of described 3rd trigger connects the second input of described 2:1 selector End；The clock letter controlling the clock signal complement that end receives with described frequency is f of described 2:1 selector Number；

Described first trigger, being used for the first data signal and the described frequency by frequency is f is the clock of f Signal synchronizes；

Described second trigger, being used for the second data signal and the described frequency by frequency is f is the clock of f Signal synchronizes；

Described 3rd trigger, for by with the clock signal synchronization that described frequency is f after second data letter Number position move π the most afterwards；

Described 2:1 selector, being used in the clock signal with the clock signal complement that frequency is f is first During level signal, the outfan of described first input end with described 2:1 selector is connected；And with frequently Rate is the clock signal of the clock signal complement of f when being second electrical level signal, by described second input and institute The outfan stating 2:1 selector is connected.

In conjunction with second aspect or the first possible implementation of second aspect, in the realization that the second is possible In mode, described first trigger, the second trigger, the 3rd trigger are d type flip flop.

In conjunction with the first possible implementation of second aspect, in the implementation that the third is possible, work as institute State half and the difference of overall delay in the cycle of the clock signal that 2:1 multiplexer receives, be less than and receive When setting up the time of trigger in the 2:1 multiplexer of the signal of this 2:1 multiplexer output, The 2:1 multiplexer of the signal receiving the output of this 2:1 multiplexer also includes chronotron；

Described chronotron, for receiving the two-divider providing clock signal for this 2:1 multiplexer The clock signal delay preset duration arrived, and will postpone the clock signal after preset duration be sent to receive this 2: The 2:1 multiplexer of the signal of 1 multiplexer output.

Possible in conjunction with second aspect, the first possible implementation of second aspect and second aspect the second Any one in implementation, in the 4th kind of possible implementation, when comprising in described two-divider During two setting circuits, the set signal that described two-divider receives, is that described high speed multiplexer receives To the clock signal synchronization that receives of the set signal combiner circuit through described two-divider place After obtain.

Possible in conjunction with second aspect, the first possible implementation of second aspect to second aspect the 4th kind Any one in implementation, in the 5th kind of possible implementation, described high speed multiplexer includes At least one buffer, at least one buffer described uses clock trees distribution, is sent to described for reception The clock signal of high speed multiplexer, and provide for each combiner circuit in described high speed multiplexer Clock signal；

Wherein, the buffer of clock signal is exported for each combiner circuit in described high speed multiplexer Outfan is joined directly together；The clock signal provided for described each combiner circuit is imported in this combiner circuit First two-divider, described first two-divider is output as afterbody 2:1 in this combiner circuit Multiplexer provides clock signal.

In conjunction with the 5th kind of possible implementation of second aspect, in the 6th kind of possible implementation, institute State the clock signal that each combiner circuit in high speed multiplexer receives, be all described in be sent to described The buffer of the clock signal of high speed multiplexer same number at least one buffer described Obtain after buffering.

In conjunction with the 6th kind of possible implementation of second aspect, in the 7th kind of possible implementation, to The transmission path of the clock signal of the buffer output of multiple combiner circuits output clock signal uses clock trees Distribution.

The beneficial effect of the embodiment of the present invention includes:

The two-divider of embodiment of the present invention offer and high speed multiplexer, due to effective at set signal Time, the first outfan of this two-divider is second electrical level, and the second outfan of this two-divider is the first electricity Flat, and set signal from effectively become invalid after, first effect along afterwards, this effect is along afterwards Before nearest non-active edge, the first outfan of this two divided-frequency is the first level, the second of this two-divider Outfan is second electrical level；Wherein, first effect along be set signal from effectively become invalid after these two points First effect edge of the clock signal that device receives frequently.It is to say, two points that the embodiment of the present invention provides Frequently device set signal from effectively become invalid after, receive at this two-divider the first of clock signal Individual effect edge, the first outfan of this two-divider exports the first level, the second outfan of this two-divider Output second electrical level, therefore, the initial phase of the two-divider that the embodiment of the present invention provides is certain, and this is avoided Use the high speed multiplexer sample error of this two-divider.

Accompanying drawing explanation

Fig. 1 is the structural representation of 2:1 multiplexer of the prior art；

One of structural representation of two-divider that Fig. 2 provides for the embodiment of the present invention；

Fig. 3 is the sequential chart of the two-divider shown in Fig. 2；

The two of the structural representation of the two-divider that Fig. 4 provides for the embodiment of the present invention；

Fig. 5 is the sequential chart of the two-divider shown in Fig. 4；

The structural representation of a combiner circuit in the high speed multiplexer that Fig. 6 provides for the embodiment of the present invention Figure；

A 2:1 multiplexer in the high speed multiplexer that Fig. 7 provides for the embodiment of the present invention Structural representation；

Fig. 8 is the working timing figure of the 2:1 multiplexer shown in Fig. 7；

Fig. 9 is one of signal circuit structure diagram when transmitting between connected two-stage 2:1 multiplexer；

The working timing figure of the circuit shown in Figure 10 Fig. 9；

Two of circuit structure diagram when Figure 11 signal transmits between connected two-stage 2:1 multiplexer；

Figure 12 is the working timing figure of the circuit shown in Figure 11；

In the high speed multiplexer that Figure 13 provides for the embodiment of the present invention two points in a combiner circuit Frequently when device uses the structure shown in Fig. 2, the attachment structure schematic diagram of each two-divider；

In the high speed multiplexer that Figure 14 provides for the embodiment of the present invention two points in a combiner circuit Frequently when device uses the structure shown in Fig. 4, the attachment structure schematic diagram of each two-divider；

The structural representation of the clock trees in the high speed multiplexer that Figure 15 provides for the embodiment of the present invention it One；

The structural representation of the clock trees in the high speed multiplexer that Figure 16 provides for the embodiment of the present invention it Two.

Detailed description of the invention

The two-divider of embodiment of the present invention offer and high speed multiplexer, control two points by set signal Frequently device is when set signal is effective, and the first outfan of two-divider is second electrical level, the of this two-divider Two outfans are the first level；And control two-divider set signal from effectively become invalid after, this two First effect edge of the clock signal that frequency divider receives, the first outfan output first of this two-divider Level, the second outfan output second electrical level of this two-divider, so that the initial phase of two-divider Necessarily, and then the high speed multiplexer using this two-divider is correctly sampled.

Multiple below in conjunction with Figure of description, a kind of two-divider that the embodiment of the present invention is provided and high-speed, multi-path Illustrate by the detailed description of the invention of device.

The embodiment of the present invention provide a kind of two-divider, as in figure 2 it is shown, include the first gate-controlled switch SW1, Second gate-controlled switch SW2, the 3rd gate-controlled switch SW3, the 4th gate-controlled switch SW4, the first phase inverter INV1, Second phase inverter INV2, the 3rd phase inverter INV3, the 4th phase inverter INV4, the first latch 22, Two latch 23 and the first setting circuits 21；

One end of first gate-controlled switch SW1 connects the input and first of the first phase inverter INV1 respectively and latches One end of device 22, the other end of the first gate-controlled switch SW1 connects the outfan of the 4th phase inverter INV4, The control end of the first gate-controlled switch SW1 receives the first control signal Ctr1；

One end of second gate-controlled switch SW2 connects the input and first of the second phase inverter INV2 respectively and latches The other end of device 22, the other end of the second gate-controlled switch SW2 connects the outfan of the 3rd phase inverter INV3, The control end of the second gate-controlled switch SW2 receives the first control signal Ctr1；

One end of 3rd gate-controlled switch SW3 connects outfan and this two divided-frequency of the first phase inverter INV1 respectively The first outfan OUT1, the other end of the 3rd gate-controlled switch SW3 connects the second latch 23 respectively One end and the input of the 3rd phase inverter INV3, the control end of the 3rd gate-controlled switch SW3 receives the second control Signal Ctr2；

One end of 4th gate-controlled switch SW4 connects outfan and this two divided-frequency of the second phase inverter INV2 respectively The second outfan OUT2, the other end of the 4th gate-controlled switch SW4 connects the second latch 23 respectively The other end and the input of the 4th phase inverter INV4, the control end of the 4th gate-controlled switch SW4 receives the second control Signal Ctr2 processed；

First setting circuit 21, for when set signal SET is effective, defeated to the first phase inverter INV1 Enter end and load the first level signal so that the first outfan OUT1 of this two-divider is second electrical level；And Second electrical level signal is loaded so that the second output of this two-divider to the input of the second phase inverter INV2 End OUT2 is the first level；And when set signal SET is invalid, stop to the first phase inverter INV1 Input and the second phase inverter INV2 input load signal；

First control signal Ctr1 and the second control signal Ctr2 are complementary, and the i.e. first control signal Ctr1 is high During level, the second control signal Ctr2 is low level, when the first control signal Ctr1 is low level, and second Control signal Ctr2 is high level；Set signal SET from effectively become invalid after, the first control signal Ctr1 is clock signal, and the second control signal Ctr2 is that clock hinders signal；

First gate-controlled switch SW1 and the second gate-controlled switch SW2 is used to, in the first control signal Ctr1 Close when being the first level signal, and disconnect when the first control signal Ctr1 is second electrical level signal；

3rd gate-controlled switch SW3 and the 4th gate-controlled switch SW4 is used to, in the second control signal Ctr2 Close when being the first level signal, and disconnect when the second control signal Ctr2 is second electrical level signal；

First latch 22, for latching the signal of the input of the first phase inverter INV1, and latches second The signal of the input of phase inverter INV2；

Second latch 23, for described set signal SET from effectively become invalid after, latch the 3rd The signal of the input of phase inverter INV3, and latch the signal of the input of the 4th phase inverter INV4.

When the first level signal is high level signal, second electrical level signal is low level signal；When the first electricity When ordinary mail number is low level signal, second electrical level signal is high level signal.

Owing to the first setting circuit is when set signal is effective, first can be loaded to the input of the first phase inverter Level signal, so that the first phase inverter output second electrical level signal, and then make the first of this two-divider Outfan is second electrical level；And the first setting circuit is when set signal is effective, can be to the second phase inverter Input loads second electrical level signal, so that the second phase inverter exports the first level signal, and then makes Second outfan of this two-divider is the first level.

It is to say, when set signal is effective, the first outfan of two-divider is always second electrical level, And the second outfan of two-divider is always the first level.

The first setting circuit 21 in two-divider shown in Fig. 2 at set signal SET from effectively becoming nothing During effect, signal will not be loaded to the input of the first phase inverter INV1 again；Therefore, in the one of clock signal Individual effect along afterwards, this effect along before the most nearest non-active edge, the i.e. first gate-controlled switch SW1 and Second gate-controlled switch SW2 all closes, and the 3rd gate-controlled switch SW3 and the 4th gate-controlled switch SW4 all disconnects, The signal of the outfan of input reception the 4th phase inverter INV4 of the first phase inverter INV1, and now, The signal of the outfan of the 4th phase inverter INV4 is the non-work that this effect is along before, this effect edge is the most nearest With along afterwards (the most the last first gate-controlled switch SW1 and the second gate-controlled switch SW2 all disconnects, the 3rd When gate-controlled switch SW3 and the 4th gate-controlled switch SW4 all closes), the input termination of the 4th phase inverter INV4 The signal received signal after anti-phase, the signal of the outfan of the i.e. second phase inverter INV2 is through anti- Signal after Xiang.

When the first level is high level, and second electrical level is low level, the effect edge of clock signal is clock signal Rising edge, the trailing edge that non-active edge is clock signal of clock signal；When the first level is low level, Second electrical level is high level, and the effect of clock signal is along the trailing edge for clock signal, the non-work of clock signal With along the rising edge being clock signal.

When this effect along for set signal from effectively become invalid after the clock letter that receives of this two-divider Number first effect along time, before this effect edge, after nearest before this effect edge non-active edge, The signal of the outfan of the second phase inverter is the signal that the second phase inverter exports when set signal is effective, i.e. First level signal, therefore, first effect along afterwards, this effect is along nearest non-active edge afterwards Before, the signal that the input of the first phase inverter receives is second electrical level signal, now, and the first phase inverter The first outfan exporting the first level signal, i.e. this two-divider is the first level；And first effect After nearest non-active edge afterwards, second effect of clock signal along before, in the first latch The signal of input of the first phase inverter latched be first effect along afterwards, this effect along after nearest Before non-active edge, the signal of the input of the first phase inverter, i.e. second electrical level signal, therefore, first is anti- Phase device still exports the first level after by this second electrical level signal inversion, say, that set signal by Effectively become invalid after first effect of the clock signal that receives of this two-divider along afterwards, set letter Number from effectively become invalid after second effect of the clock signal that receives of this two-divider along before, should First outfan of two-divider is the first level.

When this effect along for set signal from effectively become invalid after the clock letter that receives of this two-divider Number n-th (n be more than 1) individual effect along time, before this effect edge, nearest before this effect edge non-work With along afterwards, the signal of the outfan of the second phase inverter is, the second phase inverter at set signal by effectively becoming For after invalid, (n-1)th effect of clock signal that receive of this two-divider be along rear, (n-1)th effect The signal of output before the most nearest non-active edge, therefore, set signal from effectively become invalid after, N-th effect of the clock signal that this two-divider receives along afterwards, nearest non-along afterwards of this effect Effect along before, the signal of the input of the first phase inverter, be set signal from effectively become invalid after, N-th effect of the clock signal that this two-divider receives along before, nearest non-along before of this effect Effect along afterwards, the signal after the signal inversion of the outfan of the second phase inverter, namely set signal by Effectively become invalid after, the n-th effect of the clock signal that receives of this two-divider along before, (n-1)th Individual effect is along the signal after the signal inversion of the outfan of the second phase inverter afterwards, therefore, set signal by Effectively become invalid after, the n-th effect of the clock signal that receives of this two-divider along afterwards, this effect Before nearest non-active edge afterwards, the signal of the first phase inverter output, is by effectively becoming at set signal For after invalid, the n-th effect of clock signal that receives of this two-divider along before, (n-1)th effect Signal along the outfan of the second phase inverter afterwards；And in the n-th effect along nearest non-active edge afterwards Afterwards, (n+1)th effect along before, the signal of the input of the first phase inverter latched in the first latch Be the n-th effect along afterwards, this effect along after nearest non-active edge before, the input of the first phase inverter End signal, therefore, set signal from effectively become invalid after, this two-divider receive clock letter Number the n-th effect along after the most nearest non-active edge, (n+1)th effect be along the first phase inverter before The signal of output, be still that set signal from effectively become invalid after, the clock that receives of this two-divider The n-th of signal acts on along before, the signal of (n-1)th effect edge outfan of the second phase inverter afterwards.

The first setting circuit 21 in two-divider shown in Fig. 2 at set signal SET from effectively becoming nothing After effect, signal will not be loaded to the input of the second phase inverter INV2 again；Therefore, in the one of clock signal Individual effect along afterwards, this effect along before the most nearest non-active edge, the i.e. first gate-controlled switch SW1 and Second gate-controlled switch SW2 all closes, and the 3rd gate-controlled switch SW3 and the 4th gate-controlled switch SW4 all disconnects, The signal of the outfan of input reception the 3rd phase inverter INV3 of the second phase inverter INV2, and now, The signal of the outfan of the 3rd phase inverter INV3 is the non-work that this effect is along before, this effect edge is the most nearest With along afterwards (the most the last first gate-controlled switch SW1 and the second gate-controlled switch SW2 all disconnects, the 3rd When gate-controlled switch SW3 and the 4th gate-controlled switch SW4 all closes), the input termination of the 3rd phase inverter INV3 The signal received signal after anti-phase, the signal of the outfan of the i.e. first phase inverter INV1 is through anti- Signal after Xiang.

When this effect along for set signal from effectively become invalid after the clock letter that receives of this two-divider Number first effect along time, before this effect edge, after nearest before this effect edge non-active edge, The signal of the outfan of the first phase inverter is the signal that the first phase inverter exports when set signal is effective, i.e. Second electrical level signal, therefore, first effect along afterwards, this effect is along nearest non-active edge afterwards Before, the signal that the input of the second phase inverter receives is the first level signal, now, and the second phase inverter Second outfan of output second electrical level signal, i.e. this two-divider is second electrical level；And first effect After nearest non-active edge afterwards, second effect of clock signal along before, in the first latch The signal of input of the second phase inverter latched be first effect along afterwards, this effect along after nearest Before non-active edge, the signal of the input of the second phase inverter, the i.e. first level signal, therefore, second is anti- Phase device is still exporting second electrical level after anti-phase for this first level signal, say, that set signal by Effectively become invalid after first effect of the clock signal that receives of this two-divider along afterwards, set letter Number from effectively become invalid after second effect of the clock signal that receives of this two-divider along before, should Second outfan of two-divider is second electrical level.

When this effect along for set signal from effectively become invalid after the clock letter that receives of this two-divider Number n-th (n be more than 1) individual effect along time, before this effect edge, nearest before this effect edge non-work With along afterwards, the signal of the outfan of the first phase inverter is, the first phase inverter at set signal by effectively becoming For after invalid, (n-1)th effect of clock signal that receive of this two-divider be along rear, (n-1)th effect The signal of output before the most nearest non-active edge, therefore, set signal from effectively become invalid after, N-th effect of the clock signal that this two-divider receives along afterwards, nearest non-along afterwards of this effect Effect along before, the signal of the input of the second phase inverter, be set signal from effectively become invalid after, N-th effect of the clock signal that this two-divider receives along before, nearest non-along before of this effect Effect along afterwards, the signal after the signal inversion of the outfan of the first phase inverter, namely set signal by Effectively become invalid after, the n-th effect of the clock signal that receives of this two-divider along before, (n-1)th Individual effect is along the signal after the signal inversion of the outfan of the first phase inverter afterwards, therefore, set signal by Effectively become invalid after, the n-th effect of the clock signal that receives of this two-divider along afterwards, this effect Before nearest non-active edge afterwards, the signal of the second phase inverter output, is by effectively becoming at set signal For after invalid, the n-th effect of clock signal that receives of this two-divider along before, (n-1)th effect Signal along the outfan of the first phase inverter afterwards；And in the n-th effect along nearest non-active edge afterwards Afterwards, (n+1)th effect along before, the signal of the input of the second phase inverter latched in the first latch Be the n-th effect along afterwards, this effect along after nearest non-active edge before, the input of the second phase inverter End signal, therefore, set signal from effectively become invalid after, this two-divider receive clock letter Number the n-th effect along after the most nearest non-active edge, (n+1)th effect be along the second phase inverter before The signal of output, be still that set signal from effectively become invalid after, the clock that receives of this two-divider The n-th of signal acts on along before, the signal of (n-1)th effect edge outfan of the first phase inverter afterwards.

Understanding according to the above description, the two-divider that the embodiment of the present invention provides is when set signal is effective, logical Cross the first outfan output second electrical level signal of this two-divider, and by the second output of this two-divider End output the first level signal.The embodiment of the present invention provide two-divider at set signal from effectively becoming nothing After effect, first effect of the clock signal that receives of this two-divider along afterwards, second effect along before, The first level signal is exported by the first outfan of this two-divider, and defeated by the second of this two-divider Go out end output second electrical level signal, thus at set signal from when effectively becoming invalid, carry-out bit determines mutually Signal.The embodiment of the present invention provide two-divider set signal from effectively become invalid after, this two divided-frequency N-th (n be more than 1) the individual effect of the clock signal that device receives along afterwards, (n+1)th effect along before, By the signal of the first outfan output of this two-divider, with this two-divider at set signal by effectively becoming For after invalid, (n-1)th effect of clock signal that receive of this two-divider along afterwards, the n-th effect Along before, the signal by the second outfan output of this two-divider is identical；The embodiment of the present invention provides Two-divider set signal from effectively become invalid after, this two-divider receive the n-th of clock signal (n be more than 1) individual effect along afterwards, (n+1)th effect along before, defeated by the second of this two-divider Go out the signal of end output, with this two-divider set signal from effectively become invalid after, this two-divider connects (n-1)th effect of the clock signal received is along afterwards, and the n-th effect is along before, by this two-divider First outfan output signal identical；It is achieved thereby that set signal from effectively become invalid after, two The frequency of output signal of frequency divider is the half of the frequency of the clock signal that this two-divider receives, Jin Ershi Showed set signal from effectively become invalid after, the function of clock signal two divided-frequency that will receive.

Alternatively, the two-divider that the embodiment of the present invention provides, when set signal SET is effective, the first control Signal Ctr1 processed is set to second electrical level signal, and the second control signal Ctr2 is set to the first level signal.

Therefore, the first setting circuit 21 in the two-divider shown in Fig. 2 when set signal SET is effective, The first level signal can be loaded to the input of the first phase inverter INV1, and can be to the second phase inverter INV2 Input load second electrical level signal；Due to when set signal SET is effective, the first control signal Ctr1 For second electrical level signal, the second control signal Ctr2 is the first level signal, therefore, at set signal SET Time effectively, the first gate-controlled switch SW1 and the second gate-controlled switch SW2 all disconnects, the 3rd gate-controlled switch SW3 All closing with the 4th gate-controlled switch SW4, therefore, the first phase inverter INV1 exports second electrical level signal, should First outfan OUT1 of two-divider is second electrical level, and the second phase inverter INV2 exports the first level letter Number, the second outfan OUT2 of this two-divider is the first level；Further, have at set signal SET During effect, the input of the 3rd phase inverter INV3 is second electrical level, and the input of the 4th phase inverter INV4 is First level.

It is to say, when set signal is effective, the first outfan OUT1 of the two-divider shown in Fig. 2 Being always second electrical level, the second outfan OUT2 of this two-divider is always the first level.

When the first level is high level, and second electrical level is low level, the effect edge of clock signal is clock signal Rising edge, the trailing edge that non-active edge is clock signal of clock signal, set signal high level is effective, When set signal low level is invalid, the circuit timing diagram of the two-divider shown in Fig. 2 is as shown in Figure 3.

In figure 3, when set signal is effective, the first outfan of the two-divider shown in Fig. 2 is second Level, the second outfan of this two-divider is the first level；And set signal from effectively become invalid it After, set signal is acted on along before from effectively become invalid rear first control signal first, this two divided-frequency First outfan of device is second electrical level, and the second outfan of this two-divider is the first level；And in set Signal is acted on along afterwards from effectively become invalid first control signal afterwards first, the first control signal Second effect is along before, and the first outfan of this two-divider is the first level, the second of this two-divider Outfan is second electrical level.Set signal from effectively become invalid after the n-th (n of the first control signal More than 1) individual effect is along afterwards, and (n+1)th of the first control signal acts on along before, this two-divider The level of the first outfan, with set signal from effectively become invalid after the first control signal (n-1)th Individual effect is along afterwards, and the n-th of the first control signal acts on along before, the second outfan of this two-divider Level identical；Set signal from effectively become invalid after n-th (n be more than 1) of the first control signal Individual effect is along afterwards, and (n+1)th effect of the first control signal is along before, and the second of this two-divider exports The level of end, with set signal from effectively become invalid after (n-1)th of the first control signal act on edge Afterwards, the n-th of the first control signal acts on along before, the level phase of the first outfan of this two-divider With.

From figure 3, it can be seen that transparent transmission time be that two-divider receives clock signal half week each time Phase, phase reversal time is the half period that two-divider receives clock signal each time；Wherein, the transparent transmission time It is for by the 3rd gate-controlled switch Guan Bi in Fig. 2, the signal of the outfan of the first phase inverter is transmitted to the The input of three phase inverters, and be latched in the second latch；And for by the 4th gate-controlled switch in Fig. 2 Guan Bi, transmits the input to the 4th phase inverter by the signal of the outfan of the second phase inverter, and is latched in the In two latch；Phase reversal time is for by the first gate-controlled switch Guan Bi in Fig. 2, defeated by the 4th phase inverter Go out the signal transmission input to the first phase inverter of end, and be latched in the first latch, and for scheming The second gate-controlled switch Guan Bi in 2, transmits the signal of the outfan of the 3rd phase inverter to the second phase inverter Input, and be latched in the first latch.

Alternatively, the two-divider that the embodiment of the present invention provides as shown in Figure 4, also includes the second setting circuit 24；When set signal is effective, described first control signal is clock signal, and described second control signal is Clock hinders signal；

Wherein, clock hinders signal CLKB complementary with clock signal clk, i.e. clock hinders signal CLKB When being the first level, clock signal clk is second electrical level, and clock hinders signal CLKB to be second electrical level Time, clock signal clk is the first level；On one of clock signal clk effect edge, first controlled opens Close SW1 and the second gate-controlled switch SW2 and become Guan Bi, the 3rd gate-controlled switch SW3 and the 4th by disconnection Gate-controlled switch SW4 is gone off by Guan Bi；On a non-active edge of clock signal clk, first can Control switch SW1 and the second gate-controlled switch SW2 gone off by Guan Bi, the 3rd gate-controlled switch SW3 and 4th gate-controlled switch SW4 is become Guan Bi by disconnection；

Second setting circuit 24, for when set signal SET is effective, defeated to the 3rd phase inverter INV3 Enter end and load the first level signal, and load second electrical level signal to the input of the 4th phase inverter INV4； And when set signal SET is invalid, stop the input to the 3rd phase inverter INV3 and the 4th phase inverter The input of INV4 loads signal；

Wherein, to the part of the input loading signal of the 3rd phase inverter INV3 in the second setting circuit 24 Driving force, more than the driving force of the first phase inverter INV1, anti-phase to the 4th in the second setting circuit 24 The input of device INV4 loads the driving force of the part of signal, more than the driving of the second phase inverter INV2 Ability.

The first setting circuit 21 in two-divider shown in Fig. 4, can be to when set signal SET is effective The input of the first phase inverter INV1 loads the first level signal, and can be to the second phase inverter INV2 Input loads second electrical level signal；When clock signal clk is the first level, clock hinders signal CLKB is second electrical level, and now, the first gate-controlled switch SW1 and the second gate-controlled switch SW2 all closes, 3rd gate-controlled switch SW3 and the 4th gate-controlled switch SW4 all disconnects, and therefore, the first phase inverter INV1 is defeated Going out second electrical level signal, the first outfan OUT1 of this two-divider is second electrical level, the second phase inverter INV2 exports the first level signal, and the second outfan OUT2 of this two-divider is the first level；At that time When clock signal CLK is second electrical level, clock hinders signal CLKB to be the first level, and now, first can Control switch SW1 and the second gate-controlled switch SW2 all disconnects, and the 3rd gate-controlled switch SW3 and the 4th controlled opens Close SW4 all to close, owing to the second setting circuit 24 adding information carrying to the input of the 3rd phase inverter INV3 Number the driving force of part, more than the driving force of the first phase inverter INV1, therefore, even if second puts Position circuit 24 loads the first level signal to the input of the 3rd phase inverter INV3, the first of this two-divider Outfan OUT1 is still second electrical level；Due in the second setting circuit 24 to the 4th phase inverter INV4 Input load the driving force of part of signal, more than the driving force of the second phase inverter INV2, because of This, is even if the second setting circuit 24 loads second electrical level signal to the input of the 4th phase inverter INV4, should Second outfan OUT2 of two-divider is the first level.

It is to say, when set signal is effective, the first outfan OUT1 of the two-divider shown in Fig. 4 Being always second electrical level, the second outfan OUT2 of this two-divider is always the first level.

The first setting circuit 21 in two-divider shown in Fig. 4 at set signal SET from effectively becoming nothing After effect, signal will not be loaded to the input of the first phase inverter INV1 again, and will not be again to the second phase inverter The input of INV2 loads signal, and the second setting circuit 24 in this two-divider is at set signal SET Time invalid, signal will not be loaded to the input of the 3rd phase inverter INV3 again, and will not be anti-phase to the 4th again The input of device INV4 loads signal；Therefore, the two-divider shown in Fig. 4 at set signal SET by having Effect become invalid after operation principle, with the two-divider shown in Fig. 2 at set signal SET from effectively becoming Operation principle after invalid is identical, does not repeats them here.

When the first level is high level, and second electrical level is low level, the effect edge of clock signal is clock signal Rising edge, the trailing edge that non-active edge is clock signal of clock signal, set signal high level is effective, When set signal low level is invalid, the circuit timing diagram of the two-divider shown in Fig. 4 is as shown in Figure 5.

In Figure 5, when set signal is effective, the first outfan of the two-divider shown in Fig. 4 is second Level, the second outfan of this two-divider is the first level；And set signal from effectively become invalid it After, set signal from effectively become invalid after first effect edge of the clock signal that receives of this two-divider Before, the first outfan of this two-divider is second electrical level, and the second outfan of this two-divider is first Level；And set signal from effectively become invalid after this two-divider receive the first of clock signal Individual effect is along afterwards, and second of the clock signal that this two-divider receives acts on along before, this two divided-frequency First outfan of device is the first level, and the second outfan of this two-divider is second electrical level.Believe in set Number from effectively become invalid after n-th (n is more than 1) individual effect of the clock signal that receives of this two-divider Along afterwards, (n+1)th of the clock signal that this two-divider receives acts on along before, this two-divider The level of the first outfan, with set signal from effectively become invalid after this two-divider receive time (n-1)th effect of clock signal is along afterwards, and the n-th of the clock signal that this two-divider receives acts on edge Before, the level of the second outfan of this two-divider is identical；Set signal from effectively become invalid after N-th (n is more than 1) the individual effect of the clock signal that this two-divider receives is along afterwards, and this two-divider connects (n+1)th of the clock signal received acts on along before, the level of the second outfan of this two-divider, with Set signal from effectively become invalid after (n-1)th effect of clock signal that receive of this two-divider Along afterwards, the n-th effect of the clock signal that this two-divider receives along before, the of this two-divider The level of one outfan is identical.

Set signal can the saltus step when clock signal is high level (be to believe at clock with set signal in Fig. 5 Number for illustrating as a example by saltus step during high level), it is also possible to when clock signal is low level saltus step, but Cannot the saltus step when clock signal generation saltus step, to avoid the metastable state being likely to occur.When set signal exists Saltus step when clock signal is high level, then set signal from effectively become invalid after, each time during transparent transmission Between be the half period of clock signal；When the saltus step when clock signal is low level of set signal, then putting Position signal from effectively become invalid after, set signal from effectively become invalid after first of clock signal Effect is along before, and the transparent transmission time is less than the half period of clock signal, and remaining transparent transmission time is clock letter Number half period；When the transparent transmission time is too small, two-divider output signal mistake can be caused.Therefore, relatively Goodly, the set signal that two-divider receives will when its clock signal received is the first level, by It is invalid effectively to become.Wherein, the transparent transmission time is for by the 3rd gate-controlled switch Guan Bi in Fig. 4, anti-by first The signal of the outfan of phase device transmits the input to the 3rd phase inverter, and is latched in the second latch；And For by the 4th gate-controlled switch Guan Bi in Fig. 4, the signal of the outfan of the second phase inverter being transmitted to the 4th The input of phase inverter, and be latched in the second latch.

When set signal from effectively become invalid after, phase reversal time is half week of clock signal each time Phase, wherein, phase reversal time is for by the first gate-controlled switch Guan Bi in Fig. 4, by the output of the 4th phase inverter The signal of end transmits the input to the first phase inverter, and is latched in the first latch, and for by Fig. 2 In the second gate-controlled switch Guan Bi, the signal of the outfan of the 3rd phase inverter transmitted to the second phase inverter is defeated Enter end, and be latched in the first latch.

A kind of high speed multiplexer that the embodiment of the present invention provides, including at least one combiner circuit, wherein One combiner circuit (as shown in Figure 6, in Fig. 6 as a example by n=3) includes k 2:1 multiplexing (the 2:1 multichannel of 611,2 second level of 2:1 multiplexer of 4 first order in Fig. 6 is multiple for device With device 612 and the 2:1 multiplexer 613 of 1 third level) and the two of n embodiment of the present invention offer Frequency divider 62, one combiner circuit is for by one group 2ⁿRoad low speed signal synthesizes one group of one tunnel at a high speed The circuit of signal, k and n is positive integer,The transmission speed of a described road high speed signal is Described 2ⁿRoad low speed signal sum；

In a combiner circuit, receive the clock signal of same frequency with one-level 2:1 multiplexer 61, First order 2:1 multiplexer receives described low speed signal, the output of afterbody 2:1 multiplexer Signal is described high speed signal, the every one-level 2:1 multiplexing in addition to first order 2:1 multiplexer The signal that device receives is the signal of previous stage 2:1 multiplexer output；Except afterbody 2:1 multichannel The clock signal that 2:1 multiplexers at different levels beyond multiplexer receive, is this grade of 2:1 multiplexing The clock signal that the rear stage 2:1 multiplexer of device receives is defeated after two-divider 62 frequency dividing The signal gone out；

Each 2:1 multiplexer, at the clock that frequency is f receiving two-divider 62 output Under the control of signal, by the signal syntheses that two-way frequency is f received be a road frequency be the signal of 2*f.

Wherein, a 2:1 multiplexer is as it is shown in fig. 7, comprises the first trigger 71, second triggers Device the 72, the 3rd trigger 73 and 2:1 selector 74；

The input of the first trigger 71 receives the first data signal P1 that frequency is f, the first trigger 71 Clock signal terminal CLK to receive frequency be the clock signal clk 1 of f, the outfan of the first trigger 71 Connect the first input end of 2:1 selector 74；

The input of the second trigger 72 receives the second data signal P2 that frequency is f, the second trigger 72 Clock signal terminal CLK to receive frequency be the clock signal clk 1 of f, the outfan of the second trigger 72 Connect the input of the 3rd trigger 73；The clock signal terminal CLK of the 3rd trigger 73 receives and frequency For the clock signal clk 2 of clock signal clk 1 complementation of f, the outfan of the 3rd trigger 73 connects 2: Second input of 1 selector 74；It is f's that the control end C of 2:1 selector 74 receives described frequency The clock signal clk 2 of clock signal clk 1 complementation；

First trigger 71, for by the first data signal P1 that frequency is f and the clock letter that frequency is f Number CLK1 synchronizes, and exports the first data signal P11 after synchronization；

Second trigger 72, for by the second data signal P2 that frequency is f and the clock letter that frequency is f Number CLK1 synchronizes, and exports the second data signal P21 after synchronization；

3rd trigger 73, for by the second data letter after synchronize with the clock signal clk 1 that frequency is f The position of number P21 moves π the most afterwards, and exports the second data signal P22 after phase shift；

2:1 selector 74, at the clock signal clk 2 with clock signal clk 1 complementation that frequency is f When being the first level signal, defeated by the first input end of this 2:1 selector 74 and 2:1 selector 74 Go out termination logical；And the clock signal clk 2 with clock signal clk 1 complementation that frequency is f be second electricity During ordinary mail, the outfan of the second input of this 2:1 selector 74 with 2:1 selector 74 is connected.

When the time delay of the first trigger in a 2:1 multiplexer, the time delay of the second trigger and The time delay when time delay of three triggers is first, the holding of the 2:1 selector in this 2:1 multiplexer Time was less than less than the time of setting up of the 2:1 selector in the first time delay, and this 2:1 multiplexer should The half in the cycle of the clock signal that 2:1 multiplexer receives and the difference of described first time delay；

The half in the cycle of the clock signal that one 2:1 multiplexer receives and the difference of overall delay, greatly In when the setting up of trigger received in the 2:1 multiplexer of signal of this 2:1 multiplexer output Between, and described overall delay is more than the 2:1 multiplexer of the signal receiving the output of this 2:1 multiplexer In retention time of trigger, wherein, described overall delay is the 2:1 choosing in this 2:1 multiplexer Select the time delay of device, with the time delay sum of the two-divider providing clock signal for this 2:1 multiplexer.

Wherein, each trigger in a 2:1 multiplexer, such as the first trigger, the second triggering Device, the 3rd trigger can be d type flip flops, can also be to be made up of JK flip-flop, rest-set flip-flop etc. The trigger being capable of d type flip flop function.

Fig. 7 also includes a two-divider 62, for the clock signal clk that will receive_inFrequency reduces Half, and two complementary clock signals that output frequency reduction half is later.

If the first level is high level, second electrical level is low level, and the effect of clock signal is believed along for clock Number rising edge, the trailing edge that non-active edge is clock signal of clock signal, 2:1 selector self When control end is high level, the first input end of self is connected with the outfan of self, and in the control of self When end processed is low level, the second input of self is connected with the outfan of self, two shown in Fig. 7 point Frequently the circuit timing diagram of device is as shown in Figure 8.

In fig. 8, the time delay of the time delay of the first trigger, the time delay of the second trigger and the 3rd trigger is equal For Dly_Dff, say, that when the effect of clock signal clk 1 is along Dly_Dff afterwards, first The first data signal P11 after the synchronization of trigger output changes, complementary with clock signal clk 1 The effect of clock signal clk 2 along Dly_Dff afterwards time, the after the phase shift of the 3rd trigger output Two data signals P22 change, owing to the signal controlling end at 2:1 selector changes (i.e. The hopping edge of clock signal, including rising edge and the trailing edge of clock signal of clock signal) moment before A period of time, within i.e. setting up the time, and the signal controlling end of 2:1 selector changes Within a period of time after moment, i.e. retention time, the input signal that 2:1 selector receives changes Become, may result in 2:1 selector output error, therefore, the holding of 2:1 selector 74 in Fig. 7 Time is less than Dly_Dff, and the time of setting up of 2:1 selector 74 is less than T_CLK1/2-Dly_Dff, its In, the cycle of the clock signal clk 1 that T_CLK1/2 is the first trigger and the second trigger receives Half, the cycle of the clock signal clk 1 received due to the first trigger and the second trigger touches with the 3rd Send out cycle of clock signal clk 2 that device receives equal, therefore, T_CLK1/2-Dly_Dff with T_CLK2/2-Dly_Dff, T_CLK2/2 be the 3rd trigger 73 and 2:1 selector 74 receive time The half in clock signal CLK2 cycle.The most reasonably select the trigger in 2:1 multiplexer With 2:1 selector, can be by trigger (including the first trigger, the second trigger and the 3rd trigger) Time delay effectively utilize, solve the problem that sequential is nervous during high frequency signals.

When signal transmits between two-stage 2:1 multiplexer, circuit structure is as it is shown in figure 9,2:1 Selector is positioned in n-th grade of 2:1 multiplexer, and it is multiple that the first trigger is positioned at (n+1)th grade of 2:1 multichannel With in device, naturally it is also possible to be second trigger receive 2:1 selector output signal, in Fig. 9 only with First trigger illustrates as a example by receiving the signal that 2:1 selector exports.If the first level is high electricity Flat, second electrical level is low level, the rising edge that the effect edge of clock signal is clock signal, clock signal Non-active edge is the trailing edge of clock signal, and 2:1 selector, will be from when the control end of self is high level The first input end of body and the outfan of self are connected, and when the control end of self is low level, by self The second input connect with self outfan, the circuit timing diagram of the two-divider shown in Fig. 9 such as Figure 10 Shown in.

In Fig. 10, Dly_div is the two-divider providing control signal for the 2:1 selector in Fig. 9 Time delay, Dly_Mux is the time delay of the 2:1 selector in Fig. 9.In the clock signal that frequency is f When acting on edge Dly_div+Dly_Mux afterwards, the signal of 2:1 selector output changes, therefore, The retention time of the first trigger receiving the signal of 2:1 selector output in Fig. 9 is less than Dly_div+Dly_Mux, Fig. 9 receive when the setting up of the first trigger of the signal of 2:1 selector output Between less than 1/f-(Dly_div+Dly_Mux).That is reasonably select to receive a 2:1 multiplexing Trigger in the 2:1 multiplexer of the signal of device output, can be by this 2:1 multiplexer The time delay of 2:1 selector effectively utilizes, the problem that during solution high frequency signals, sequential is nervous.

Data_Mux in Figure 10 refers to the signal of 2:1 selector 74 output in Fig. 9, Tu10Zhong Data_DFF refer in Fig. 9 first trigger 71 output signal.

Along with the frequency of clock signal constantly raises, the cycle of clock signal constantly reduces, 1/f-(Dly_div+Dly_Mux) tapers into, to such an extent as to the time of setting up of the first trigger is more than or equal to 1/f-(Dly_div+Dly_Mux), when signal transmits between two-stage 2:1 multiplexer, circuit structure As shown in figure 11.In fig. 11, may also include a chronotron 111, being used for will be that n-th grade of 2:1 is many Path multiplexer (only giving the 2:1 selector 74 in n-th grade of 2:1 multiplexer in Figure 11) carries The clock signal delay preset duration received for the two-divider 62 of clock signal, and when delay is preset Clock signal after length is sent to receive the 2:1 multiplexer of the signal of this 2:1 multiplexer output, I.e. (n+1)th grade 2:1 multiplexer (only gives in Figure 11 in (n+1)th grade of 2:1 multiplexer The first trigger 71)；Wherein, the clock signal after postponing preset duration is sent to (n+1)th grade of 2:1 Multiplexer, refers to that the clock signal after postponing preset duration sends to (n+1)th grade of 2:1 multichannel multiple Touch with second in the clock signal terminal of the first trigger in device, and (n+1)th grade of 2:1 multiplexer Send out the clock signal terminal of device, and the clock signal that will postpone the clock signal complement after preset duration sends to the The clock signal terminal of the 3rd trigger in n+1 level 2:1 multiplexer, and (n+1)th grade of 2:1 multichannel The control end of the 2:1 selector in multiplexer；

Wherein, the cycle of the clock signal that the first trigger in n-th grade of 2:1 multiplexer receives Half, i.e. the difference of 1/f and overall delay again with described preset duration sum, many more than this 2:1 of described reception Path multiplexer output signal 2:1 multiplexer in trigger set up the time；Described overall delay 2:1 multichannel with the signal that the difference of described preset duration exports more than this 2:1 multiplexer of described reception The retention time of the trigger in multiplexer；Overall delay is the 2:1 choosing in n-th grade of 2:1 multiplexer Select time delay D ly_Mux of device and the two-divider 62 that clock signal is provided for n-th grade of 2:1 multiplexer Time delay D ly_DFF sum.

If the first level is high level, second electrical level is low level, and the effect of clock signal is believed along for clock Number rising edge, the trailing edge that non-active edge is clock signal of clock signal, 2:1 selector self When control end is high level, the first input end of self is connected with the outfan of self, and in the control of self When end processed is low level, the second input of self is connected with the outfan of self, two shown in Figure 11 The circuit timing diagram of frequency divider is as shown in figure 12.

In fig. 12, Dly_div is the two-divider providing control signal for the 2:1 selector in Figure 11 Time delay, Dly_Mux is the time delay of the 2:1 selector in Figure 11.In the clock signal that frequency is f When acting on edge Dly_div+Dly_Mux afterwards, the signal of 2:1 selector output changes, but by In, Figure 11 (Figure 11 only receives by the first trigger and illustrates as a example by the signal of 2:1 selector output, Second trigger receive 2:1 selector output signal similar) in output to the first trigger time Clock signal after chronotron, time delay Dly_B, therefore, Figure 11 receives the output of 2:1 selector Retention time of the first trigger of signal less than Dly_div+Dly_Mux-Dly_B, Figure 11 receives 2: The time of setting up of the first trigger of the signal of 1 selector output is less than 1/f+Dly_B -(Dly_div+Dly_Mux)。

Data_Mux in Figure 12 refers to the signal of 2:1 selector 74 output in Figure 11, Figure 12 In Data_DFF refer in Figure 11 first trigger 71 output signal.In Figure 12 CLK1_f_Dly is the signal of chronotron 111 output in Figure 11.

It is preferred that when two-divider comprises the second setting circuit, the set letter that this two-divider receives Number, it is destined to the set signal of the described high speed multiplexer synthesis electricity through described two-divider place Obtain after the clock signal synchronization that road receives.Wherein, the set signal that two-divider receives can be adopted The clock signal synchronization received with the combiner circuit of trigger Yu described two-divider place, two-divider The annexation of DIV and trigger DFF is as shown in figure 13 (only with in high speed multiplexer in Figure 13 Illustrate as a example by comprising two combiner circuits, certainly, high speed multiplexer can comprise many more than two Combiner circuit).In Figure 13, illustrate as a example by trigger is as d type flip flop, it is of course also possible to use Other trigger synchronizes, and only contains the two-divider in two combiner circuits in Figure 13, In practice, the signal after the synchronization of trigger output can go each conjunction driven in a multiplexer Becoming the two-divider in circuit, therefore, trigger needs bigger driving force, and the volume of trigger is bigger. Further comprises two buffers, the clock signal that the combiner circuit at two-divider place receives in fig. 13 CLK_f buffers through a buffer, is sent to the set signal SET warp of described high speed multiplexer Cross another buffer buffering.DIV represents that two-divider, DFF represent d type flip flop in fig. 13, three Angle icon representation buffer.

And when two-divider only comprises the first setting circuit, two-divider DIV and trigger DFF's Annexation is as shown in figure 14 (as a example by only comprising two combiner circuits in Figure 14 in high speed multiplexer Illustrate, certainly, high speed multiplexer can comprise many more than two combiner circuit).In Figure 14 also Including two buffers, the clock signal clk that the combiner circuit at two-divider place receives _ f passes through One buffer buffering, the set signal SET being sent to described high speed multiplexer buffers through another Device buffers.In Figure 14, the implication of icon can be found in the description of Figure 13.

The high speed multiplexer that the embodiment of the present invention provides also includes at least one buffer, described at least one Individual buffer uses clock trees distribution, for receiving the clock signal being sent to described high speed multiplexer, And provide clock signal for each combiner circuit in described high speed multiplexer；

Owing to exporting the buffer of clock signal for each combiner circuit in described high speed multiplexer Outfan is joined directly together, therefore, and the clock letter that the different combiner circuit in high speed multiplexer receives Number shake be consistent.

Alternatively, for each combiner circuit in the high speed multiplexer that the embodiment of the present invention provides, respectively The clock signal that individual combiner circuit receives, be all described in be sent to described high speed multiplexer clock letter Number obtaining after the buffer of same number at least one buffer described buffers, so high speed is many The time comparison of postponing a meeting or conference of the clock signal that each combiner circuit in path multiplexer receives is consistent.

Alternatively, during the output of the multiple combiner circuits in the high speed multiplexer that the embodiment of the present invention provides The transmission path of the clock signal of the buffer output of clock signal uses clock trees distribution, therefore, high-speed, multi-path The time delay of the clock signal that the different combiner circuit in multiplexer receives is more consistent.

The clock trees provided when the embodiment of the present invention is one-level, when this clock trees only includes a buffer, The structure of this clock trees is as shown in figure 15.Only comprising a buffer in clock trees shown in Figure 15, this delays Rush device to want to drive each combiner circuit in high speed multiplexer, therefore, the driving energy of this buffer Power wants enough strong.

The clock trees provided when the embodiment of the present invention is divided into three grades, when this clock trees includes multiple buffer, The structure of this clock trees is as shown in figure 16.In Figure 16, multiple buffers of the third level drive high-speed, multi-path jointly Each combiner circuit in multiplexer, it reduces the requirement of driving force to each buffer.

Buffer in the clock trees that the embodiment of the present invention provides uses clock trees distribution, and this clock trees receives to be sent out Give the clock signal of described high speed multiplexer, and be each synthesis in described high speed multiplexer Circuit provides clock signal.Owing to exporting clock signal for each combiner circuit in high speed multiplexer The outfan of buffer is joined directly together, and therefore, the different combiner circuit in high speed multiplexer receives The shake of clock signal be consistent.Owing to each combiner circuit in high speed multiplexer receives Clock signal, be all described in be sent to the clock signal of described high speed multiplexer through described at least one Clock signal after the buffer buffering of the same number in buffer, and in high speed multiplexer The transmission path of the clock signal of the buffer output of multiple combiner circuits output clock signal uses clock trees Distribution, therefore, the time delay of the clock signal that each combiner circuit in high speed multiplexer receives is consistent.

It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the mould in accompanying drawing Block or flow process are not necessarily implemented necessary to the present invention.

It will be appreciated by those skilled in the art that the module in the device in embodiment can describe according to embodiment Carry out being distributed in the device of embodiment, it is also possible to carry out respective change and be disposed other than one of the present embodiment Or in multiple device.The module of above-described embodiment can merge into a module, it is also possible to is further split into Multiple submodules.

The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.

Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.

Claims

1. a two-divider, it is characterised in that include the first gate-controlled switch, the second gate-controlled switch, Three gate-controlled switches, the 4th gate-controlled switch, the first phase inverter, the second phase inverter, the 3rd phase inverter, the 4th anti- Phase device, the first latch, the second latch and the first setting circuit；

Described second latch, for described set signal from effectively become invalid after, latch the 3rd anti-phase The signal of the input of device, and latch the signal of the input of described 4th phase inverter；

Described two-divider also includes the second setting circuit；

2. two-divider as claimed in claim 1, it is characterised in that when described set signal is effective, Described first control signal is set to second electrical level signal, and described second control signal is set to the first level letter Number.

3. a high speed multiplexer, it is characterised in that include at least one combiner circuit, Qi Zhongyi Individual combiner circuit includes k 2:1 multiplexer and individual two points as claimed in claim 1 or 2 of n Frequently device, one combiner circuit is for by one group 2ⁿRoad low speed signal synthesizes one group of one road high speed signal Circuit, k and n is positive integer,The transmission speed of a described road high speed signal is described 2ⁿ Road low speed signal sum；

4. high speed multiplexer as claimed in claim 3, it is characterised in that a 2:1 multichannel is multiple The first trigger, the second trigger, the 3rd trigger and 2:1 selector is included with device；

5. high speed multiplexer as claimed in claim 4, it is characterised in that when described 2:1 multichannel The half in the cycle of the clock signal that multiplexer receives and the difference of overall delay, less than receiving this 2:1 multichannel When setting up the time of trigger in the 2:1 multiplexer of the signal of multiplexer output, receives this 2:1 The 2:1 multiplexer of the signal of multiplexer output also includes chronotron；

6. the high speed multiplexer as described in as arbitrary in claim 3～5, it is characterised in that when described two When comprising the second setting circuit in frequency divider, the set signal that described two-divider receives, is described high speed The set signal that multiplexer a receives combiner circuit through described two-divider place receives Clock signal synchronization after obtain.

7. high speed multiplexer as claimed in claim 6, it is characterised in that described high-speed, multi-path is multiple Including at least one buffer with device, at least one buffer described uses clock trees distribution, sends out for receiving Give the clock signal of described high speed multiplexer, and be each synthesis in described high speed multiplexer Circuit provides clock signal；

8. high speed multiplexer as claimed in claim 7, it is characterised in that described high-speed, multi-path is multiple The clock signal received with each combiner circuit in device, be all described in be sent to described high-speed, multi-path multiplexing The clock signal of device obtains after the buffer of the same number at least one buffer described buffers.

9. high speed multiplexer as claimed in claim 8, it is characterised in that to multiple combiner circuits The transmission path of the clock signal of the buffer output of output clock signal uses clock trees distribution.