CN105932984B - Digital signal synthesis circuit and cascade digital signal combiner circuit - Google Patents
Digital signal synthesis circuit and cascade digital signal combiner circuit Download PDFInfo
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- CN105932984B CN105932984B CN201610408372.7A CN201610408372A CN105932984B CN 105932984 B CN105932984 B CN 105932984B CN 201610408372 A CN201610408372 A CN 201610408372A CN 105932984 B CN105932984 B CN 105932984B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
Abstract
A kind of digital signal synthesis circuit of present invention offer and cascade digital signal combiner circuit, the digital signal synthesis circuit includes that selection signal generates access, the first signal receiving path, second signal receiving path and data selector, data selector is used to generate the selection signal that access generates according to selection signal, selection synthesis is carried out to the signal that the first signal receiving path and second signal receiving path export, selection signal changes the time interval along the variation edge of the signal exported with the first signal receiving path and second signal receiving path in default range.The present invention generates the selection signal for being supplied to data selector by increasing selection signal generation access, so that the time interval on the variation edge for the signal that the variation edge of the selection signal is exported with the first signal receiving path and second signal receiving path is in default range, can occur data break-through to avoid data selector, so as to improve stability and the accuracy of generated data.
Description
Technical field
The invention belongs to digital signal synthesis fields, and in particular to a kind of digital signal synthesis circuit and cascade digital signal
Combiner circuit.
Background technology
The digital signal synthesis circuit application used with the sustainable development of high-speed digital communication, multi-channel data converter
It is increasingly extensive.Since multi-channel data sampling can reduce the frequency requirement of sampling clock, high speed data converter is generally adopted
Use multi-channel mode.And the transfer process after data acquisition then needs that multichannel data is first synthesized high-frequency data all the way, therebetween
Digital signal synthesis circuit must be used.Being effectively synthesized for multidigit high-speed data is realized under high-speed digital clocks, to entirely counting
It is had a very important significance according to the reliability of converting system.
However, when carrying out Data Synthesis using traditional high-speed digital signal circuit, especially cascade data is being carried out
When synthesis, data break-through may occur for data selector, finally make generated data unstable, substantially reduce data it is effective when
Between, more likely generated data is made to malfunction.
Invention content
A kind of digital signal synthesis circuit of present invention offer and cascade digital signal combiner circuit, to solve using traditional
When digital signal synthesis circuit carries out Data Synthesis, generated data is steady caused by there is data break-through due to data selector
The qualitative and relatively low problem of accuracy.
According to a first aspect of the embodiments of the present invention, a kind of digital signal synthesis circuit is provided, including selection signal generates
Access, the first signal receiving path, second signal receiving path and data selector, the data selector are used for according to
Selection signal generates the selection signal that access generates, defeated to the first signal receiving path and the second signal receiving path
The signal gone out carries out selection synthesis, variation edge and the first signal receiving path and the second signal of the selection signal
The time interval on the variation edge of the signal of receiving path output is in default range；
The first clock signal for being input to each digital signal synthesis circuit in prime digital signal synthesis circuit is input
To the two divided-frequency clock letter of the second clock signal of each digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit
Number, and the second clock signal for being input to each digital signal synthesis circuit in prime digital signal synthesis circuit is to be input to phase
First clock signal of each digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit；
For every grade of digital signal synthesis circuit, setting is there are one d type flip flop is divided, for every grade of digital signal synthesis electricity
The frequency dividing d type flip flop on road, clock end are connect with the output end Q of the frequency dividing d type flip flop of adjacent rear class digital signal synthesis circuit,
Input terminal is connect with its output end Q, and output end and each digital signal synthesis electricity in the digital signal synthesis circuit of this grade
The input terminal that first signal receiving path, the clock end of second signal receiving path and the selection signal on road generate access connects
It connects；This grade number signal synthesis circuit in each digital signal synthesis circuit selection signal generate access clock end with
The output end Q connections of the frequency dividing d type flip flop of the adjacent rear class digital signal synthesis circuit.
In an optional implementation manner, it includes the first d type flip flop, the first D that the selection signal, which generates access,
The input terminal of trigger inputs the first clock signal, and clock end inputs second clock signal, the output end Q connections data selection
The selection signal input terminal of device.
In another optional realization method, the first signal receiving path includes the second d type flip flop, and described second
The input terminal of d type flip flop inputs the first signal, and clock end inputs first clock signal, and output end Q is selected with the data
The second end of device connects；
The second signal receiving path includes third d type flip flop and four d flip-flop, the third d type flip flop it is defeated
Enter end input second signal, clock end inputs first clock signal, the input terminal of output end Q and the four d flip-flop
Connection, the clock end of the four d flip-flop input first clock signal, and the of output end Q and the data selector
One end connects.
In another optional realization method, first d type flip flop is become by the first kind in the second clock signal
Change along triggering, second d type flip flop and the third d type flip flop first kind described in first clock signal change edge
Triggering, the four d flip-flop change edge by changing with the first kind in first clock signal along the second opposite class
Triggering, data selector selection when the selection signal is first kind level are input to the signal output of its second end,
Select the signal for being input to its first end defeated when the selection signal is the second class level opposite with the first kind level
Go out.
In another optional realization method, closed for each two digital signal in prime digital signal synthesis circuit
At circuit, the first signal of one of digital signal synthesis circuit output is input in adjacent rear class digital signal synthesis circuit
The input terminal of the third d type flip flop of corresponding digital signals combiner circuit, the second signal of another digital signal synthesis circuit output
It is input to the input terminal of the second d type flip flop of the corresponding digital signals combiner circuit in adjacent rear class digital signal synthesis circuit.
In another optional realization method, the number of digital signal synthesis circuit in prime digital signal synthesis circuit
It is twice of the number of digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit.
The beneficial effects of the invention are as follows：
1, the present invention generates the selection signal for being supplied to data selector by increasing selection signal generation access, so that
The selection signal is different from the first signal receiving path and the clock signal of second signal receiving path is supplied to, and makes the selection
The variation of signal is between the time on the variation edge of the signal exported with the first signal receiving path and second signal receiving path
It is interposed between in default range, can occur data break-through to avoid data selector, so as to improve the stability of generated data
And accuracy；
2, by using the first d type flip flop, alternatively signal generates access to the present invention, relatively simple for structure, and passes through
First d type flip flop carries out sampling generated selection signal using the first clock signal of second clock signal pair, can be further
Ensure the variation of selection signal along the variation edge of the signal exported with the first signal receiving path and second signal receiving path
There is data break-through so as to further avoid data selector, thus further carries in default range in time interval
The stability of high generated data and accuracy；
3, it by the present invention in that the first clock signal is the two divided-frequency clock signal of second clock signal, can further protect
Demonstrate,prove the selection signal that access generates occurs for selection signal variation edge and the first signal receiving path and second signal receiving path
There is number in default range so as to further avoid data selector in the time interval on the variation edge of the signal of output
According to break-through, stability and the accuracy of generated data are thus further improved；
4, since cascade digital signal combiner circuit uses the digital signal synthesis circuit in the present invention, and in the present invention
The selection signal for being supplied to data selector is generated by increasing selection signal generation access in digital signal synthesis circuit, it can
So that the selection signal is different from the first signal receiving path and the clock signal of second signal receiving path is supplied to, and make this
The variation of selection signal along the variation edge of the signal exported with the first signal receiving path and second signal receiving path when
Between be spaced in default range, therefore through the invention can to avoid to data carry out grade be unified into when, before adjacent
Data selector data break-through caused by random phase difference between the clock signal of two-stage digital signal synthesis circuit afterwards, from
And stability and the accuracy of cascade data synthesis can be improved；
5, by the present invention in that being input to first of each digital signal synthesis circuit in prime digital signal synthesis circuit
Clock signal is to be input to the second clock signal of each digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit
Two divided-frequency clock signal, and be input to the second clock of each digital signal synthesis circuit in prime digital signal synthesis circuit
Signal is the first clock signal for being input to each digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit, thus
Can ensure selection signal in each digital signal synthesis circuit generate the variation of the selection signal that access generates along with its first
The time interval on the variation edge of signal receiving path and the signal of second signal receiving path output in default range, to
It can further avoid data selector and data break-through occur, thus further improve the stability of generated data and accurate
Degree；
6, a frequency dividing d type flip flop is arranged by being directed to every grade of digital signal synthesis circuit in the present invention, can be to after adjacent
The clock signal of the frequency dividing d type flip flop output of the digital signal synthesis circuit of grade carries out two divided-frequency, simple in structure, and can make input
The first clock signal to each digital signal synthesis circuit in prime digital signal synthesis circuit is to be input to adjacent rear series
The two divided-frequency clock signal of the second clock signal of each digital signal synthesis circuit, is input to prime in word signal synthesis circuit
The second clock signal of each digital signal synthesis circuit is to be input to adjacent rear class digital signal in digital signal synthesis circuit
First clock signal of each digital signal synthesis circuit in combiner circuit, it is possible thereby to ensure each digital signal synthesis circuit
The variation that middle selection signal generates the selection signal that access generates is logical along being received with its first signal receiving path and second signal
The time interval on the variation edge of the signal of road output occurs in default range so as to further avoid data selector
Data break-through further increases stability and the accuracy of generated data；
7, by the present invention in that the signal of each two digital signal synthesis circuit output of prime digital signal synthesis circuit
As the input signal of one in adjacent rear class digital signal synthesis circuit digital signal synthesis circuit, may be implemented data by
Grade synthesis；
8, by the present invention in that the number of digital signal synthesis circuit is adjacent rear class in prime digital signal synthesis circuit
Twice of the number of digital signal synthesis circuit in digital signal synthesis circuit, minimum component may be used realize data by
Grade synthesis.
Description of the drawings
Fig. 1 is one embodiment circuit diagram of digital signal synthesis circuit of the present invention；
Fig. 2 is sequence diagram when carrying out single level data synthesis using traditional high-speed digital signal circuit；
Fig. 3 is the sequence diagram of digital signal synthesis circuit in Fig. 1；
Fig. 4 is one embodiment circuit diagram of cascade digital signal combiner circuit of the present invention；
Fig. 5 is sequence diagram when carrying out cascade data synthesis using traditional digital signal synthesis circuit；
Fig. 6 is the sequence diagram of Fig. 4 cascade digital signal synthesis circuits；
Fig. 7 is one embodiment circuit diagram of cascade digital signal combiner circuit of the present invention.
Specific implementation mode
In order to make those skilled in the art more fully understand the technical solution in the embodiment of the present invention, and make of the invention real
The above objects, features, and advantages for applying example can be more obvious and easy to understand, below in conjunction with the accompanying drawings to technical side in the embodiment of the present invention
Case is described in further detail.
In the description of the present invention, unless otherwise specified and limited, it should be noted that term " connection " should do broad sense reason
Solution, for example, it may be mechanical connection or electrical connection, can also be the connection inside two elements, can be directly connected, also may be used
Indirectly connected through an intermediary, for the ordinary skill in the art, can understand as the case may be above-mentioned
The concrete meaning of term.
It is one embodiment circuit diagram of digital signal synthesis circuit of the present invention referring to Fig. 1.The digital signal synthesis circuit
May include that selection signal generates access 100, the first signal receiving path 200, second signal receiving path 300 and data selection
Device 400, the data selector 400 can be used for generating the selection signal that access 100 generates according to the selection signal, to institute
The signal for stating the first signal receiving path 200 and the second signal receiving path 300 output carries out selection synthesis, the selection
Change of the variation of signal along the signal exported with the first signal receiving path 200 and the second signal receiving path 300
Change the time interval on edge in default range.
In the present embodiment, it may include the first d type flip flop 110 that the selection signal, which generates access 100, the first D triggerings
The input terminal D of device 110 inputs the first clock signal, and clock end CK inputs second clock signal, the output end Q connections data choosing
Select the selection signal input terminal S of device 400.It should be noted that：Selection signal generates access in addition to the first D triggerings may be used
Device can also use other circuits, as long as the variation edge of the selection signal generated and the first signal receiving path and second signal
The time interval on the variation edge of the signal of receiving path output is in default range.
First trigger 110 can be by first kind variation be along triggering in the second clock signal CLK2, by using the
Two the first clock signals of clock signal pair sample, and can obtain selection signal, and export to data selector 400.This
One signal receiving path 200 may include the second d type flip flop 210, input terminal D the first letters of input of second d type flip flop 210
Number D1, clock end CK input first clock signal clk 1, and output end Q and the second end B of the data selector 400 connect
It connects.The second signal receiving path 300 may include third d type flip flop 310 and four d flip-flop 320, the 3rd D triggerings
The input terminal D of device 310 inputs second signal D2, and clock end CK inputs first clock signal clk 1, output end Q and described the
The clock end CK of the input terminal D connections of four d flip-flop 320, the four d flip-flop 320 inputs first clock signal
CLK1, output end Q are connect with the first end A of the data selector 400.Four d flip-flop 310 can to second signal D2 into
Row misphase operates, so that second signal D2 relative first signals D1 postpones 180 °.
Wherein, the first d type flip flop 110 can be described along triggering by first kind variation in the second clock signal CLK2
Second d type flip flop 210 and the third d type flip flop 310 first kind described in first clock signal clk 1 change
Along triggering, the four d flip-flop 320 can be by changing with the first kind along opposite in first clock signal clk 1
Second class variation along triggering, data selector 400 can the selection signal be the first kind level when selection input its second
The signal at end exports, when the selection signal is the second class level opposite with the first kind level selection input its first
The signal at end exports.For example, the first d type flip flop 110 can be triggered by rising edge in second clock signal CLK2, the 2nd D triggerings
Device 210 and third d type flip flop 310 can be triggered by rising edge in the first clock signal clk 1, and four d flip-flop 320 can be by
Failing edge triggers in first clock signal clk 1, and data selector 400 selection can input it when selection signal is high level
The signal of second end exports, the signal output of its first end of selection input when selection signal is low level.In addition, the first clock
Signal CLK1 can be the two divided-frequency clock signal of second clock signal CLK2.
It has been investigated that when carrying out Data Synthesis using traditional high-speed digital signal circuit, data selector may
The reason of data break-through occurs is：Due to the first signal receiving path and second signal in traditional digital signal synthesis circuit
The clock signal of receiving path is identical as the selection signal in data selector so that the change of the selection signal of numerical selector
Change the variation along the signal inputted with it along close proximity.Single level data conjunction is being carried out using traditional high-speed digital signal circuit
Cheng Shi, sequence diagram can with as shown in Fig. 2, in figure CLK indicate the first signal receiving path and second signal receiving path when
Clock signal, D1 indicate that the first signal for being input to the first signal receiving path, D2 expressions are input to second signal receiving path
Second signal, A indicate that the first signal receiving path is supplied to the signal of data selector first end, B to indicate that second signal receives
Access is supplied to the signal of data selector second end, S to indicate that the selection signal of data selector, Z indicate that data selector is defeated
The signal gone out.As seen from Figure 2, along the variation with signal A, B along close proximity, this results in counting for the variation of selection signal S
It is likely to occur data break-through according to selector, it is unstable so as to cause generated data, or even occur mistake completely.
Believed with the two divided-frequency clock that the first clock signal clk 1 in digital signal synthesis circuit is second clock signal CLK2
For number, the sequence diagram of digital signal synthesis circuit is as shown in Figure 3 in the present embodiment.As seen from Figure 3, selection signal S
Variation keeps larger time interval along the variation edge with signal A, B, it is possible thereby to data selector is avoided data break-through occur,
So as to improve stability and the accuracy of generated data.
As seen from the above-described embodiment, the present invention is supplied to data selector by increasing selection signal generation access to generate
Selection signal, so as to the selection signal and be supplied to the clock signal of the first signal receiving path and second signal receiving path
Difference, and make the variation of the selection signal along the signal exported with the first signal receiving path and second signal receiving path
Change the time interval on edge in default range, can occur data break-through to avoid data selector, be closed so as to improve
Stability at data and accuracy.
In addition, the present invention is by using the first d type flip flop, alternatively signal generates access, relatively simple for structure, and
It carries out sampling generated selection signal, Ke Yijin using the first clock signal of second clock signal pair by the first d type flip flop
One step ensures variation of the variation along the signal exported with the first signal receiving path and second signal receiving path of selection signal
There is data break-through, thus into one in default range so as to further avoid data selector in the time interval on edge
Step improves stability and the accuracy of generated data.By the present invention in that the first clock signal is two points of second clock signal
Frequency clock signal may further ensure that variation edge and the reception of the first signal of the selection signal that access generates occur for selection signal
The time interval on the variation edge of access and the signal of second signal receiving path output is in default range, so as into one
Step avoids data selector from data break-through occur, thus further improves stability and the accuracy of generated data.
It is one embodiment circuit diagram of cascade digital signal combiner circuit of the present invention referring to Fig. 4.The cascade digital signal
Combiner circuit may include multilevel digital signals combiner circuit along outbound course is input to, and be wrapped in every grade of digital signal synthesis circuit
Include at least one above-mentioned digital signal synthesis circuit.
In the present embodiment, for each two digital signal synthesis circuit in prime digital signal synthesis circuit, wherein one
First signal of a number signal synthesis circuit output is input to corresponding digital signals in adjacent rear class digital signal synthesis circuit
The input terminal of the third d type flip flop of combiner circuit, the second signal of another digital signal synthesis circuit output be input to it is adjacent after
The input terminal of second d type flip flop of the corresponding digital signals combiner circuit in the digital signal synthesis circuit of grade.Prime digital signal
The number of digital signal synthesis circuit is digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit in combiner circuit
Twice of number.By the present invention in that the letter of each two digital signal synthesis circuit output of prime digital signal synthesis circuit
Input signal number as one in adjacent rear class digital signal synthesis circuit digital signal synthesis circuit, may be implemented data
It synthesizes step by step.By the present invention in that the number of digital signal synthesis circuit is adjacent rear series in prime digital signal synthesis circuit
Minimum component may be used to realize data step by step in twice of the number of digital signal synthesis circuit in word signal synthesis circuit
Synthesis.
Wherein, the first clock signal for being input to each digital signal synthesis circuit in prime digital signal synthesis circuit is
When being input to the two divided-frequency of the second clock signal of each digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit
Clock signal, and the second clock signal for being input to each digital signal synthesis circuit in prime digital signal synthesis circuit is input
To the first clock signal of each digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit, it is possible thereby to ensure each
Selection signal generates the variation for the selection signal that access generates along logical with the reception of its first signal in a number signal synthesis circuit
The time interval on the variation edge of the signal of road and the output of second signal receiving path is in default range, so as to further
It avoids data selector from data break-through occur, thus further improves stability and the accuracy of generated data.
In an optional implementation manner, for every grade of digital signal synthesis circuit, there are one frequency dividing D triggerings for setting
Device, for the frequency dividing d type flip flop of every grade of digital signal synthesis circuit, clock end and adjacent rear class digital signal synthesis circuit
The output end Q connections of d type flip flop are divided, input terminal is connect with its output end Q, and output end and the digital signal synthesis circuit of this grade
In the second d type flip flop of each digital signal synthesis circuit, the clock end of third d type flip flop and four d flip-flop and
The input terminal of first d type flip flop connects；First D of each digital signal synthesis circuit in this grade number signal synthesis circuit
The clock end of trigger is connect with the output end Q of the frequency dividing d type flip flop of the adjacent rear class digital signal synthesis circuit.It needs to note
Meaning be：In the output stage digital signal synthesis circuit of cascade digital signal combiner circuit, the clock end for dividing d type flip flop is defeated
Enter clock signal clk.
For the present invention by being directed to every grade of digital signal synthesis circuit, one frequency dividing d type flip flop of setting can be to adjacent rear class
The clock signal of the frequency dividing d type flip flop output of digital signal synthesis circuit carries out two divided-frequency, simple in structure, and can make to be input to
The first clock signal of each digital signal synthesis circuit is to be input to adjacent rear class number in prime digital signal synthesis circuit
The two divided-frequency clock signal of the second clock signal of each digital signal synthesis circuit, is input to preceding series in signal synthesis circuit
The second clock signal of each digital signal synthesis circuit is to be input to adjacent rear class digital signal to close in word signal synthesis circuit
At the first clock signal of each digital signal synthesis circuit in circuit, it is possible thereby to ensure in each digital signal synthesis circuit
Selection signal generates variation edge and its first signal receiving path and the second signal receiving path for the selection signal that access generates
There is number in default range so as to further avoid data selector in the time interval on the variation edge of the signal of output
According to break-through, stability and the accuracy of generated data are further increased.
When carrying out cascade data synthesis using traditional digital signal synthesis circuit, cascade digital signal combiner circuit
Sequence diagram is as shown in Figure 5.Since the clock of adjacent front stage digital signal synthesis circuit in cascade digital signal combiner circuit is negative
Difference is carried, therefore the path delay of digital signal synthesis circuit at different levels is different, there are phase differences.Prime digital signal synthesis circuit
Clock signal clk 1 and the clock signal clk 2 of adjacent rear class data-signal combiner circuit between phase difference variation can adopt
Indicate that is, clock signal CLK2 rising edges can change within the scope of dotted line with the dotted line near clock signal CLK2 rising edges, this
Sample can cause the variation of the selection signal of data selector in adjacent rear class digital signal synthesis circuit along (including rising edge and under
Drop edge) also change within the scope of dotted line.When the variation edge of the selection signal of data selector in subset of numbers signal synthesis circuit
When variation with its signal A, B is along close proximity, which is easy to that data break-through occurs, so as to cause generated data
It is unstable, or even occur mistake completely.
Believed with the two divided-frequency clock that the first clock signal clk 1 in digital signal synthesis circuit is second clock signal CLK2
For number, the sequence diagram of digital signal synthesis circuit is as shown in fig. 6, the first clock signal clk 1 and second in figure in the present embodiment
The phase difference variation of clock signal clk 2 may be used dotted line near second clock signal CLK2 rising edges and indicate, i.e., when second
Clock signal CLK2 rising edges can change within the scope of dotted line, can cause in this way data selector selection signal S rising edges and
Failing edge also changes within the scope of dotted line.It will be appreciated from fig. 6 that even if second clock signal CLK2 is with respect to the first clock signal clk 1
Phase difference changes in wide range, the selection signal S of data selector still with data A, B justified, with data A, B
Variation is along larger time slot is kept, it is possible thereby to avoid data selector from data break-through occur, so as to improve synthesis
The stability of data and accuracy.
As seen from the above-described embodiment, the digital signal synthesis in the present invention is used due to cascade digital signal combiner circuit
Circuit, and it is supplied to data to select to generate by increasing selection signal generation access in digital signal synthesis circuit in the present invention
The selection signal of device can make the selection signal and the clock for being supplied to the first signal receiving path and second signal receiving path
Signal is different, and makes the variation of the selection signal along the letter exported with the first signal receiving path and second signal receiving path
Number variation edge time interval in default range, therefore through the invention can be to avoid being unified into carrying out grade to data
When, data select caused by the random phase difference between the clock signal of adjacent front and back stages digital signal synthesis circuit
Device data break-through, so as to improve stability and the accuracy of cascade data synthesis.
It is the circuit diagram of another embodiment of cascade digital signal combiner circuit of the present invention referring to Fig. 7.The present embodiment
In, for synthesizing an output signal to 8 input signals.The cascade digital signal combiner circuit may include three-level number
Signal synthesis circuit, wherein first order digital signal synthesis circuit 710 may include 4 digital signal synthesis circuits, the second level
Digital signal synthesis circuit 720 may include 2 digital signal synthesis circuits, and third level digital signal synthesis circuit 730 can be with
Including 1 digital signal synthesis circuit.Wherein, in every grade of digital signal synthesis circuit each digital signal synthesis circuit first
Clock signal and second clock signal are all identical, and the first clock signal of third level digital signal synthesis circuit 730 is believed for clock
The two divided-frequency signal of number CLK, second clock signal are clock signal clk；Second level digital signal synthesis circuit 720 first when
Clock signal is four fractional frequency signals of clock signal clk, and second clock signal is the two divided-frequency signal of clock signal clk, the first order
First clock signal of digital signal synthesis circuit 710 is eight fractional frequency signals of clock signal clk, and second clock signal is clock
Four fractional frequency signals of signal CLK, and the signal of its input is D0<39>~D7<39>.
Believe for first order digital signal synthesis circuit 710, second level digital signal synthesis circuit 720 and third level number
Number combiner circuit 730 is correspondingly arranged on the first frequency dividing d type flip flop 711, second frequency dividing d type flip flop 721 and third frequency dividing D triggerings
Device 731.Wherein, clock end the input clock signal CLK, input terminal D of third frequency dividing d type flip flop 731 are connect with its output end Q,
Output end Q can export the two divided-frequency signal of clock signal clk；The clock end input clock signal of second frequency dividing d type flip flop 721
The two divided-frequency signal of CLK, input terminal D are connect with its output end Q, and output end Q can export four frequency dividing letters of clock signal clk
Number；Four fractional frequency signals of the clock end input clock signal CLK of first frequency dividing d type flip flop 711, input terminal D connect with its output end Q
It connects, output end Q can export eight fractional frequency signals of clock signal clk.
For each digital signal synthesis circuit in first order digital signal synthesis circuit 710, digital signal synthesis electricity
The input terminal of the second d type flip flop, the clock end of third d type flip flop and four d flip-flop and the first d type flip flop can be in road
The output end Q of connection the first frequency dividing d type flip flop 711, the input terminal of the first d type flip flop can connect the second frequency dividing d type flip flop 721
Output end Q (not shown)s.For each digital signal synthesis circuit in second level digital signal synthesis circuit 720,
Second d type flip flop, the clock end of third d type flip flop and four d flip-flop and the first D triggerings in digital signal synthesis circuit
The input terminal of device can connect the output end Q of the second frequency dividing d type flip flop 721, and the input terminal of the first d type flip flop can connect first
Divide the output end Q (not shown)s of d type flip flop 711.For each number in third level digital signal synthesis circuit 730
Signal synthesis circuit, the clock end of the second d type flip flop, third d type flip flop and four d flip-flop in digital signal synthesis circuit,
And first the input terminal of d type flip flop can connect the output end Q of the first frequency dividing d type flip flop 711, the input of the first d type flip flop
End can be with input clock signal CLK.
The operation principle of the present embodiment is as follows：
The first signal receiving path and second of each digital signal synthesis circuit in first order digital signal synthesis circuit
When signal receiving path carries out data sampling, using eight fractional frequency signal fs/8CLK of clock signal clk, the choosing of data selector
Select signal by four fractional frequency signal fs/4CLK of clock signal clk to eight fractional frequency signal fs/8CLK samplings of clock signal clk after
It obtains, the frequency of the first order generated data of first order digital signal synthesis circuit output is the 2 of input data D0~D7 frequencies
Times；The the first signal receiving path and second signal of each digital signal synthesis circuit connect in the digital signal synthesis circuit of the second level
When receiving access progress data sampling, using four fractional frequency signal fs/4CLK of clock signal clk, the selection signal of data selector
By the two divided-frequency signal fs/2CLK of clock signal clk to being obtained after four fractional frequency signal fs/4CLK samplings of clock signal clk, the
The frequency of the second level generated data of two-stage digital signal synthesis circuit output is 4 times of input data D0~D7 frequencies；Third
The the first signal receiving path and second signal receiving path of each digital signal synthesis circuit in the digital signal synthesis circuit of grade
When carrying out data sampling, using the two divided-frequency signal fs/2CLK of clock signal clk, the selection signal of data selector is by clock
Signal CLK after the two divided-frequency signal fs/2CLK samplings of clock signal clk to obtaining, third level digital signal synthesis circuit output
The frequency of third level generated data be 8 times of input data D0~D7 frequencies.Hereby it is achieved that the high speed of digital signal is closed
At.
As seen from the above-described embodiment, the digital signal synthesis in the present invention is used due to cascade digital signal combiner circuit
Circuit, and it is supplied to data to select to generate by increasing selection signal generation access in digital signal synthesis circuit in the present invention
The selection signal of device can make the selection signal and the clock for being supplied to the first signal receiving path and second signal receiving path
Signal is different, and makes the variation of the selection signal along the letter exported with the first signal receiving path and second signal receiving path
Number variation edge time interval in default range, therefore through the invention can be to avoid being unified into carrying out grade to data
When, data select caused by the random phase difference between the clock signal of adjacent front and back stages digital signal synthesis circuit
Device data break-through, so as to improve stability and the accuracy of cascade data synthesis.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the present invention
Its embodiment.This application is intended to cover the present invention any variations, uses, or adaptations, these modifications, purposes or
Person's adaptive change follows the general principle of the present invention and includes undocumented common knowledge in the art of the invention
Or conventional techniques.The description and examples are only to be considered as illustrative, and true scope and spirit of the invention are by following
Claim is pointed out.
It should be understood that the invention is not limited in the precision architectures for being described above and being shown in the accompanying drawings, and
And various modifications and changes may be made without departing from the scope thereof.The scope of the present invention is limited only by the attached claims.
Claims (6)
1. a kind of cascade digital signal combiner circuit, which is characterized in that it includes that multilevel digital signals close that edge, which is input to outbound course,
At circuit, every grade of digital signal synthesis circuit includes digital signal synthesis circuit, and the digital signal synthesis circuit includes choosing
It selects signal and generates access, the first signal receiving path, second signal receiving path and data selector, the data selector is used
In generating the selection signal that access generates according to the selection signal, to the first signal receiving path and the second signal
The signal of receiving path output carries out selection synthesis, variation edge and the first signal receiving path and the institute of the selection signal
The time interval on variation edge of the signal of second signal receiving path output is stated in default range；
The first clock signal for being input to each digital signal synthesis circuit in prime digital signal synthesis circuit is to be input to phase
The two divided-frequency clock signal of first clock signal of each digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit, and
Be input to each digital signal synthesis circuit in prime digital signal synthesis circuit second clock signal be input to it is adjacent after
First clock signal of each digital signal synthesis circuit in the digital signal synthesis circuit of grade；
For every grade of digital signal synthesis circuit, setting is there are one dividing d type flip flop, for every grade of digital signal synthesis circuit
Divide d type flip flop, the output end of clock end and the frequency dividing d type flip flop of adjacent rear class digital signal synthesis circuitConnection, it is defeated
Enter end and its output endConnection, and output end and each digital signal synthesis circuit in the digital signal synthesis circuit of this grade
The first signal receiving path, the clock end of second signal receiving path and selection signal generate the input terminal connection of access；
The selection signal of each digital signal synthesis circuit generates clock end and the institute of access in this grade number signal synthesis circuit
State the output end of the frequency dividing d type flip flop of adjacent rear class digital signal synthesis circuitConnection.
2. circuit according to claim 1, which is characterized in that it includes the first d type flip flop that the selection signal, which generates access,
The input terminal of first d type flip flop inputs the first clock signal, and clock end inputs second clock signal, output end Q connections institute
State the selection signal input terminal of data selector.
3. circuit according to claim 2, which is characterized in that the first signal receiving path includes the second d type flip flop,
The input terminal of second d type flip flop inputs the first signal, and clock end inputs first clock signal, output end Q with it is described
The second end of data selector connects；
The second signal receiving path includes third d type flip flop and four d flip-flop, the input terminal of the third d type flip flop
Second signal is inputted, clock end inputs first clock signal, and output end Q is connect with the input terminal of the four d flip-flop,
The clock end of the four d flip-flop inputs first clock signal, and output end Q and the first end of the data selector connect
It connects.
4. circuit according to claim 3, which is characterized in that first d type flip flop is by the second clock signal
First kind variation is along triggering, and second d type flip flop and the third d type flip flop are first described in first clock signal
Class variation is along triggering, and the four d flip-flop in first clock signal with the first kind by changing along opposite second
Along triggering, data selector selection when the selection signal is first kind level is input to the letter of its second end for class variation
Number output, the selection signal be the second class level opposite with the first kind level when select be input to its first end
Signal exports.
5. circuit according to claim 1, which is characterized in that for each two number in prime digital signal synthesis circuit
Word signal synthesis circuit, the first signal of one of digital signal synthesis circuit output are input to adjacent rear class digital signal and close
At the input terminal of the third d type flip flop of corresponding digital signals combiner circuit in circuit, another digital signal synthesis circuit output
Second signal is input to the second d type flip flop of the corresponding digital signals combiner circuit in adjacent rear class digital signal synthesis circuit
Input terminal.
6. circuit according to claim 1, which is characterized in that digital signal synthesis electricity in prime digital signal synthesis circuit
The number on road is twice of the number of digital signal synthesis circuit in adjacent rear class digital signal synthesis circuit.
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| CN201610408372.7A CN105932984B (en) | 2016-06-12 | 2016-06-12 | Digital signal synthesis circuit and cascade digital signal combiner circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6560661B2 (en) * | 1997-04-25 | 2003-05-06 | Kabushiki Kaisha Toshiba | Data receiver that performs synchronous data transfer with reference to memory module |
| CN102709118A (en) * | 2012-06-14 | 2012-10-03 | 浙江大学 | Economizer of alternative-current contactor |
| CN103873047A (en) * | 2014-03-18 | 2014-06-18 | 华为技术有限公司 | Two-divided-frequency device and high-speed multiplexer |
-
2016
- 2016-06-12 CN CN201610408372.7A patent/CN105932984B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6560661B2 (en) * | 1997-04-25 | 2003-05-06 | Kabushiki Kaisha Toshiba | Data receiver that performs synchronous data transfer with reference to memory module |
| CN102709118A (en) * | 2012-06-14 | 2012-10-03 | 浙江大学 | Economizer of alternative-current contactor |
| CN103873047A (en) * | 2014-03-18 | 2014-06-18 | 华为技术有限公司 | Two-divided-frequency device and high-speed multiplexer |
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| CN105932984A (en) | 2016-09-07 |
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