CN103872121B - HFET based on channel array structure - Google Patents
HFET based on channel array structure Download PDFInfo
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- CN103872121B CN103872121B CN201410113967.0A CN201410113967A CN103872121B CN 103872121 B CN103872121 B CN 103872121B CN 201410113967 A CN201410113967 A CN 201410113967A CN 103872121 B CN103872121 B CN 103872121B
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Abstract
The present invention relates to a kind of HFET based on channel array structure, including hetero-junctions, described hetero-junctions includes first that stacking from top to bottom is arranged, second semiconductor layer, first, second semiconductor interface is formed with two-dimensional electron gas, arrange active on first semiconductor layer, leakage and grid, grid is arranged at source, between drain electrode, and it is provided with channel array in the hetero-junctions below grid, this channel array is made up of a plurality of raceway groove being set up in parallel, the two ends of any of which raceway groove point to source electrode and drain electrode respectively, and cover the grid metal level for constituting grid the most continuously on the upper surface of arbitrary raceway groove and two side.The present invention uses structure based on channel array design, and form gate-all-around structure by grid metal being covered the sidewall on the top of raceway groove and both sides, thus enhance the modulation capability to raceway groove, it is applicable to all semi-conductor electronic devices worked based on two-dimensional electron gas at heterojunction boundary, and the various requirement of actual application can be met simultaneously.
Description
The application is Application No. 201110083011.7, filing date on April 2nd, 2011, entitled " based on channel array
The HFET of structure " divisional application.
Technical field
The present invention relates to a kind of semi-conductor electronic device, particularly relate to a kind of heterojunction field based on channel array structure effect
Answer transistor.
Background technology
Heterojunction semiconductor is made up of two or more different semi-conducting materials.Owing to having between different semi-conducting materials
Different the physical-chemical parameters (such as electron affinity, band structure, dielectric constant, lattice paprmeter etc.), meeting at its contact interface
Produce the mismatch of various physico-chemical properties, so that hetero-junctions has many new features.The base of HFET
This structure is exactly to comprise a hetero-junctions being made up of wide bandgap material and low bandgap material.In this hetero-junctions, doped type N impurity
Wide bandgap material provide a large amount of electronics, or due to strong polarization material as the offer layer of electronics to the low bandgap material that undopes
Polarity effect cause a large amount of electronics, these electron accumulation are in the triangular quantum well formed by the energy difference of bi-material conduction band
Form two-dimensional electron gas.Due to the scattering departing from alms giver's spur, and present the highest mobility.Utilize high concentration,
The two-dimensional electron gas of high mobility is modulated by gate voltage as conducting channel, the electron concentration in raceway groove, in grid both sides
Source region and drain region are set, i.e. form HFET.Due to its have the highest cut-off frequency and frequency of oscillation,
High electric current density, less short channel effect and good noise performance, HFET is put in Microwave Low-Noise
Big device, high-speed digital integrated circuit, high speed static random access memory, high temperature circuit, power amplifier and micro-wave resonator circuit
Aspect has the widest application.
At present, there have been very many material systems to be applied to HFET, and had been achieved for non-
The achievement of Chang Youyi.If GaAs radical heterojunction field effect transistor (HFET) is in high frequency, hyperfrequency and Microwave Radio frequency
Field is widely used.And in millimere-wave band, InP is paid close attention to by people due to its superior performance compared with GaAs.
The breakdown electric field of InP, electronics average speed are the highest, and bigger existing in hetero-junctions InAlAs/InGaAs interface
Conduction band discontinuity, two-dimensional electron gas density are big, electron mobility is high, so InP-base device is more suitable for frequency applications in raceway groove.
Further, the HFET of Si/SiGe base and the most concerned GaN base etc. are due to its material and formation
Have the advantage that after hetero-junctions, it is similarly subjected to the concern of people.
Generally, hetero-junctions just has the most highdensity two-dimensional electron gas in the case of not outer bias, formation
Device is depletion device.But, from the perspective of application, the HEMT of enhancement mode has a lot of advantage.Such as, at high frequency PA
With LNA application aspect, enhancement mode HEMT can be removed the use in negative voltage source from, thus be reduced complexity and the cost of circuit；?
Integrated formed direct-coupling field-effect transistor logic (DCFL) of digital application aspect, depletion type and enhancement mode HEMT can
To provide simplest circuit structure；In terms of power electronics applications, due to system reliability and the requirement of cost, usually not
Negative supply, thus the core switching device being applied to power electronic system must be enhancement mode (normally-off) device.Heterojunction field
One important application of effect transistor is in high frequency, high-speed circuit system, and this is accomplished by higher device cut-off frequency and
High oscillation frequency.
At present, it is achieved the technology of enhancement mode HEMT device has the so-called GIT skill of groove gate technique, fluorine treatment technology and p-type grid
Art, all there is certain weak point in these technology, especially in terms of group iii nitride semiconductor HEMT, such as groove gate technique
Technique controlling difficulty very big, the reliability of fluorine treatment technology and GIT technology need checking.It addition, based on common HEMT
Structure, it is long that the lifting of the frequency performance of device depends on reduction grid, and present technology has been realized in the long 30-50nm's of grid
Device, if needing to improve further the frequency characteristic of device, will inevitably run into huge technology difficulty.More than based on
Reason, it is proposed that a kind of new HEMT device structure, this structure is capable of device threshold voltage and adjusts on a large scale, even
Realize enhancement device, and the frequency performance of device in the case of grid length is identical, can be effectively improved.
Summary of the invention
In view of deficiency of the prior art, it is an object of the invention to propose the hetero junction field effect crystal of a kind of new construction
Pipe, with the needs of satisfied actual application.
For achieving the above object, present invention employs following technical scheme:
A kind of HFET based on channel array structure, including hetero-junctions, described hetero-junctions include by
First semiconductor layer of top to bottm stacking setting and the second semiconductor layer, described first semiconductor layer and the second semiconductor layer interface
Place is formed with two-dimensional electron gas, and described first semiconductor layer is provided with source electrode, drain and gate, and described grid is arranged at source electrode
And between drain electrode, it is characterised in that:
It is formed with one or more raceway groove in hetero-junctions below described grid, and described electron channel two ends are respectively directed to source
Pole and drain electrode.
Further say, in the hetero-junctions below described grid, be provided with the raceway groove that the raceway groove being set up in parallel by plural number bar forms
Array.
The grid metal level for constituting grid is covered continuously on the upper surface of described raceway groove and two side.
Preferably, it is additionally provided with insulating barrier or oxide layer between upper surface and two side and the grid metal level of described raceway groove.
The width of described raceway groove is in 1nm～10 μm.
A described grid metal level select location between described raceway groove two ends extends into covering raceway groove near source electrode or leakage
On one end edge part of pole.
Described grid metal level is distributed between the two ends of described raceway groove.
Form Schottky contacts between described grid and hetero-junctions, MIM element contacts or metal-oxygen
Change layer-semiconductor contact.
Described HFET also includes field plate structure.
Described HFET uses planar isolated or mesa-isolated.
A kind of HFET based on channel array structure, including hetero-junctions, described hetero-junctions include by
First semiconductor layer of top to bottm stacking setting and the second semiconductor layer, described first semiconductor layer and the second semiconductor layer interface
Place is formed with two-dimensional electron gas, and described first semiconductor layer is provided with source electrode, drain and gate, and described grid is arranged at source electrode
And between drain electrode, it is characterised in that:
Being formed with one or more raceway groove in hetero-junctions below described grid, described raceway groove two ends are respectively directed to source electrode and leakage
The grid metal level for constituting grid is covered continuously on pole, and the upper surface of described raceway groove and two side；
Described first semiconductor layer and the second semiconductor layer are respectively the stratiform knot formed by least one semi-conducting material
Structure or the laminated construction formed by two or more semi-conducting materials or a combination thereof.
Described raceway groove is plural number bar, and it is set up in parallel formation channel array, and each channel width is in 1nm～10 μm.
Preferably, described first semiconductor layer is GaN, AlxGa1-xN、AlN、InxAl1-xN、InxAlyGa1-x-yN、
InxAl1-xAs、InxGa1-xAs、AlxGa1-xAs and InxAl1-xThe layer structure or any two that any one material in Sb is formed
Plant above material or the laminated construction of a combination thereof formation, wherein, 0≤x≤1,0≤Y≤1, and 0≤x+Y≤1.
Preferably, described second semiconductor layer is GaN, AlxGa1-xN、AlN、InxAl1-xN、InxAlyGa1-x-yN、
InxAl1-xAs、InxGa1-xAs、AlxGa1-xThe layer structure or the most two or more that any one material in As and InP is formed
The laminated construction that material or a combination thereof are formed, wherein, 0≤x≤1,0≤Y≤1, and 0≤x+Y≤1.
Certainly, aforementioned first semiconductor layer and the second semiconductor layer also can be by addition to above-mentioned materials, art technology
Other semi-conducting materials formation that personnel are known.
The operation principle of this new construction HFET is:
For single raceway groove, grid metal covers on raceway groove.Grid raceway groove is modulated except above from hang down
Nogata modulation upwards, also from the modulation of side wall both sides, because when channel width reduces, the grid from side wall both sides are adjusted
Control be can not ignore, thus forms ring matrix effect.This gate-all-around structure can bring following some impact:
(1) the grid modulation of the side wall that gate-all-around structure increases, will increase the ability of regulation and control of device, thus brings device transconductance
Increase, also bring the increase of gate capacitance simultaneously.By technique adjustment, make the increase more than gate capacitance of the mutual conductance increments, then can carry
Carry out the raising of device cut-off frequency；
(2) increase of grid-control ability, is applying in the case of same grid voltage compared to traditional devices, and channel structure will consumption
More two-dimensional electron gas, causes the positive excursion of device threshold voltage to the greatest extent；
(3) this gate-all-around structure makes the electric field of each raceway groove more uniformly, in this uniform electric field and the situation of high electric field
Under, the electronics in raceway groove can obtain bigger energy, and this may make phon scattering between the acoustical phonon in raceway groove and paddy become
Main scattering mechanism, and this scattering has very weak sensitivity to lattice temperature.Therefore, at high temperature new construction heterojunction field
Effect transistor can keep stable drain terminal saturation current.
Analyzing further, due to the introducing of raceway groove, the electric current of wall scroll raceway groove is much smaller compared to traditional devices, so dissipating
Heat is more preferable than traditional devices, therefore can effectively suppress self-heating effect present in tradition HFET.
(such as GaN material system) in the hetero-junctions of some strong polarization material, the two-dimensional electron gas in raceway groove is mainly by polarity effect
(piezoelectricity and spontaneous polarization) causes.And at trench edges, due to Stress Release, piezoelectric polarization effect disappears, raceway groove
This part two-dimensional electron gas that the interface at edge is caused by polarity effect also will disappear, so that the threshold voltage of device enters one
Step is to the forward drifted about.Finally, during as upper grid, due to the work function difference between grid metal and quasiconductor, side, ditch under the gate
The two-dimensional electron gas of road edge will be exhausted further, without grid device threshold voltage at negative sense very
Close to null value, the applying of grid metal the threshold voltage drift that may make device is become on the occasion of, thus form enhancement mode hetero-junctions
Field-effect transistor.
This new construction field-effect transistor can use traditional semiconductor microactuator process technology to complete, it is possible to use equipment
(set such as beamwriter lithography, ion beam lithography, immersion lithography, distributed exposure and optical exposure etc. including etching system
Standby), nano impression, etching apparatus (RIE, ICP etc.), ion implantation device etc..
Accompanying drawing explanation
Fig. 1 a is the three dimensional structure of Schottky gate HFET based on channel array structure in embodiment 1
Schematic diagram；
Fig. 1 b is the top view of Schottky gate HFET based on channel array structure in embodiment 1；
Fig. 1 c is the partial enlargement of Schottky gate HFET based on channel array structure in embodiment 1
Figure；
Fig. 2 is the cross-sectional view of the channel array of Schottky gate in Fig. 1；
Fig. 3 is the cross-sectional view of the channel array that MIM element (MIS) contacts in embodiment 2；
Fig. 4 is the Schottky gate HFET three dimensional structure schematic diagram of wall scroll raceway groove in embodiment 3；
Fig. 5 is the hetero junction field effect crystal that in embodiment 4, grid metal and channel array edge are overlapping near source electrode one end
The three dimensional structure schematic diagram of pipe；
Fig. 6 is the hetero junction field effect crystal that in embodiment 5, grid metal is overlapping near drain electrode one end with channel array edge
The three dimensional structure schematic diagram of pipe.
Detailed description of the invention
The HFET of the present invention, its core design thought is to use channel array structure, and it is tied substantially
Structure is as shown in Fig. 1 a～1c.Channel array, raceway groove battle array is produced between the source and drain of HFET, below grid
The structure of row is as in figure 2 it is shown, be to be formed by one or more channels connected in parallel.
Generally, it is achieved the technical scheme is that
New construction HFET based on channel array structure, at tradition HFET knot
Introducing channel array structure on the basis of structure, described channel array is by between source and drain, below grid or many
Individual channels connected in parallel is formed.
Specifically, described channel array structure is applicable to all based on two-dimensional electron gas work at heterojunction boundary
Semi-conductor electronic device.
The isolation of described HFET can use planar isolated or mesa-isolated.
Preferably, in described described channel array, channel width can be from several nanometers to several microns, i.e. 1nm～10
The scope of μm.
In described channel array, the plane geometric shape of raceway groove is regular shape or non-regular shape.
Described channel array, can be wall scroll raceway groove, it is also possible to be a plurality of raceway groove.
In described channel array, channel dimensions arranged side by side is same size or non-equal size；Channel shape arranged side by side
For same shape or non-equal shape.
Described grid metal covers on channel array.
Described grid metal and channel array edge near source or drain terminal while overlapping, or not with channel array
Edge overlaps.
Being shaped as of described grid metal is common, T-shaped or V-arrangement grid；Grid metal dimension is submicron or more large scale.
What described grid metal was formed with quasiconductor contacts can be Schottky contacts, or lets out to reduce grid further
Leakage current and the breakdown voltage of increase device, it would however also be possible to employ MIM element contact or metal-oxide layer-half
Conductor contacts.
Described heterojunction field effect transistor structure can not have field plate, or can add field plate to improve device yet
Breakdown voltage, improve device performance.
It should be noted that the heretofore described conducting channel known by raceway groove system those skilled in the art, in fact
It is the band being respectively directed to source electrode and drain electrode at the two ends being positioned at the formation of the hetero-junctions below described grid on border, this band two
Side is respectively equipped with the groove going deep into the second semiconductor layer from the first semiconductor layer, covers continuously on this band upper surface and two side simultaneously
If gate metal layer.And aforesaid channel array, it is i.e. the array structure being made up of some bands of parallel distribution.
For making substantial structure feature, implementation method and the beneficial effect of HFET of the present invention be easier to reason
Solve, below in conjunction with some preferred embodiments and accompanying drawing thereof, technical solution of the present invention is further non-limitingly described in detail.
Embodiment 1
Refering to Fig. 1 a, it is somebody's turn to do Schottky gate HFET based on channel array structure by heterogenous junction epitaxy material
Material (including quasiconductor 1 and quasiconductor 2), source electrode 3, drain electrode 4, channel array 5 and grid 6 form.Wherein, hetero-junctions is formed
Quasiconductor 1 and quasiconductor 2 can be any semi-conducting materials that can form two-dimensional electron gas 7 at hetero-junctions.In raceway groove
Two-dimensional electron gas 7 is adjusted control by grid 6, thus controls device and be in cut-off region, linear zone and saturation region.Raceway groove battle array
Row 5 are formed in parallel by multiple raceway grooves 8, in the active area between source electrode 3 and drain electrode 4, below grid 6.In the present embodiment,
Grid 6 is between channel array 5, and this can find out in Fig. 1 b and Fig. 1 c clearly.And as shown in Figure 2, grid metal 6 covers
Raceway groove 8 top and both sides, form gate-all-around structure and regulate and control hetero-junctions raceway groove.According to structure described in the present embodiment, with
As a example by AlGaN/GaN HEMT, using raceway groove 8 width is 70nm, totally 1000 channels connected in parallel, and grid 6 metal thickness is 300nm,
The a length of 300nm of grid 6, grid 6 and source electrode 3 spacing 2 m, the structure design of grid 6 and drain electrode 4 spacing 3 m, compared to tradition
The device of structure, it is possible to achieve threshold voltage is the AlGaN/GaN HEMT of 0.15V enhancement mode, and in the mutual conductance increasing of device
Add five times, in the case of parasitic gate capacitance increases twice, the cut-off frequency of device can be made at least to improve twice.
Embodiment 2
Refering to Fig. 3, quasiconductor 1 should be included, partly leads by insulation grid heterojunction field-effect transistor based on channel array structure
Body 2, insulating medium layer 9 and grid 6.Highdensity two-dimensional electron gas 7 is there is at heterojunction boundary.Insulating medium layer covers
Above channel array 5, topmost cover is that grid metal is with the two-dimensional electron gas in modulation raceway groove.Wherein, insulating medium layer can
To be oxide (such as silicon dioxide, aluminium sesquioxide, hafnium oxide etc.), it is also possible to be that non-medium of oxides layer is (such as silicon nitride, nitrogen
Change aluminum etc.).According to the present embodiment, as a example by AlGaN/GaN HEMT, between grid 6 metal and AlGaN, use the mode of ALD
Deposit a layer thickness is the Al of 10 nm2O3, grid leakage current can be made to reduce by four orders of magnitude, effectively enhance grid to ditch
The control ability in road.
Embodiment 3
Refering to Fig. 4, this wall scroll raceway groove HFET comprise quasiconductor 1, quasiconductor 2, source electrode 3, drain electrode 4,
Raceway groove 8 and grid 6.Highdensity two-dimensional electron gas 7 is there is at heterojunction boundary.This device is made up of wall scroll raceway groove 8, grid
Pole 6 covers the both sides at raceway groove 8, is modulated the two-dimensional electron gas 7 at heterogeneous interface.Source electrode 3 ground connection, drain electrode 4 adds forward
Voltage makes channel electrons flow to drain electrode 4 from source electrode 3.According to the present embodiment, as a example by AlGaN/GaN hetero-junctions, the width of raceway groove 8
Being 500 nm, grid 6 metal thickness is 300 nm, a length of 300 nm of grid 6, obtains device at VgsSaturated leakage during=1.5V
Electric current is 850mA/mm, and peak-peak mutual conductance is 195mS/mm, compared to tradition AlGaN/GaN HEMT device at VgsDuring=1.5V
Drain saturation current 570mA/mm, peak-peak mutual conductance is 155mS/mm.The drain saturation current of device and peak-peak mutual conductance are all
Increased.
Embodiment 4
Refering to Fig. 5, in the present embodiment, grid 10 and channel array 5 edge overlapping near source electrode 3.Whole crystal
Pipe is made up of heterogenous junction epitaxy material (including quasiconductor 1 and quasiconductor 2), source electrode 3, drain electrode 4, channel array 5 and grid 7.
Grid 7 is not located between channel array 5, but a part covers channel array 5, and another part covers at channel array
On active area between 5 and source electrode 3.Thus formed grid 7 and channel array 5 edge near source electrode 3 while the knot that overlaps mutually
Structure.According to the present embodiment, as a example by AlGaN/GaN HEMT device, in channel array 5, the width of wall scroll raceway groove 8 is 200nm, ditch
A length of 1 m in road 8, totally 1000, grid 10 metal thickness is 300nm, a length of 500nm of grid 10, covers at channel array 5
On a length of 300nm of grid 10 metal part.Channel array device increases by five times compared to the mutual conductance of traditional device, posts
In the case of raw gate capacitance increases twice, the cut-off frequency of device can be made at least to improve twice.
Embodiment 5
Refering to Fig. 6, grid 11 and channel array 5 edge overlapping near drain electrode 4 in the present embodiment.Whole transistor
It is made up of heterogenous junction epitaxy material (including quasiconductor 1 and quasiconductor 2), source electrode 3, drain electrode 4, channel array 5 and grid 11.Grid
Pole 11 is not located between channel array 5, but a part covers channel array 5, and another part covers at channel array 5
And on the active area between drain electrode 4.Thus formed grid 11 and channel array 5 edge near drain electrode 4 while the knot that overlaps mutually
Structure.According to this embodiment, as a example by AlGaN/GaN HEMT device, in channel array, the width of wall scroll raceway groove 8 is 200nm, ditch
A length of 1 m in road 8, totally 1000, grid 11 metal thickness is 300nm, a length of 500nm of grid 11, covers at channel array 5
On a length of 300nm of grid 11 metal part.Channel array device increases by five times compared to the mutual conductance of traditional device, posts
In the case of raw gate capacitance increases twice, the cut-off frequency of device can be made at least to improve twice.
Below the HFET of Schottky gate based on channel array structure is (embodiment 1, real respectively
Execute example 4 and embodiment 5), the field-effect transistor of the field-effect transistor (embodiment 3) of wall scroll raceway groove and insulated gate (real
Execute example 2) as a example by technical scheme is illustrated.And in actual design, channel array structure can apply to
There is field plate or there is no the HFET of field plate；Corresponding each raceway groove, channel dimensions arranged side by side can be identical chi
Very little or non-equal size；Shape can be same shape or non-equal shape.Therefore, above-described embodiment is only the explanation present invention's
Technology design and feature, its object is to allow person skilled in the art will appreciate that present disclosure and to implement according to this,
Can not limit the scope of the invention with this.All equivalence changes made according to spirit of the invention or modification, all answer
Contain within protection scope of the present invention.
Claims (8)
1. a HFET based on channel array structure, including hetero-junctions, described hetero-junctions includes by upper
The first semiconductor layer arranged to lower stacking and the second semiconductor layer, described first semiconductor layer and the second semiconductor interface
Be formed with two-dimensional electron gas, described first semiconductor layer be provided with source electrode, drain and gate, described grid be arranged at source electrode and
Between drain electrode, it is characterised in that: being provided with channel array in the hetero-junctions below described grid, described channel array is by plural number bar also
The raceway groove that width is 1nm～the 10 μm composition that row are arranged, the two ends of any of which raceway groove are pointed to source electrode and drain electrode respectively, and are appointed
Covering the grid metal level for constituting grid on the upper surface of one raceway groove and two side the most continuously, described grid metal level is from described ditch
A select location between two ends, road extends into covering raceway groove on one end edge part of source electrode or drain electrode.
HFET based on channel array structure the most according to claim 1, it is characterised in that described
First semiconductor layer and the second semiconductor layer have the layer structure formed by least one semi-conducting material or by two or more
The laminated construction that semi-conducting material or a combination thereof are formed.
3., according to the HFET based on channel array structure according to any one of claim 1-2, it is special
Levy and be between the upper surface of described raceway groove and two side and grid metal level to be additionally provided with insulating medium layer.
4., according to the HFET based on channel array structure according to any one of claim 1-2, it is special
Levy and be between described grid and hetero-junctions that formation Schottky contacts or MIM element contact.
HFET based on channel array structure the most according to claim 1, it is characterised in that described
HFET also includes field plate structure.
HFET based on channel array structure the most according to claim 1, it is characterised in that described
HFET uses planar isolated or mesa-isolated.
HFET based on channel array structure the most according to claim 1, it is characterised in that described
First semiconductor layer is GaN, AlxGa1-xN、AlN、InxAl1-xN、InxAlyGa1-x-yN、InxAl1-xAs、InxGa1-xAs、
AlxGa1-xAs and InxAl1-xLayer structure that any one material in Sb is formed or any two or more material or a combination thereof shape
The laminated construction become, wherein, 0≤x≤1,0≤Y≤1, and 0≤x+Y≤1.
HFET based on channel array structure the most according to claim 1, it is characterised in that described
Second semiconductor layer is GaN, AlxGa1-xN、AlN、InxAl1-xN、InxAlyGa1-x-yN、InxAl1-xAs、InxGa1-xAs、
AlxGa1-xThe layer structure of any one material formation in As and InP or any two or more material or a combination thereof are formed
Laminated construction, wherein, 0≤x≤1,0≤Y≤1, and 0≤x+Y≤1.
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| CN201410113967.0A CN103872121B (en) | 2011-04-02 | HFET based on channel array structure |
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| CN201410113967.0A CN103872121B (en) | 2011-04-02 | HFET based on channel array structure |
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| CN201110083011.7A Division CN102201442B (en) | 2011-04-02 | 2011-04-02 | Heterojunction field effect transistor based on channel array structure |
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