CN103856199B - One kind of pull-up devices on the data bus for - Google Patents

One kind of pull-up devices on the data bus for Download PDF

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CN103856199B
CN103856199B CN201210494059.1A CN201210494059A CN103856199B CN 103856199 B CN103856199 B CN 103856199B CN 201210494059 A CN201210494059 A CN 201210494059A CN 103856199 B CN103856199 B CN 103856199B
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pull
current source
source circuit
connected
sda
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CN103856199A (en
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邓洪波
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苏州新宏博智能科技股份有限公司
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Abstract

本发明提供一种用于数据总线上的上拉装置,所述数据总线包括一根串行数据线SDA,和一根串行时钟线SCL,所述串行数据线SDA和串行时钟线SCL分别连接一个上拉电流源电路。 The present invention provides a data bus for the pulling means, said data bus comprises a serial data line SDA, SCL, and a serial clock line, a serial data line SDA and a serial clock line SCL They are connected to a pull-up current source circuit. 通过采用电流源电路代替现有技术中的上拉电阻,彻底解决了由于上拉电阻降低,导致的I2C总线的低电平的最大值变大,从而影响通信速率和通信稳定性。 Pull circuit by using a current source in place of the prior art resistance solve large maximum low level due to the reduction of the I2C bus pull-up resistor, the lead, thus affecting the stability of communication rate and communication.

Description

一种用于数据总线上的上拉装置 One kind of pull-up devices on the data bus for

技术领域 FIELD

[0001] 本发明涉及串行通信总线领域,尤其是涉及一种自动恢复总线锁死的技术领域。 [0001] The present invention relates to a serial communication bus, and in particular relates to the technical field of automatic recovery bus deadlocks. 背景技术 Background technique

[0002] 在单片机某些通信系统中如I2C/SMbus接口总线中,有些需要外接上拉电阻(芯片内部结构为漏级/集电极开路),以I2C接口为例,I2C总线只需要由两根信号线组成,一根是串行数据线SDA,另一根是串行时钟线SCL。 [0002] In some communication systems, such as microcontroller I2C / SMbus interface bus, and some require external pull-up resistor (chip internal structure of drain / collector), I2C interface to an example, the I2C bus requires only two signal lines, a is the SDA serial data line, the other serial clock line SCL. 在系统中,I2C总线的典型接法如图1所示, 注意连接时需要共地。 In the system, I2C bus connection typically shown in Figure 1, needs to pay attention to common ground connection. 一般具有I2C总线的器件其SDA和SCL管脚都是漏极开路(或集电极开路)输出结构。 I2C bus devices generally have their SDA and SCL pins are open-drain (or open collector) output structure. 因此实际使用时,SDA和SCL信号线都必须要加上拉电阻Rp(Pull-Up Resistor)。 Therefore, when actual use, SDA, and SCL signal lines must pull-up resistor Rp (Pull-Up Resistor). 上拉电阻一般取值3〜10KQ。 Usually pull-up resistor value 3~10KQ.

[0003] 采用开漏结构的好处是:当总线空闲时,SDA和SCL两条信号线都保持高电平,不会消耗电流;电气兼容性好。 Benefits [0003] The open-drain structure is: When the bus is idle, SDA, and SCL lines remain high two signals, not consume current; good electrical compatibility. 上拉电阻接5V电源就能与5V逻辑器件接口,上拉电阻接3V 电源又能与3V逻辑器件接口;因为是开漏结构,所以不同器件的SDA与SDA之间、SCL与SCL之间可以直接相连,不需要额外的转换电路。 Pull-up resistor can be connected to the 5V logic supply 5V device interface, a pullup resistor can supply 3V and 3V logic device interface; because it is an open drain structure, between different devices SDA and SDA, and SCL SCL may between directly connected, no additional conversion circuit.

[0004] I2C总线的规范要求SDA/SCL的上升沿时间要小于1000US,下降沿为300US。 [0004] I2C bus specifications SDA / SCL rise time less than 1000US, the falling edge 300US. 同时, I2C总线要求总线上总的等效电容加起来小于400pf。 Meanwhile, I2C bus requires a total equivalent capacitance on the bus together less than 400pf. 由于受总线杂散、分布电容、电感的影响,通信距离越长,器件越多,则上升沿时间越长,通信速率/通信稳定性会下降,出错/丢包的概率会上升。 Due bus stray, distributed capacitance, influence of inductance, the longer the communication distance, the more the device, the longer the rise time, the communication rate / communication stability decreases, an error / loss probability will rise.

[0005] 如果降低上拉电阻的阻值,则低电平的最大值会变大,成为不可调和的矛盾,尤其是高速模式或是插拔式接口保护电路中带有串联电阻和TVS管。 [0005] If the reduced value of the pullup resistor, the maximum low level becomes large, becoming irreconcilable conflict, especially high-speed mode or pluggable interface protection circuit with a series resistor and TVS tube.

[0006] I2C总线的上升时间由上拉电阻Rp、端接电阻Rs、容性负载Cb等共同决定,在I2C总线上升时间确定时,上拉电阻Rp、端接电阻Rs、容性负载Cb的相互关系如图2所示。 [0006] I2C bus rise time of a pull-up resistor Rp of, terminating resistor Rs of, Cb capacitive load combine to determine, when the rise time is determined in the I2C bus, pull-up resistor Rp of, the resistance Rs of termination, the capacitive load Cb relationship as shown in FIG.

[0007] 由图2可知,I2C总线的上升时间主要由荣幸负载和上拉电阻决定,在端接电阻为一定数值时,1C总线上升时间tr近似与上啦电阻和容性负载的成绩成正比,在I2C总线上升时间保持不变时,若I2C总线的容性负载增加,为保证I2C总线的上升时间不便,需要减少上拉电阻的数值。 [0007] The rise time is mainly determined by the I2C bus can be seen in FIG. 2 and the load honored by the pull-up resistor, when the termination resistance value is constant, 1C bus rise time tr is approximately proportional to it and the resistive and capacitive load results , remains unchanged when the rise time I2C bus, I2C bus if the capacitive load increases, the rise time to ensure the I2C bus inconvenience, it is necessary to reduce the value of the pull-up resistor. 发明内容 SUMMARY

[0008] 为了解决上述技术问题,本发明公开了用于数据总线上的上拉装置。 [0008] To solve the above problems, the present invention discloses a means for pulling on the data bus.

[0009] 本发明所述一种用于数据总线上的上拉装置,所述数据总线包括一根串行数据线SDA,和一根串行时钟线SCL,所述串行数据线SDA和串行时钟线SCL分别连接一个上拉电流源电路。 [0009] The present invention is an apparatus for pulling on the data bus, said data bus comprises a serial data line SDA, and a serial clock line SCL, and a serial data line SDA string line clock line SCL are connected to a pull-up current source circuit.

[0010] 进一步的,所述上拉电流源电路包括至少两个晶体管。 [0010] Further, the pull-up current source circuit comprises at least two transistors. 第一晶体管和串行数据线SDA相连,第二晶体管和串行时钟线SCL相连。 A first transistor and a serial data line SDA is connected, is connected to the second transistor and a serial clock line SCL.

[0011] 进一步的,所述的两个晶体管为PNP型晶体管。 [0011] Further, the two transistors is a PNP type transistor.

[0012] 进一步的,所述上拉电流源电路还包括两个NPN型晶体管。 [0012] Further, the pull-up current source circuit further comprises two NPN transistor.

[0013] 进一步的,所述上拉电流源电路还包括一电阻,所述电阻和一NPN型晶体管相连, 可以调节所述上拉电流源电路的电流值。 [0013] Further, the pull-up current source circuit further comprises a resistor, the resistor and a NPN transistor connected to the pull-up current can be adjusted value of the current source circuit. [0〇14]进一步的,所述的数据总线上总的等效电容小于400pf。 [0〇14] Further, the total equivalent capacitance on the data bus is less than 400pf.

[0015] 进一步的,所述上拉电流源电路中流过各个晶体管的电流相等。 [0015] Further, the pull-up current source circuit flowing a current equal to the respective transistors.

[0016] 本发明的优点在于:本发明提供一种用于数据总线上的上拉装置,所述数据总线包括一根串行数据线SDA,和一根串行时钟线SCL,所述串行数据线SDA和串行时钟线SCL分别连接一个上拉电流源电路。 [0016] The advantage of the present invention is that: the present invention provides a data bus for the upper pulling means, said data bus comprises a serial data line the SDA, and a serial clock line SCL, the serial data line SDA and a serial clock line SCL are connected to a pull-up current source circuit. 通过采用电流源电路代替现有技术中的上拉电阻,彻底解决了由于上拉电阻降低,导致的I2C总线的低电平的最大值变大,从而影响通信速率和通信稳定性。 Pull circuit by using a current source in place of the prior art resistance solve large maximum low level due to the reduction of the I2C bus pull-up resistor, the lead, thus affecting the stability of communication rate and communication. 附图说明 BRIEF DESCRIPTION

[0017] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的有关本发明的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0017] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments for the present invention the figures are merely some embodiments of the present invention, those of ordinary skill in the art is concerned, without creative efforts, we can derive from these drawings other drawings.

[0018] 图1为现有技术中上拉电阻和I2C总线的连接电路图; [0018] FIG. 1 is a prior art circuit diagram of a pull-up resistor and connected to the I2C bus;

[0019] 图2为现有技术中上拉电阻、容性负载和I2C总线上升时间的关系图; [0019] FIG. 2 is a prior art pull-up resistor, the capacitive load and I2C bus rise time diagram;

[0020] 图3为本发明所述的上拉电流源电路与I2C总线的连接关系图。 [0020] FIG. 3 pull-up current source connected with the I2C bus circuit diagram of the present invention. 具体实施方式 Detailed ways

[0021] 本发明提供一种用于数据总线上的上拉装置,如图1所示,现有技术上拉电阻和12C总线的连接电路图,串行数据线SDA和串行时钟线SCL分别连接一个上拉电阻11和12,上拉电阻11和12的阻值范围为3 KQ〜1 OK Q。 [0021] The present invention provides a pull on means on the data bus, as shown, over the prior art circuit diagram of a pull-up resistor is connected and the 12C bus, a serial data line SDA and a serial clock line SCL connected FIG 1 a pull-up resistor 11 and 12, pull-up resistor 11 and the resistance range of 12 to 3 KQ~1 OK Q. 12C总线连接一总设备10,用于负责整个12C总线通信的调度工作,发起各种通信命令,I2C总线节点上还包括至少一个从设备20,用于接受主设备10的命令,进行相应的处理。 12C a total bus connection device 10, is responsible for scheduling the operation of the entire communication bus 12C, a command to initiate a variety of communication, on the I2C bus node further comprises at least one slave device 20, 10 for receiving the master's command, the corresponding process . [〇〇22] 由于I2C总线的规范要求SDA/SCL的上升时间要小于lOOOus,下降沿为300us<J2C 总线要求总线上总的等效电容加起来小于400pf。 [〇〇22] Since the I2C bus specifications SDA / SCL rise time is less than lOOOus, the falling edge 300us <J2C bus requires a total equivalent capacitance on the bus together less than 400pf. 由于受总线杂散/分布电容/电感的影响, 通信距离越长,器件越多,则上升沿时间越长,通信速率/通信稳定性会下降,出错/丢包的概率会上升。 Due to stray bus / distributed capacitance / inductance, the longer the communication distance, the more the device, the rising edge of the longer, the communication rate / communication stability decreases, an error / loss probability will rise. 如果降低上拉电阻的阻值,则低电平的最大值会变大,成为不可调和的矛盾, 尤其是高速模式或是插拔式接口保护电路中带有串联电阻和TVS管。 If the pull-up resistor to reduce the resistance, the maximum low level becomes large, becoming irreconcilable conflict, especially high-speed mode or pluggable interface protection circuit with a series resistor and TVS tube.

[0023] 本实施例采用一电流源电路来替代现有技术中的上拉电阻。 [0023] The present embodiment employs a current source circuit in place of the prior art pull-up resistor. 图3示出本发明所述的上拉电流源电路与I2C总线的连接关系图,本发明所述一种用于数据总线上的上拉装置, 所述数据总线包括一根串行数据线SDA,和一根串行时钟线SCL,所述串行数据线SDA和串行时钟线SCL分别连接一个上拉电流源电路。 Figure 3 shows a pull-up current source is connected with the I2C bus circuit diagram according to the present invention, the present invention provides a data bus for the pulling means, said data bus comprises a serial data line SDA , and a serial clock line SCL, the serial data line SDA and a serial clock line SCL are connected to a pull-up current source circuit.

[0024] 所述上拉电流源电路包括至少两个晶体管。 [0024] The pull-up current source circuit comprises at least two transistors. 图3示出的电流源电路中包括5个晶体管,其中晶体管221、晶体管222为PNP型晶体管,晶体管221和串行数据线SDA相连,晶体管222和串行时钟线SCL相连。 A current source circuit shown in FIG. 3 includes five transistors, transistor 221, transistor 222 is a PNP type transistor, and the transistor 221 is connected to the serial data line SDA, and the transistor 222 is connected to the serial clock line SCL. 所述上拉电流源电路还包括两个NPN型晶体管224和晶体管225, 其中晶体管224连接一电阻226,可以调节所述上拉电流源电路的电流值。 The pull-up current source circuit further comprises two NPN transistor 224 and transistor 225, transistor 224 which is connected to a resistor 226, can adjust the current value of the pull-up current source circuit. 晶体管225连接一PNP型晶体管,用于对所述上拉电流源电路进行调节。 Transistor 225 is connected a PNP type transistor for the pull-up current source circuit is adjusted. 本发明所述的数据总线上总的等效电容小于400pf,满足I2C总线的要求。 On the data bus of the present invention, the total equivalent capacitance is less than 400pf, meet the requirements of the I2C bus. 所述上拉电流源电路中流过各个晶体管的电流相等。 The pull-up current source circuit flowing a current equal to the respective transistors.

[0025]本发明的优点在于:本发明提供一种用于数据总线上的上拉装置,所述数据总线包括一根串行数据线SDA,和一根串行时钟线SCL,所述串行数据线SDA和串行时钟线SCL分别连接一个上拉电流源电路。 [0025] The advantage of the present invention is that: the present invention provides a data bus for the upper pulling means, said data bus comprises a serial data line the SDA, and a serial clock line SCL, the serial data line SDA and a serial clock line SCL are connected to a pull-up current source circuit. 通过采用电流源电路代替现有技术中的上拉电阻,彻底解决了由于上拉电阻降低,导致的I2C总线的低电平的最大值变大,从而影响通信速率和通信稳定性。 By using the pull current source circuit in place of the prior art resistance solve large maximum low level due to the reduction of the I2C bus pull-up resistor, the lead, thus affecting the stability of communication rate and communication. [〇〇26]应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅是为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施方式中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。 [〇〇26] It should be understood that while the present specification be described in terms of embodiments, but not every embodiment contains only a separate aspect, this narrative description only for the sake of clarity, those skilled in the specification should as a whole, each of the embodiments described technical solutions can be suitably combined to form other embodiments of the present art can be appreciated in the art.

[0027]上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明,它们并非用以限制本发明的保护范围,凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。 [0027] A series of the detailed description set forth above is merely for the feasibility of specifically described embodiments of the present invention, they are not intended to limit the scope of the present invention, who have not departing from the spirit of the present invention the equivalent skills made embodiment or changes be included within the scope of the present invention.

Claims (3)

1.一种用于数据总线上的上拉装置,所述数据总线包括一根串行数据线SDA,和一根串行时钟线SCL,其特征在于:所述串行数据线SDA和串行时钟线SCL连接一个上拉电流源电路,所述上拉电流源电路包括两个PNP型晶体管及两个NPN型晶体管,其中一个PNP型晶体管和串行数据线SDA相连,另一PNP型晶体管和串行时钟线SCL相连;所述上拉电流源电路还包括一电阻,所述电阻和其中一个NPN型晶体管相连以调节所述上拉电流源电路的电流值。 A data bus is used for the upper pulling means, said data bus comprises a serial data line SDA, and a serial clock line SCL, which is characterized in that: said serial data line SDA and a serial clock line SCL connected to a pull-up current source circuit, the pull-up current source circuit includes two transistors and two PNP NPN transistor, which is connected to a PNP transistor and the SDA serial data line, and a further PNP transistor serial clock line SCL connected; the pull-up current source circuit further comprises a resistor, the resistor and wherein a NPN transistor is connected to adjust a current value of the pull current source circuit.
2.根据权利要求1所述的上拉装置,其特征在于:所述的数据总线上总的等效电容小于400pf〇 The pull-up devices according to claim 1, wherein: said data bus is less than the total equivalent capacitance 400pf〇
3.根据权利要求1所述的上拉装置,其特征在于:所述上拉电流源电路中流过各个晶体管的电流相等。 The said pulling device of claim 1, wherein: said pull-up current source circuit flowing a current equal to the respective transistors.
CN201210494059.1A 2012-11-28 2012-11-28 One kind of pull-up devices on the data bus for CN103856199B (en)

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CN101150476A (en) * 2007-10-23 2008-03-26 中兴通讯股份有限公司 Bus realization method for point-to-point communication
CN101330580A (en) * 2007-06-18 2008-12-24 康佳集团股份有限公司 Flat television
US7514962B2 (en) * 2006-04-28 2009-04-07 Stmicroelectronics Pvt. Ltd. Configurable I2C interface
CN101432705A (en) * 2006-04-24 2009-05-13 爱特梅尔公司 High speed dual- wire communications device requiring no passive pullup components
CN101599055A (en) * 2009-07-24 2009-12-09 亮 原 Embedded isomerism CPU array system based on correlative bus

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1220795A (en) * 1997-01-30 1999-06-23 皇家菲利浦电子有限公司 Communications bus using different transmission rates
CN101432705A (en) * 2006-04-24 2009-05-13 爱特梅尔公司 High speed dual- wire communications device requiring no passive pullup components
US7514962B2 (en) * 2006-04-28 2009-04-07 Stmicroelectronics Pvt. Ltd. Configurable I2C interface
CN101330580A (en) * 2007-06-18 2008-12-24 康佳集团股份有限公司 Flat television
CN101150476A (en) * 2007-10-23 2008-03-26 中兴通讯股份有限公司 Bus realization method for point-to-point communication
CN101599055A (en) * 2009-07-24 2009-12-09 亮 原 Embedded isomerism CPU array system based on correlative bus

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